CN2738454Y - Capacity charging circuit with soft starting function - Google Patents
Capacity charging circuit with soft starting function Download PDFInfo
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- CN2738454Y CN2738454Y CN 200420074065 CN200420074065U CN2738454Y CN 2738454 Y CN2738454 Y CN 2738454Y CN 200420074065 CN200420074065 CN 200420074065 CN 200420074065 U CN200420074065 U CN 200420074065U CN 2738454 Y CN2738454 Y CN 2738454Y
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- 238000007600 charging Methods 0.000 title claims description 82
- 238000004804 winding Methods 0.000 claims abstract description 80
- 239000003990 capacitor Substances 0.000 claims description 57
- 238000001514 detection method Methods 0.000 claims description 22
- 230000007423 decrease Effects 0.000 abstract 1
- 238000010586 diagram Methods 0.000 description 22
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- 230000010355 oscillation Effects 0.000 description 2
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Abstract
When first winding current increases to the upper limit of the current which is initialized by reference voltage which has a soft start characteristic, a power switch switches to a disconnection state. When second winding current decreases to the lower limit of the current which is initialized by another scheduled reference voltage, the power switch switches to a connection state. A minimum connection time limitation unit prevents the power switch switching to the disconnection state before the minimum connection time expires. The minimum connection time has a soft start modulating characteristic. A minimum disconnection time limitation unit prevents the power switch switching to the connection state before the minimum disconnection time expires. A connection time maximal limitation unit prevents the power switch still being in the connection state after the maximal connection time expires.
Description
[technical field]
The utility model relates to a kind of charging circuit, relates in particular to a kind of capacitor charging circuit with soft start function, can be applied to the capacitor of flash lamp of digital camera efficiently or other have the capacity load of broad charge voltage range.
[background technology]
In the flashing light system of digital camera, utilize about 3 volts cell voltage to charge for capacitor of flash lamp via transformer, make its terminal voltage rise to hundreds of volts, required high voltage when providing photoflash lamp to light from zero volt.United States Patent (USP) the 6th, 411, No. 064, the 6th, 417, No. 649, the 6th, 518, No. 733 and the 6th, 636, No. 021 etc. the prior art document has disclosed various electric capacity charging methods and circuit, can be applicable to have the capacity load of broad charge voltage range.Aforementioned documents is incorporated in this specification as a reference.Yet above-mentioned various prior aries still have many shortcomings, and need to improve further and innovation.
At first, beginning the charging initial stage, a winding of excessive inrush current meeting inflow transformer makes big relatively store energy in transformer.Yet, since the terminal voltage of capacity load is almost nil, so need considerable time stored energy could be sent to capacity load via secondary winding.As a result, the charge efficiency that begins the initial stage of charging is quite low, influences the normal operation of charging system.
When the power switch that is coupled in a winding when carrying out the on/off handover operation, once winding current and secondary winding electric current take place significantly to vibrate up and down unavoidablely.Because once winding current and secondary winding electric current so this vibration noise may mislead the current detecting result, and destroy desired charging controlling mechanism in order to the switching time of decision power switch.
Along with battery uses for a long time, cell voltage may descend significantly.Because being transformed into the opportunity of disconnection from connection, power switch controls, so low excessively cell voltage certainly will cause once winding current just can rise to upper current limit through after considerable time via making once winding current increase to a upper current limit.As a result, the cycle stretch-out of each charging cycle causes the pulsation of output voltage excessive or charge efficiency is reduced, and influences the normal operation of charging system.
[utility model content]
Because foregoing problems, a purpose of the present utility model is to provide a kind of capacitor charging circuit, can reduce inrush current and improves the charge efficiency of initial start stage.
Another purpose of the present utility model is to provide a kind of capacitor charging circuit, can avoid the current detecting result to be subjected to the current oscillation noise and mislead.
Another purpose of the present utility model is to provide a kind of capacitor charging circuit, can prevent that charging operations is subjected to the influence that cell voltage reduces.
According to an aspect of the present utility model, a kind of capacitor charging circuit is provided, make cell voltage charge for capacity load in order to control transformer via this transformer.Cell voltage is coupled in a winding of transformer.Capacity load is coupled in the secondary winding of transformer.
Capacitor charging circuit comprises a power switch, an on-off controller and a soft starting circuit.Power switch is coupled in winding one time, makes in the turn-on time of power switch the circulation that allows once winding current, and stops the circulation of once winding current in the opening time of power switch.The turn-on time and the opening time of on-off controller power controlling switch.Beginning the charging initial stage, the turn-on time of soft starting circuit modulation power switch, it is being increased gradually.Therefore, can reduce inrush current according to capacitor charging circuit of the present utility model and improve the charge efficiency of initial start stage.
First current detection circuit detects once winding current, and produces the primary current detection signal.Reference voltage generator is controlled by soft starting circuit and is produced a soft-start reference voltage.First voltage comparator is primary current detection signal and soft-start reference voltage relatively, and export one turn-on time termination signal to on-off controller.Second current detection circuit detects the secondary winding electric current, and produces the secondary current detection signal.Second voltage comparator is a secondary current detection signal and a predetermined reference voltage relatively, and export one opening time termination signal to on-off controller.
Minimal turn-on time restriction unit is coupled in the on-off controller or first voltage comparator, prevents that power switch from switching to off-state before the minimal turn-on time expires.Preferably, minimal turn-on time restriction unit is controlled and is modulated the minimal turn-on time by soft starting circuit, and it is increased gradually beginning the charging initial stage.Minimum limiting unit opening time is coupled in the on-off controller or second voltage comparator, prevents that power switch from switching to on-state before expiring a minimum opening time.Therefore, can avoid the current detecting result to be subjected to the current oscillation noise according to capacitor charging circuit of the present utility model misleads.
Maximum limiting unit turn-on time is coupled in on-off controller, prevents that power switch still is maintained at on-state after expiring a maximum turn-on time.Therefore, can prevent that according to capacitor charging circuit of the present utility model charging operations is subjected to the influence that cell voltage reduces.
[description of drawings]
Fig. 1 shows the circuit block diagram according to the capacitor charging circuit of the utility model first embodiment.
Fig. 2 (a) shows the detailed circuit diagram according to an example of soft starting circuit of the present utility model.
Fig. 2 (b) shows the detailed circuit diagram according to an example of reference voltage generator of the present utility model.
Fig. 2 (c) shows the detailed circuit diagram according to an example of minimal turn-on time restriction of the present utility model unit.
Fig. 2 (d) shows the detailed circuit diagram according to an example of maximum of the present utility model limiting unit turn-on time.
Fig. 2 (e) shows the detailed circuit diagram according to an example of minimum of the present utility model limiting unit opening time.
Fig. 2 (f) shows the detailed circuit diagram according to an example of on-off controller of the present utility model.
Fig. 3 shows the sequential chart according to the soft start charge waveforms of capacitor charging circuit of the present utility model.
Fig. 4 shows according to the once winding current of capacitor charging circuit of the present utility model and the waveform sequential chart of secondary winding electric current.
Fig. 5 shows the sequential chart according to the charge waveforms of capacitor charging circuit reply cell voltage of the present utility model change.
Fig. 6 shows the circuit block diagram according to the capacitor charging circuit of the utility model second embodiment.
Fig. 7 (a) shows the detailed circuit diagram according to an example of the voltage comparator of the utility model second embodiment.
Fig. 7 (b) shows the detailed circuit diagram according to an example of the voltage comparator of the utility model second embodiment.
Fig. 7 (c) shows the detailed circuit diagram according to an example of the on-off controller of the utility model second embodiment.
[embodiment]
Explanation hereinafter and accompanying drawing will make aforementioned and other purposes of the present utility model, feature, more obvious with advantage.Below with reference to the preferred embodiment of the present utility model of graphic detailed description foundation.
Fig. 1 shows the circuit block diagram according to capacitor charging circuit 10 of the present utility model.With reference to Fig. 1, under the on/off handover operation of power switch SW, cell voltage V
BatBe adjusted to output voltage V via transformer 11
Out, in order to for capacity load C
LoadCharging.In an embodiment of the present utility model, power switch SW is implemented by the nmos pass transistor that the high-voltage semi-conductor processing procedure is produced.One time winding L 1 is designed to have reciprocal polarity with secondary winding L2, and is indicated as the stain of Fig. 1, so transformer 11 belongs to (Flyback) kenel of flybacking.When power switch SW is in on-state, cell voltage V
BatSupply once winding current I
Pri, with storage power in transformer 11.At this moment, secondary winding electric current I
SecBe zero, and capacity load C
LoadTerminal voltage keep fixing.When power switch SW is in off-state, cell voltage V
BatStop supplies once winding current I
PriAt this moment, be stored in the energy of transformer 11 via the secondary winding electric current I
SecFor capacity load C
LoadCharging is to improve its terminal voltage V
OutBe arranged at secondary winding L2 and capacity load C
LoadBetween diode D only allow electric current I
SecFor capacity load C
LoadCharging, and prevent capacity load C
LoadReverse secondary winding L2 is discharged.
Based on once winding current I
PriWith the secondary winding electric current I
SecVariation, on-off controller 12 produces a switch controlling signal DRV, in order to the on/off operation of decision power switch SW.Particularly, current detector 13 detects once winding current I
Pri, in order to produce primary current detection signal V
PriPrimary current detection signal V
PriBe coupled to the non-inverting input of voltage comparator 15.14 output of reference voltage generator soft-start reference voltage V
RsInverting input to voltage comparator 15.When power switch SW was in on-state, energy was from cell voltage V
BatBe passed to transformer 11, so primary current detection signal V
PriContinue to increase from zero.As primary current detection signal V
PriIncrease to and equal soft-start reference voltage V
RsThe time, termination signal V turn-on time that voltage comparator 15 is produced
OnBecome high level from low transition, trigger switch controller 12 so that power switch SW finish on-state and enter off-state.As a result, once winding current I
OriBe terminated to zero.Based on the effect of induced electromotive force, the secondary winding electric current I
SecJump to by once winding current I before stopping from zero
PriThe value that is determined with ratio of winding L2/L1.
Power switch SW be in off-state during in, the secondary winding electric current I
SecTo capacity load C
LoadThe charging and continue to reduce.Via series resistance R
SecDetect the secondary winding electric current I
SecTo produce secondary current detection signal V
SecSecondary current detection signal V
SecBe coupled to the non-inverting input of voltage comparator 16, and reference voltage V
rThen be coupled to the inverting input of voltage comparator 16.When the secondary winding electric current I
SecTermination signal V opening time that reduces gradually and voltage comparator 16 is produced
OffWhen low transition became high level, on-off controller 12 was triggered and makes power switch SW finish off-state and enter on-state.As a result, secondary winding electric current I
SecBe terminated to zero.Based on the effect of induced electromotive force, once winding current I
PriJump to by secondary winding current I before stopping from zero
SecThe value that is determined with ratio of winding L1/L2.Subsequently, repeat each step of above stated specification and proceed next charging cycle.
In an embodiment of the present utility model, current detector 13 is implemented by a series connection resistance.In another embodiment of the present utility model, current detector 13 is applied for by the applicant and in No. the 1517714th, disclosed Chinese disclosure of the Invention communique on August 4th, 2004, denomination of invention is implemented for " current detection circuit of high-speed driving level " disclosed current detection circuit.Aforementioned documents is also incorporated in this specification as a reference.
More be provided with a soft starting circuit 17 and a time limiter 18 according to capacitor charging circuit 10 of the present utility model, with intensified charging efficient.Soft starting circuit 17 is exported soft-start signal SS to reference voltage generator 14 and time restriction device 18 in response to charge command signal CH.Reference voltage generator 14 is exported soft-start reference voltage V in response to soft-start signal SS
RsTo voltage comparator 15.Time restriction device 18 is in response to soft-start signal SS and switch controlling signal DRV and export minimal turn-on time restriction signal T
On Min, maximum turn-on time restricting signal T
On Max, and minimum opening time restricting signal T
Off MinTo on-off controller 12.
Fig. 2 (a) shows the detailed circuit diagram according to an example of soft starting circuit 17 of the present utility model.When charge command signal CH is in low level, inverter N
sThe output high level signal makes nmos pass transistor Q
sConducting.As a result, soft-start signal SS is coupled to earth potential.When charge command signal CH is in high level so that capacitor charging circuit 10 when beginning to carry out charging procedure, inverter N
sThe output low level signal makes nmos pass transistor Q
sNot conducting.Current source I
sTo capacitor C
sCharging makes soft-start signal SS rise gradually up to forward pressure drop (Forward Bias Drop) the institute's clamp (Clamp) by diode D1 and D2 from earth potential.
Fig. 2 (b) shows the detailed circuit diagram according to an example of reference voltage generator 14 of the present utility model.With reference to Fig. 2 (b), soft-start signal SS is coupled to first non-inverting input, the predetermined reference voltage V of voltage comparator CP
R1Be coupled to second non-inverting input of voltage comparator CP, the output control nmos pass transistor Q of voltage comparator CP
V1Grid and nmos pass transistor Q
V1Source-coupled to the inverting input of voltage comparator CP.In one embodiment, reference voltage V
R1Set stationary value (for example, the diode D1 of the stationary value of soft-start signal SS shown in Fig. 2 (a) and the forward pressure drop of D2) for less than soft-start signal SS.PMOS transistor Q
V2With Q
V3Constitute a current mirror, wherein transistor Q
V2Drain coupled in transistor Q
V1Drain electrode and transistor Q
V3Drain coupled to resistance R 2 to produce soft-start reference voltage V
RsTherefore, when soft-start signal SS less than reference voltage V
RlThe time, soft-start reference voltage V
RsRise gradually along with the increase of soft-start signal SS.When soft-start signal SS surpasses reference voltage V
R1The time, soft-start reference voltage V
RsThen change by reference voltage V
R1Determine and be fixed in a stationary value.
In an embodiment of the present utility model, time restriction device 18 comprises a minimal turn-on time restriction unit 18-1, maximum limiting unit 18-2 turn-on time and minimum limiting unit 18-3 opening time, produces minimal turn-on time restriction signal T respectively
On Min, maximum turn-on time restricting signal T
On Max, and minimum opening time restricting signal T
Off MinFig. 2 (c) shows the detailed circuit diagram according to the example of minimal turn-on time restriction unit 18-1 of the present utility model.Fig. 2 (d) shows the detailed circuit diagram according to the example of maximum of the present utility model limiting unit 18-2 turn-on time.Fig. 2 (e) shows the detailed circuit diagram according to the example of minimum of the present utility model limiting unit 18-3 opening time.
With reference to Fig. 2 (c), when switch controlling signal DRV is in low level and when making power switch SW operate in off-state, inverter N1 output high level signal makes nmos pass transistor Q1 conducting.As a result, the non-inverting input of voltage comparator CP1 is coupled to earth potential, and output minimal turn-on time restriction signal T
On MinLow level.In case switch controlling signal DRV is transformed into high level and when making power switch SW enter on-state, inverter N1 output low level signal makes not conducting of nmos pass transistor Q1 from low level.In the case, current source I1 is to capacitor C 1 charging, finally makes the non-inverting input voltage of voltage comparator CP1 greater than inverting input voltage, and output minimal turn-on time restriction signal T
On MinHigh level.From hereinafter as can be known, as minimal turn-on time restriction signal T about the detailed description of on-off controller 12
On MinWhen being in low level, switch controlling signal DRV is restricted to high level so that power switch SW is maintained at on-state.Therefore, from switch controlling signal DRV by low level be transformed into high level the time start at up to minimal turn-on time restriction signal T
On MinOccur high level the time till, during this promptly according to the operated minimal turn-on time of power switch SW of the present utility model.
Please note according to minimal turn-on time restriction unit 18-1 of the present utility model and determine when to produce minimal turn-on time restriction signal T based on soft-start signal SS
On MinHigh level, use for the minimal turn-on time and also carry out soft start modulation.Shown in Fig. 2 (c), soft-start signal SS is coupled in the grid of PMOS transistor Q2, and I2 is supplied to capacitor C 1 with the Control current source.When soft-start signal SS when earth potential rises to stationary value gradually, current source I2 reduces its part that is supplied to capacitor C 1 gradually because PMOS transistor Q2 and Q3 are constituted differential to (Differential Pair) according to soft-start signal SS and reference voltage V
R2Ratio and distribute the flow through each several part of PMOS transistor Q2 and Q3 of current source I2.In other words, at the initial stage that capacitor charging circuit 10 begins to charge, soft-start signal SS is much smaller than reference voltage V
R2, make current source I2 almost completely charge for capacitor C 1 via transistor Q2.In the case, the terminal voltage of capacitor C 1 rises with big speed, makes minimal turn-on time restriction signal T
On MinMore early be transformed into high level, that is the minimal turn-on time that minimal turn-on time restriction unit 18-1 sets is shorter.SS rises gradually along with soft-start signal, and current source I2 is used for the part of capacitor C 1 charging is reduced gradually, makes minimal turn-on time restriction signal T
On MinThe more late high level that is transformed into, that is the minimal turn-on time that minimal turn-on time restriction unit 18-1 sets is longer.Therefore, the minimal turn-on time that sets according to minimal turn-on time restriction unit 18-1 of the present utility model has from minimum value and increases to peaked soft start modulation signature gradually.
With reference to Fig. 2 (d), when switch controlling signal DRV is in low level and when making power switch SW operate in off-state, inverter N2 output high level signal makes nmos pass transistor Q4 conducting.As a result, the non-inverting input of voltage comparator CP2 is coupled to earth potential, and output maximum turn-on time of restricting signal T
On MaxLow level.In case switch controlling signal DRV is transformed into high level and when making power switch SW enter on-state, inverter N2 output low level signal makes not conducting of nmos pass transistor Q4 from low level.In the case, current source I3 finally makes the non-inverting input voltage of voltage comparator CP2 export maximum restricting signal T turn-on time greater than inverting input voltage to capacitor C 2 chargings
On MaxHigh level.From hereinafter as can be known about the detailed description of on-off controller 12, maximum turn-on time restricting signal T
On MaxHigh level trigger switch control signal DRV become low level, make power switch SW switch to off-state.Therefore, from switch controlling signal DRV by low level be transformed into high level the time start at up to maximum turn-on time of restricting signal T
On MaxTill occurring in the high level, it during this operated maximum turn-on time of foundation power switch SW of the present utility model.
With reference to Fig. 2 (e), when switch controlling signal DRV is in high level and when making power switch SW operate in on-state, nmos pass transistor Q5 conducting makes the non-inverting input of voltage comparator CP3 be coupled to earth potential, and output minimum opening time of restricting signal T
Off MinLow level.In case switch controlling signal DRV is transformed into low level and when making power switch SW enter off-state, not conducting of nmos pass transistor Q5 makes current source I4 to capacitor C 3 chargings from high level.In the case, when non-inverting input voltage during finally greater than inverting input voltage, voltage comparator CP3 output minimum opening time of restricting signal T
Off MinHigh level.From hereinafter as can be known, as minimum opening time of restricting signal T about the detailed description of on-off controller 12
Off MinWhen being in low level, switch controlling signal DRV is restricted to low level so that power switch SW is maintained at off-state.Therefore, be transformed into by high level from switch controlling signal DRV and start in the low level up to minimum opening time of restricting signal T
Off MinTill occurring in the high level, it during this operated minimum opening time of foundation power switch SW of the present utility model.
Fig. 2 (f) shows the detailed circuit diagram according to an example of on-off controller 12 of the present utility model.With reference to Fig. 2 (f), on-off controller 12 is logic control circuits, comprises two AND gate A1 and A2, an OR gate O1 and a SR latch LA.Two inputs of AND gate A1 are respectively in order to receive termination signal V turn-on time
OnWith minimal turn-on time restriction signal T
On MinTwo inputs of AND gate A2 are respectively in order to receive minimum restricting signal T opening time
Off MinWith termination signal V opening time
OffTwo inputs of OR gate O1 are coupled in the output and maximum restricting signal T turn-on time of AND gate A1 respectively
On MaxThe input R that resets of SR latch LA is that output, the set input S that is coupled in OR gate O1 is that output and the noninverting output Q that is coupled in AND gate A2 provides required switch controlling signal DRV.
Describe in detail according to the operation of capacitor charging circuit 10 of the present utility model as follows with reference to Fig. 3 to 5 below with the excellent results of being reached.Fig. 3 shows the sequential chart according to the soft start charge waveforms of capacitor charging circuit 10 of the present utility model.Fig. 4 shows the once winding current I according to capacitor charging circuit 10 of the present utility model
PriWith the secondary winding electric current I
SecThe waveform sequential chart.Fig. 5 shows according to capacitor charging circuit 10 reply cell voltage V of the present utility model
BatThe sequential chart of the charge waveforms of change.
With reference to Fig. 3, charge command signal CH is transformed into high level from low level, makes capacitor charging circuit 10 begin to carry out charging operations.Soft-start signal SS rises to stationary value gradually from earth potential.Soft-start reference voltage V
RsSS rises gradually along with soft-start signal, and than the more Zao stationary value that reaches of soft-start signal SS.Soft-start reference voltage V
RsStationary value set stationary value for less than soft-start signal SS.At soft-start reference voltage V
RsBe to be defined as between the soft start charge period charging period that reaches before the stationary value, and at soft-start reference voltage V
RsThe charging that reaches after the stationary value then is defined as during the constant charge period.In between the soft start charge period, the high level time of switch controlling signal DRV in each charging cycle (that is corresponding to power switch SW turn-on time) is along with soft-start reference voltage V
RsRising and increase gradually.During constant charge, in each charging cycle the high level time of switch controlling signal DRV then keep fixing because soft-start reference voltage V
RsReached stationary value.Owing to have the soft start modulation signature that increases gradually the turn-on time of power switch SW, prevent a winding of excessive inrush current inflow transformer according to capacitor charging circuit 10 of the present utility model effectively.As a result, the energy that is stored in each charging cycle in the transformer 11 is relatively little, only need spend a small amount of time can be sent to capacity load C
LoadEven when the terminal voltage of capacity load is almost nil, also be like this.Thereby capacitor charging circuit 10 of the present utility model improves the charge efficiency of initial start stage effectively.
With reference to Fig. 4, when switch controlling signal DRV is in high level, because energy is from cell voltage V
BatBe sent to transformer 11 and make once winding current I
PriIncrease, at this moment the secondary winding electric current I
SecBe zero.When switch controlling signal DRV is in low level, because energy is sent to capacity load C from transformer 11
LoadAnd make the secondary winding electric current I
SecReduce, at this moment once winding current I
PriBe zero.When high and low level transition take place switch controlling signal DRV, that is power switch SW carries out on/off when switching, once winding current I
PriWith the secondary winding electric current I
SecProduce the noise that significantly vibrates up and down.This kind vibration noise may mislead the current detecting result, and can't reach correct on/off handover control mechanism for power switch SW.
For fear of the vibration interference of noise, be provided with minimal turn-on time restriction signal T according to capacitor charging circuit 10 of the present utility model
On MinWith minimum restricting signal T opening time
Off MinCan know from Fig. 4 and to find out that switch controlling signal DRV caused vibration noise when low level changes high level into betides minimal turn-on time restriction signal T fully
On MinStill be in low level period.In the case, shown in Fig. 2 (f), no matter turn-on time termination signal V
OnHow changing, the output of AND gate A1 all is maintained at low level, switches to low level thereby the noise that prevents from effectively to vibrate misleads switch controlling signal DRV.Moreover switch controlling signal DRV caused vibration noise when high level changes low level into betides minimum opening time of restricting signal T fully
Off MinStill be in low level period.In the case, shown in Fig. 2 (f), no matter opening time termination signal V
OffHow changing, the output of AND gate A2 all is maintained at low level, switches to high level thereby the noise that prevents from effectively to vibrate misleads switch controlling signal DRV.
Subsidiary one carries, between the soft start charge period in, the once winding current I of each charging cycle
PriMaximum become gradually greatly, this is because soft-start reference voltage V
RsDue to increasing gradually.Yet, during constant charge in because soft-start reference voltage V
RsReached stationary value, so the once winding current I of each charging cycle
PriMaximum keep fixing.
With reference to Fig. 5, at cell voltage V
BatUnder the normal situation, when switch controlling signal DRV is in high level, once winding current I
PriRise with normal speed.As once winding current I
PriReach by soft-start reference voltage V
RsDuring the upper current limit that determined, turn-on time termination signal V
OnMake switch controlling signal DRV be transformed into low level via on-off controller 12, as previously mentioned.Along with battery uses for a long time, cell voltage V
BatMay descend significantly.At cell voltage V
BatCross under the low situation, when switch controlling signal DRV is in high level, once winding current I
PriClimbing speed become very slow.If still must wait for once winding current I
PriJust can make switch controlling signal DRV be transformed into low level when reaching upper current limit, then the cycle stretch-out of each charging cycle may cause the pulsation of output voltage excessive, charge efficiency is reduced and influences the normal operation of total system.
For fear of this shortcoming, be provided with maximum restricting signal T turn-on time according to capacitor charging circuit 10 of the present utility model
On MaxWhen the time that switch controlling signal DRV is in high level is reached predetermined maximum turn-on time, even once winding current I
PriDo not reach upper current limit yet, maximum restricting signal T turn-on time
On MaxCan make switch controlling signal DRV be transformed into low level via on-off controller 12.Therefore, prevent effectively that according to capacitor charging circuit 10 of the present utility model normal circuit operation is subjected to the influence that cell voltage reduces.
Fig. 6 shows the circuit block diagram according to the capacitor charging circuit 10 ' of the utility model second embodiment.The first embodiment capacitor charging circuit, 10 parts that the second embodiment capacitor charging circuit 10 ' of Fig. 6 is different from Fig. 1 are: (1) minimal turn-on time restriction unit 18-1 output minimal turn-on time restriction signal T
On MinTo voltage comparator 15 ', prevent termination signal V turn-on time
On' before expiring, the minimal turn-on time becomes low level; (2) minimum limiting unit 18-3 output opening time minimum opening time of restricting signal T
Off MinTo voltage comparator 16 ', prevent termination signal V opening time
Off' before expiring minimum opening time, become low level; And (3) on-off controller 12 ' is in response to termination signal V turn-on time
On', opening time termination signal V
Off' and maximum restricting signal T turn-on time
On MaxAnd generation switch controlling signal DRV.
Fig. 7 (a) shows the detailed circuit diagram according to an example of the voltage comparator 15 ' of the utility model second embodiment.With reference to Fig. 7 (a), voltage comparator 15 ' be coupled in via a switching transistor Q6 and an inverter N3 Fig. 1 voltage comparator 15 non-inverting input and form.As minimal turn-on time restriction signal T
On MinWhen being in low level, inverter N3 output high level is with actuating switch transistor Q6.As a result, the non-inverting input of voltage comparator 15 is coupled in earth potential.In the case, turn-on time termination signal V
OnBe constrained to low level, avoid the interference of noise of vibrating effectively.Expire and minimal turn-on time restriction signal T when the minimal turn-on time
On MinHigh level when occurring, inverter N3 output low level and can't actuating switch transistor Q6.As a result, the non-inverting input of voltage comparator 15 reverts to again and receives primary current detection signal V
Pri, to carry out normal comparing function.
Fig. 7 (b) shows the detailed circuit diagram according to an example of the voltage comparator 16 ' of the utility model second embodiment.With reference to Fig. 7 (b), voltage comparator 16 ' be coupled in via a switching transistor Q7 and an inverter N4 Fig. 1 voltage comparator 16 non-inverting input and form.As minimum restricting signal T opening time
Off MinWhen low level, inverter N4 output high level is with actuating switch transistor Q7.As a result, the non-inverting input of voltage comparator 16 is coupled in earth potential.In the case, opening time termination signal V
OffBe constrained to low level, avoid the interference of noise of vibrating effectively.Expire and minimum restricting signal T opening time when minimum opening time
Off MinHigh level when occurring, inverter N4 output low level and can't actuating switch transistor Q7.As a result, the non-inverting input of voltage comparator 16 reverts to again and receives secondary current detection signal V
Sec, to carry out normal comparing function.
Fig. 7 (c) shows the detailed circuit diagram according to an example of the on-off controller 12 ' of the utility model second embodiment.As previously mentioned, because turn-on time termination signal V
On' before the minimal turn-on time expires, be limited to low level, so turn-on time termination signal V
On' be equivalent to the output signal of the AND gate A1 of Fig. 2 (f) in logic.In like manner, because opening time termination signal V
Off' before expiring minimum opening time, be limited to low level, so opening time termination signal V
Off' be equivalent to the output signal of the AND gate A2 of Fig. 2 (f) in logic.Therefore, in the on-off controller 12 ' of Fig. 7 (c), two inputs of OR gate O1 are coupled in termination signal V turn-on time respectively
On' and maximum restricting signal T turn-on time
On MaxOutput, the set input S that input R is coupled in OR gate O1 that reset of SR latch LA is coupled in termination signal V opening time
Off' and noninverting output Q required switch controlling signal DRV is provided.
Though the utility model is illustrated as illustration via preferred embodiment, it should be understood that the utility model is not limited thereto the disclosed embodiment in place.On the contrary, to be intended to contain be tangible various modification and similar configuration to the utility model for a person skilled in the art.Therefore, the scope of claim should be according to the widest annotation, and this type of is revised and similar configuration to contain all.
Claims (10)
1. capacitor charging circuit, make a voltage source via this transformer capacity load that charges in order to control a transformer, wherein this voltage source is coupled in a winding of this transformer and this capacity load is coupled in the secondary winding of this transformer, and this capacitor charging circuit comprises:
One power switch is coupled in this winding, makes in the turn-on time of this power switch the circulation that allows once winding current, and stops the circulation of once winding current in the opening time of this power switch;
One on-off controller is in order to control this turn-on time and this opening time; And
One soft starting circuit in order to modulate this turn-on time beginning the charging initial stage, increases it gradually.
2. capacitor charging circuit as claimed in claim 1 also comprises:
One first current detection circuit is in order to detect this once winding current, to produce the primary current detection signal;
One reference voltage generator is controlled by this soft starting circuit and is produced a soft-start reference voltage; And
One first voltage comparator, in order to relatively this primary current detection signal and this soft-start reference voltage, with export one turn-on time termination signal to this on-off controller.
3. capacitor charging circuit as claimed in claim 1 also comprises:
One second current detection circuit is in order to detect the secondary winding electric current, to produce the secondary current detection signal; And
One second voltage comparator, in order to relatively this a secondary current detection signal and a predetermined reference voltage, with export one opening time termination signal to this on-off controller.
4. capacitor charging circuit as claimed in claim 1 also comprises:
One minimal turn-on time restriction unit prevents that this power switch from switching to off-state before the minimal turn-on time expires.
5. capacitor charging circuit as claimed in claim 4, wherein:
This minimal turn-on time restriction unit is controlled and is modulated this minimal turn-on time by this soft starting circuit, and it is increased gradually beginning the charging initial stage.
6. capacitor charging circuit as claimed in claim 1 also comprises:
One minimum limiting unit opening time prevents that this power switch from switching to on-state before expiring a minimum opening time.
7. capacitor charging circuit as claimed in claim 1 also comprises:
One maximum limiting unit turn-on time prevents that this power switch still is maintained at on-state after expiring a maximum turn-on time.
8. capacitor charging circuit, make a voltage source via this transformer capacity load that charges in order to control a transformer, wherein this voltage source is coupled in a winding of this transformer and this capacity load is coupled in the secondary winding of this transformer, and this capacitor charging circuit comprises:
One power switch is coupled in this winding, makes in the turn-on time of this power switch the circulation that allows once winding current, and stops the circulation of once winding current in the opening time of this power switch;
One on-off controller is in order to control this turn-on time and this opening time; And
One minimal turn-on time restriction unit prevents that this power switch from switching to off-state before the minimal turn-on time expires.
9. capacitor charging circuit, make a voltage source via this transformer capacity load that charges in order to control a transformer, wherein this voltage source is coupled in a winding of this transformer and this capacity load is coupled in the secondary winding of this transformer, and this capacitor charging circuit comprises:
One power switch is coupled in this winding, makes in the turn-on time of this power switch the circulation that allows once winding current, and stops the circulation of once winding current in the opening time of this power switch;
One on-off controller is in order to control this turn-on time and this opening time; And
One minimum limiting unit opening time prevents that this power switch from switching to on-state before expiring a minimum opening time.
10. capacitor charging circuit, make a voltage source via this transformer capacity load that charges in order to control a transformer, wherein this voltage source is coupled in a winding of this transformer and this capacity load is coupled in the secondary winding of this transformer, and this capacitor charging circuit comprises:
One power switch is coupled in this winding, makes in the turn-on time of this power switch the circulation that allows once winding current, and stops the circulation of once winding current in the opening time of this power switch;
One on-off controller is in order to control this turn-on time and this opening time; And
One maximum limiting unit turn-on time prevents that this power switch still is maintained at on-state after expiring a maximum turn-on time.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200420074065 CN2738454Y (en) | 2004-08-13 | 2004-08-13 | Capacity charging circuit with soft starting function |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200420074065 CN2738454Y (en) | 2004-08-13 | 2004-08-13 | Capacity charging circuit with soft starting function |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN2738454Y true CN2738454Y (en) | 2005-11-02 |
Family
ID=35348357
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 200420074065 Expired - Fee Related CN2738454Y (en) | 2004-08-13 | 2004-08-13 | Capacity charging circuit with soft starting function |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN2738454Y (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101673956B (en) * | 2008-09-12 | 2013-01-30 | 力博特公司 | UPS soft start circuit and method |
| CN115102384A (en) * | 2022-07-15 | 2022-09-23 | 深圳市单源半导体有限公司 | Soft start control circuit, control method thereof and power supply circuit |
-
2004
- 2004-08-13 CN CN 200420074065 patent/CN2738454Y/en not_active Expired - Fee Related
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101673956B (en) * | 2008-09-12 | 2013-01-30 | 力博特公司 | UPS soft start circuit and method |
| CN115102384A (en) * | 2022-07-15 | 2022-09-23 | 深圳市单源半导体有限公司 | Soft start control circuit, control method thereof and power supply circuit |
| CN115102384B (en) * | 2022-07-15 | 2023-07-18 | 深圳市单源半导体有限公司 | Soft start control circuit, control method thereof and power supply circuit |
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Address after: Postcode of Taiwan, Hsinchu: Patentee after: Global Mixed-mode Technology Inc. Address before: Postcode of Taiwan, Hsinchu: Patentee before: Yuanchuang Science and Technology Co., Ltd. |
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Owner name: ZHIXIN TECHNOLOGY CO., LTD. Free format text: FORMER NAME: YUANCHUANG TECHNOLOGY CO., LTD. |
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Granted publication date: 20051102 Termination date: 20090914 |