CN2733781Y - Interface between mainboard and decoding board of TV set - Google Patents
Interface between mainboard and decoding board of TV set Download PDFInfo
- Publication number
- CN2733781Y CN2733781Y CNU2004200973309U CN200420097330U CN2733781Y CN 2733781 Y CN2733781 Y CN 2733781Y CN U2004200973309 U CNU2004200973309 U CN U2004200973309U CN 200420097330 U CN200420097330 U CN 200420097330U CN 2733781 Y CN2733781 Y CN 2733781Y
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Abstract
The utility model relates to an interface between a mainboard and a decoding board of a TV set, belonging to the TV set technique. The interface between the mainboard and the decoding board of the TV set is connected between the mainboard and the decoding board of the TV set; further, structual sizes and the definition of a base pin of the interface between the mainboard and the decoding board are standardized. The utility model adopts two double-row sockets of 40 needle; one is used for a 9 pin TJC3 socket of a VGA signal input, and the other is used for a 10 pin TJC3 socket of an RGB signal output. The interface between the mainboard and the decoding board of the TV set sufficiently considers the condition that some video decoding chips self contain a detecting output unit of middle playing, and fractions after a pre-middle playing decoding unit are removed to a number board, which is convenient to realize modular design; the utility model can shorten development cycle of the design, simplify production technique, and reduce production cost. The utility model can be widely applied to various digital TV sets.
Description
Technical field
The utility model belongs to technical field of television sets, more particularly relates to the improvement of the interface of TV SKD and decoding deck.
Background technology
Existing television set is owing to adopt different digitization programs, and the digiboard that it is inner and the interface of mainboard generally can not generally exchange.The characteristics of digital to television technology are its motherboard circuit (mainly referring to power supply, Hang Chang, sound accompaniment, circuit such as tuning) comparative maturities, its digitizer because of update often development very fast change also very fast.Therefore cause the interface of digiboard and mainboard generally not exchange.Because the interface of each digitization program can not be general, also just be difficult to realize modularized design.Whenever new technology appearance, the developer must redesign mainboard, and construction cycle lengthening, design work amount are strengthened, and has improved design and production cost, and production technology is also more complicated.
Summary of the invention
The purpose of this utility model just is to overcome above-mentioned shortcoming and defect, and the interface of a kind of novel TV machine mainboard and decoding deck is provided.It fully takes into account and will serve the situation that video decoding chip is put the detection output unit in carrying, all moved in the digiboard put decoding unit in pre-in the former mainboard with the rear section, make can the share out the work and help one another design work of mainboard and decoding deck of designer, can on identical mainboard, cooperate simultaneously with different digiboard schemes, be convenient to realize modularized design, and then shortening is designed and developed the cycle, simplifies production technology, is reduced design and production cost.
In order to achieve the above object, the further standard of the utility model mainboard and the physical dimension of decoding deck interface and the definition of pin.This interface is connected between the mainboard and decoding deck of television set.It adopts two 40 double sockets of pin, one to be used for 9 pin TJC3 sockets of VGA signal input and one to be used for rgb signal and to output to and look the 10 pin TJC3 sockets of putting plate.
The pin of two 40 double socket XS501 of pin and XS502 is defined as follows:
XS501:1 pin-Y input, 2 pin-AGC output, 3 pin-Y/C-C input, 4 pin-GND, 5 pin-PIF input, 6 pin-GND, 7 pin-VIDEO1 input, 8 pin-PAL/NTSC SW, 9 pin-GND, 10 pin-Cr input, 11 pin-GND, 12 pin-VIDEO2 input, 13 pin-GND, 14 pin-VIDEO output, 15 pin-+5V-2,16 pin-GND, 17 pin-+8V, 18 pin-GND, 19 pin-Audio output, 20 pin-+5V, 21 pin-+12V, 22 pin-Audio output, 23 pin-GND, 24 pin-+8V, 25 pin-GND, 26 pin-+5V-2,27 pin-VIDEO output, 28 pin-GND, 29 pin-VIDEO2 input, 30 pin-GND, 31 pin-Cr input, 32 pin-GND, 33 pin-Cb input, 34 pin-GND, 35 pin-Y input, 36 pin-GND, 37 pin-Pr input, 38 pin-GND, 39 pin-Pb input, 40 pin-S SW input.
XS502:1 pin-GND, 2 pin-GND, 3 pin-GND, 4 pin-GND, 5 pin-PWM, 6 pin-GND, 7 pin-KEY2,8 pin-KEY1,9 pin-LED, 10 pin-GND, 11 pin-Remote input, 12 pin-Stand-by, 13 pin-GND, 14 pin-+5V-1,15 pin-GND, 16 pin-TEST, 17 pin-SDA2,18 pin-SCL2,19 pin-SDA1,20 pin-SCL1,21 pin-3410-RESET, 22 pin-GND, 23 pin-MUTE+5V, 24 pin-BASS+5V, 25 pin-HDTV (+B), 26 pin-GND, 27 pin-+5V-1,28 pin-CDTV (+B), 29 pin-Stand-by, 30 pin-GND, 31 pin-Vs, 32 pin-Hs, 33 pin-H-BLANK, 34 pin-EW, 35 pin-H output, 36 pin-GND, 37 pin-VD-, 38 pin-VD+, 39 pin-ABL, 40 pin-EHT.
The pin of 10 pin TJC3 sockets is defined as follows: 1 pin-GND, 2 pin-R output, 3 pin-GND, 4 pin-G output, 5 pin-GND, 6 pin-B output, 7 pin-GND, 8 pin-AKB, 9 pin-VM, 10 pin-PC.The pin of 9 pin TJC3 sockets is defined as follows: 1 pin-Vs, 2 pin-Hs, 3 pin-GND, 4 pin-R, 5 pin-GND, 6 pin-G, 7 pin-GND, 8 pin-B, 9 pin-GND.
Consider that most vision signal AD and decoding chip all have the multi-channel video handoff functionality, mainboard no longer adopts the video switch chip, each road signal directly enters digiboard, comprises that two VIDEO inputs, the input of intermediate frequency 38M signal, a YC input (multiplexing with AV1), a YCbCr import.For the demonstration of compatible high-definition format, also has one road YPbPr input.In addition, the TJC3 socket of one 9 pin is that the RGBHV that is used for the VGA signal imports.
Output mainly is to export to video amplifier circuit through the rgb signal behind decoding, the up conversion.This connects by one 10 pin TJC3 socket.Be exactly the output of row field sync signal in addition.Row adopts the output of 5V positive pulse waveform synchronously, and field synchronization adopts the sawtooth waveforms output of two-way symmetry.At the geometric distortion adjustment, stipulated the parabolic shape output interface.Simultaneously since in put detection unit and on digiboard, finish, digiboard produces one road audio frequency and outputs to mainboard.
At the preheating amplification circuit on the digiboard, 12V and 8V power supply are provided.At AD, decoding, up conversion, DA provides the 5V power supply of big electric current.Provide one road 5V power supply specially at CPU.The 5V that provides to CPU during standby still powers, and all the other are no-output then.
The peripheral chip major part of television set has all realized IIC control, thereby only needs two signals of SDA, SCL can realize control to all IIC devices on the mainboard.Because adopted the tuner of frequency tuning, IIC also can control and search platform, therefore simplified design, improved reliability.
Also stipulated the ABL control pin at row field signal, the horizontal blanking signal feedback is used for the capable field synchronization feedback that OSD shows.Stipulated that simultaneously CPU output foot control PAL and TSC-system formula diverter switch, quiet, supper bass switch, power supply indicator, two AD pin receive the button input, an input pin receives controls such as remote control input.
In order to solve interference problem, all there is a ground corresponding to all signaling interfaces on interface, the shielding when being used to connect up.
This interface has been done comprehensive definition again on circuit and structure, be convenient to realize modularized design in the exploitation of new architecture, has shortened construction cycle and risk, has simplified production technology, has reduced production cost.It can be widely used in the various digital televisions.
Description of drawings
Fig. 1 is a structural representation of the present utility model.
Fig. 2 is the pin definitions table of the double socket XS501 of 40 pins.
Fig. 3 is the pin definitions table of the double socket XS502 of 40 pins.
Embodiment
Embodiment 1.The interface of a kind of TV SKD and decoding deck.It is connected between the mainboard and decoding deck of television set, adopts two 40 double socket XS501 of pin and XS502,9 pin TJC3 sockets and 10 pin TJC3 sockets that are used for rgb signal output that are used for the input of VGA signal.Visible Fig. 1 of structural representation of two 40 double socket XS501 of pin and XS502, the visible Fig. 2 of its pin definitions and Fig. 3.
The pin of 10 pin TJC3 sockets is defined as: 1 pin-GND, 2 pin-R output, 3 pin-GND, 4 pin-G output, 5 pin-GND, 6 pin-B output, 7 pin-GND, 8 pin-AKB, 9 pin-VM, 10 pin-PC.The pin of 9 pin TJC3 sockets is defined as: 1 pin-Vs, 2 pin-Hs, 3 pin-GND, 4 pin-R, 5 pin-GND, 6 pin-G, 7 pin-GND, 8 pin-B, 9 pin-GND.
Claims (3)
1. the interface of TV SKD and decoding deck, it is connected between the mainboard and decoding deck of television set, it is characterized in that two 40 double sockets of pin of its employing, 9 pin TJC3 sockets and 10 pin TJC3 sockets that are used for rgb signal output that are used for the input of VGA signal.
2. according to the interface of described TV SKD of claim 1 and decoding deck, it is characterized in that the pin of double socket XS501 of said two 40 pins and XS502 is defined as follows:
XS501:1 pin-Y input, 2 pin-AGC output, 3 pin-Y/C-C input, 4 pin-GND, 5 pin-PIF input, 6 pin-GND, 7 pin-VIDEO1 input, 8 pin-PAL/NTSC SW, 9 pin-GND, 10 pin-Cr input, 11 pin-GND, 12 pin-VIDEO2 input, 13 pin-GND, 14 pin-VIDEO output, 15 pin-+5V-2,16 pin-GND, 17 pin-+8V, 18 pin-GND, 19 pin-Audio output, 20 pin-+5V, 21 pin-+12V, 22 pin-Audio output, 23 pin-GND, 24 pin-+8V, 25 pin-GND, 26 pin-+5V-2,27 pin-VIDEO output, 28 pin-GND, 29 pin-VIDEO2 input, 30 pin-GND, 31 pin-Cr input, 32 pin-GND, 33 pin-Cb input, 34 pin-GND, 35 pin-Y input, 36 pin-GND, 37 pin-Pr input, 38 pin-GND, 39 pin-Pb input, 40 pin-S SW input.
XS502:1 pin-GND, 2 pin-GND, 3 pin-GND, 4 pin-GND, 5 pin-PWM, 6 pin-GND, 7 pin-KEY2,8 pin-KEY1,9 pin-LED, 10 pin-GND, 11 pin-Remote input, 12 pin-Stand-by, 13 pin-GND, 14 pin-+5V-1,15 pin-GND, 16 pin-TEST, 17 pin-SDA2,18 pin-SCL2,19 pin-SDA1,20 pin-SCL1,21 pin-3410-RESET, 22 pin-GND, 23 pin-MUTE+5V, 24 pin-BASS+5V, 25 pin-HDTV (+B), 26 pin-GND, 27 pin-+5V-1,28 pin-CDTV (+B), 29 pin-Stand-by, 30 pin-GND, 31 pin-Vs, 32 pin-Hs, 33 pin-H-BLANK, 34 pin-EW, 35 pin-H output, 36 pin-GND, 37 pin-VD-, 38 pin-VD+, 39 pin-ABL, 40 pin-EHT.
3. according to the interface of described TV SKD of claim 2 and decoding deck, it is characterized in that the pin of said 10 pin TJC3 sockets is defined as follows: 1 pin-GND, 2 pin-R output, 3 pin-GND, 4 pin-G output, 5 pin-GND, 6 pin-B output, 7 pin-GND, 8 pin-AKB, 9 pin-VM, 10 pin-PC; The pin of 9 pin TJC3 sockets is defined as follows: 1 pin-Vs, 2 pin-Hs, 3 pin-GND, 4 pin-R, 5 pin-GND, 6 pin-G, 7 pin-GND, 8 pin-B, 9 pin-GND.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNU2004200973309U CN2733781Y (en) | 2004-10-25 | 2004-10-25 | Interface between mainboard and decoding board of TV set |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNU2004200973309U CN2733781Y (en) | 2004-10-25 | 2004-10-25 | Interface between mainboard and decoding board of TV set |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN2733781Y true CN2733781Y (en) | 2005-10-12 |
Family
ID=35069617
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNU2004200973309U Expired - Fee Related CN2733781Y (en) | 2004-10-25 | 2004-10-25 | Interface between mainboard and decoding board of TV set |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN2733781Y (en) |
-
2004
- 2004-10-25 CN CNU2004200973309U patent/CN2733781Y/en not_active Expired - Fee Related
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| C19 | Lapse of patent right due to non-payment of the annual fee | ||
| CF01 | Termination of patent right due to non-payment of annual fee |