CN2731717Y - CMOS assembly - Google Patents
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- CN2731717Y CN2731717Y CN 200420007675 CN200420007675U CN2731717Y CN 2731717 Y CN2731717 Y CN 2731717Y CN 200420007675 CN200420007675 CN 200420007675 CN 200420007675 U CN200420007675 U CN 200420007675U CN 2731717 Y CN2731717 Y CN 2731717Y
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Abstract
The utility model provides a Complementary Metal Oxide Semiconductor (CMOS) assembly. The structure of the utility model is that: a gate electrode is provided on the base; a source electrode and a draw electrode are provide in the base of the bilateral of the gate electrode; the stress leno breaker is in adjustment allocation on the both sides of the gate electrode, and part of the stress leno breaker extends to the surface of the base; the stressed layer is provided on the gate electrode, the stressed leno breaker and the source electrode and draw electrode, and is contacted with the stressed leno breaker. Thus, the stress of the channel region of the base of the bottom of the gate electrode is raised.
Description
Technical field
The utility model relates to a kind of cmos component, particularly a kind of structure of utilizing local mechanical Stress Control (local mechanical-stress control is called for short LMC) to increase the usefulness of cmos component.
Background technology
In present semiconductor subassembly, be to use silicon integral body (Si bulk) as substrate, and reach the purpose of high speed operation and low power consumption by dwindling size of components.Yet size of components dwindles near the limit of physics and the limit of cost at present.Therefore, other is different from the technology of the method for minification to need development, reaches the purpose of high speed operation and low power consumption.
Therefore, the someone proposes to utilize at transistorized channel region the mode of Stress Control, overcomes the limit of assembly downsizing.The method is to change the silicon crystal lattice spacing by applied stress, increases the mobility in electronics and electric hole.
Common method places Si-Ge layer (being in tensile stress) to go up the channel layer of the silicon layer (tensile-strained Si layer) of tensile stress as nmos pass transistor for using, and the germanium-silicon layer (compressive-strained Si-Ge layer) (being in compression stress) of use compressive tension is as the transistorized channel layer of PMOS.By the Si-Ge layer of silicon layer that uses tensile stress and compressive tension channel layer, can increase the mobility in surface electronic and electric hole, and reach the purpose of high speed operation and low-yield consume simultaneously as MOS transistor.
Yet, there are some problems in this technology, when the Si-Ge layer (p channel layer) of Si layer (n channel layer) that forms tensile stress simultaneously and compressive tension during as the channel layer of CMOS, it is very complicated that processing procedure can become, and to want selectivity to form NMOS channel layer and PMOS channel layer be suitable difficulty.And, when forming the Si-Ge layer by high-temperature heat treatment, the separation (segregation) of difference row (dislocation) or generation Ge can take place, and make the characteristic degradation of gate breakdown voltage.
In addition, have research and utilization to produce stress as the silicon nitride layer that contact hole etching stops layer recently, influence the transistor electric current of tending to act, this technology is called the local mechanical Stress Control.By the compression stress that increase adds, can improve the transistorized mobility of PMOS; By the compression stress that minimizing adds, can improve the mobility of nmos pass transistor.
Though the above-mentioned method of utilizing silicon nitride layer generation stress to improve performance of transistors uses the method for Si-Ge resilient coating simple, its effect that can improve is limited.
Summary of the invention
In view of this, the purpose of this utility model provides a kind of cmos component structure, utilizes the technology of local mechanical Stress Control, further improves transistorized usefulness.
According to a kind of cmos component that the purpose of this utility model provided, its structure comprises to be located at gate electrode in the substrate, source/drain is located in the gate electrode substrate on two sides, with stress buffer lining compliance be disposed at the gate electrode both sides and part extends to substrate surface, and stressor layers is located on gate electrode, stress buffer lining and the source/drain, and contact with the stress buffer lining, use the stress that improves the channel region in the gate electrode below substrate.
Specifically, cmos component provided by the utility model, its structure comprises:
One substrate;
One gate electrode is located in this substrate;
One source pole/drain is located in this substrate of these gate electrode both sides;
One stress buffer lining is configured in to compliance these gate electrode both sides and part extends to this substrate surface; And
One stressor layers is located on this gate electrode, this stress buffer lining and this source/drain, and contacts with this stress buffer lining, uses the stress that improves the channel region in this gate electrode this substrate of below.
Wherein, the thickness of described stress buffer lining is preferably less than 500 dusts.The material of this stress buffer lining is a silica.And the material of this stressor layers is the laminated of silicon nitride, silicon oxynitride or silicon nitride and silicon oxynitride.
Wherein, if above-mentioned stressor layers tool tensile stress, being covered in the gate electrode of stressor layers below and the transistor of source/drain formation is PMOS transistor and nmos pass transistor.If above-mentioned stressor layers tool compression stress, being covered in the gate electrode of stressor layers below and the transistor of source/drain formation is the PMOS transistor.
In addition, more can comprise a metal silicide layer in the cmos component of the present utility model, be arranged between this stressor layers and this source/drain, and between this stressor layers and this gate electrode.
Simultaneously, the utility model also provides another kind of cmos component, its structure comprises to be located at gate electrode in the substrate that is provided with at least one barrier assembly, comprise one first stressor layers in this shallow trench barrier assembly, be located at source/drain in the gate electrode substrate on two sides and contact above-mentioned barrier assembly, with stress buffer lining compliance be disposed at the gate electrode both sides and part extends to substrate surface, and second stressor layers is located at gate electrode, on stress buffer lining and the source/drain, and contact with the stress buffer lining, by above-mentioned first stressor layers and second stressor layers to improve the stress of the channel region in the gate electrode below substrate.
Specifically, another kind of cmos component provided by the utility model, its structure comprises:
One substrate is provided with at least one barrier assembly, and comprises one first stressor layers in this barrier assembly;
One gate electrode is located in this substrate;
One source pole/drain is located in this substrates of this gate electrode both sides and contacts described barrier assembly;
One stress buffer lining is configured in to compliance these gate electrode both sides and part extends to this substrate surface; And
One second stressor layers is located on this gate electrode, this stress buffer lining and this source/drain, and contacts with this stress buffer lining, by second stressor layers and first stressor layers to improve the stress of the channel region in this gate electrode this substrate of below.
The thickness of wherein said stress buffer lining is preferably less than 500 dusts.And the material of this stress buffer lining is preferably silica.The material of this first stressor layers can be the laminated of silicon nitride, silicon oxynitride or silicon nitride and silicon oxynitride, and the material of this second stressor layers can be the laminated of silicon nitride, silicon oxynitride or silicon nitride and silicon oxynitride.When the laminated of described silicon nitride and silicon oxynitride is a tension stress layer, preferably this laminated upper strata has higher tensile stress than its lower floor.This lower floor's material be Silicon-rich silicon nitride (silicon-rich nitride) or silicon oxynitride wherein for example, and the silicon nitride that this upper strata material is silicon nitride or rich nitrogen (nitrogen-rich nitride).
Wherein, if when the above-mentioned second stressor layers tool tensile stress and the first stressor layers tool tensile stress, being covered in the gate electrode of second stressor layers below and transistor that source/drain constitutes is PMOS transistor and nmos pass transistor.If when compression of the above-mentioned second stressor layers tool compression stress and the first stressor layers tool or tensile stress, being covered in the gate electrode of second stressor layers below and transistor that source/drain constitutes is the PMOS transistor.
In addition, cmos component of the present utility model more can comprise a metal silicide layer, is arranged between this second stressor layers and this source/drain, and between this second stressor layers and this gate electrode, provides this PMOS transistor one compression stress.
Utilize the structure of cmos component provided by the utility model, can use the transistor that forms characteristic with mechanical stress concentration at channel region with high speed operation and low-yield consume.
For above-mentioned purpose of the present utility model, feature and advantage can be become apparent, a preferred embodiment cited below particularly, and cooperate appended graphicly, be described in detail below:
Description of drawings
Figure 1A to Fig. 1 E is the schematic diagram that illustrates the structure and the manufacture process of a kind of cmos component of the utility model.
Fig. 2 A to Fig. 2 G illustrates the structure of the another kind of cmos component of the utility model and the schematic diagram of manufacture process.
Embodiment
Show according to result of study,, when compression stress that increases channel region or tensile stress, can lead to the mobility that powers up the hole carrier P channel-style transistor.For N channel-style transistor, when reducing the compression stress of channel region, when also promptly increasing the tensile stress of channel region, can lead to the mobility that adds the electronics carrier.In order to increase the mobility of carrier at channel region, so the utility model provides a kind of structure of cmos component of the stress that can effectively increase channel region.
Structure:
The utility model provides a kind of structure of cmos component, shown in Fig. 1 D.In this structure, gate electrode 104 is to be located in the substrate 100, and source/drain S/D is located in gate electrode 104 substrate on two sides 100.Wherein, the material of gate electrode 104 can be polysilicon, metal, SiGe or germanic polysilicon.
In addition, at gate electrode 104 and substrate 100 brake-pole dielectric layer 102 is set, its material can be silica.
Then, stressor layers 118 is located on gate electrode 104, stress buffer lining 110 and the source/drain S/D, and contacts with stress buffer lining 110, use the stress that improves the channel region 114 in the gate electrode 104 below substrates 100 with gate electrode 104.Wherein, the material of stressor layers 118 is the laminated of silicon nitride (SiN), silicon oxynitride (SiON) or silicon nitride (SiN) and silicon oxynitride (SiON).
If these stressor layers 118 tool tensile stresses cover the gate electrode 104 of stressor layers 118 belows and the transistor of source/drain S/D formation and then are PMOS transistor and nmos pass transistor.
If these stressor layers 118 tool compression stresses cover the gate electrode 104 of stressor layers 118 belows and the transistor of source/drain S/D formation and then are the PMOS transistor.
In addition, between stressor layers 118 and source/drain S/D, a metal silicide layer 116 is set, uses the sheet resistor that reduces source/drain S/D, it also shows suitable compression stress, can promote the PMOS performance of transistors.Usually, between stressor layers 118 and gate electrode 104, the metal silicide layer 116 of identical material can be set also.
In addition, also can adopt implanting ions program (not illustrating) to implant as argon (Ar) ion or oxygen (O) ion in stressor layers 118, its operation opportunity is after stressor layers 118 forms, and after finishing implanting ions, then implement one between 350 ℃～700 ℃ tempering program, to increase the compression stress of stressor layers 118, by this and appropriateness is adjusted the integrated stress in the channel region 114.
Moreover the utility model also provides the structure of another kind of cmos component, shown in Fig. 2 F.In this structure, gate electrode 210 is arranged in the active region AA that defined by two shallow trench barrier assembly STI ' in the substrate 200, and source/drain S/D is located in gate electrode 210 substrate on two sides 200 and is attached at contiguous shallow trench barrier assembly STI '.Wherein, in shallow trench barrier assembly STI ', be provided with first stressor layers 205 of compliance.
In addition, the material of gate electrode 210 can be polysilicon, metal, SiGe or germanic polysilicon, and at gate electrode 210 and substrate 200 brake-pole dielectric layer 208 is set, and its material can be silica.
Be disposed to stress buffer lining 214 compliances gate electrode 210 both sides and partly extend to substrate 200 surfaces.The THICKNESS CONTROL of stress buffer lining 214 is below 500 dusts, and its material can be silica.
Then, second stressor layers 224 is located on gate electrode 210, stress buffer lining 214 and the source/drain S/D, and contact with stress buffer lining 214 with gate electrode 210, by the influence of second stressor layers 224 that is arranged at first stressor layers 205 in the shallow trench barrier assembly STI ' and is arranged at the gate electrode surface to improve channel region 220 stress in the gate electrode 210 below substrates 200.Wherein, the material of first stressor layers 205 and second stressor layers 224 can be the laminated of silicon nitride (SiN), silicon oxynitride (SiON) or silicon nitride (SiN) and silicon oxynitride (SiON).
If when these second stressor layers, 224 tool tensile stresses and first stressor layers, 205 tool tensile stresses, be covered in the gate electrode 210 of second stressor layers, 224 belows and transistor that source/drain S/D constitutes and then be PMOS transistor or nmos pass transistor.
If these second stressor layers, 224 tool compression stresses and first stressor layers, 205 tools stretch or during compression stress, be covered in the gate electrode 210 of second stressor layers, 224 belows and transistor that source/drain S/D constitutes and then be the PMOS transistor.
In addition, between second stressor layers 224 and source/drain S/D, a metal silicide layer 222 can be set, use the sheet resistor that reduces source/drain S/D, it also can show suitable compression stress and promote the transistorized usefulness of PMOS.Usually, between second stressor layers 224 and gate electrode 210, the metal silicide layer 222 of identical material can be set also.
In addition, also can adopt implanting ions program (not illustrating) to implant as argon (Ar) ion or oxygen (O) ion in first stressor layers 205 and second stressor layers 224, its operation opportunity is after described stressor layers forms, and after finishing implanting ions, then implement one between 350 ℃～700 ℃ tempering program, to increase the compression stress of these a little stressor layers, by this and appropriateness is adjusted the integrated stress in the channel region 220.
Manufacture method:
First embodiment:
Figure 1A to Fig. 1 E is the schematic diagram that illustrates the manufacture method of a kind of cmos component of the utility model.
At first please refer to Figure 1A, a substrate 100 is provided, substrate 100 has active region AA.Wherein this active region AA is by forming the barrier assembly structure in substrate 100, shallow trench barrier assembly STI for example, and define.
Then, form transistor for active region, this transistor can be PMOS transistor and nmos pass transistor.As shown in the figure, form a brake-pole dielectric layer 102 and gate electrode 104 in substrate 100, wherein the material of brake-pole dielectric layer 102 can be silica, and the material of gate electrode 104 can be polysilicon, metal, SiGe or germanic polysilicon.The formation method of brake-pole dielectric layer 102 and gate electrode 104 wherein, for example be in substrate 100, to deposit one dielectric layer and conductive layer in regular turn, and on conductive layer, form a patterning cover curtain layer (not illustrating), afterwards, with the patterning cover curtain layer is the cover curtain, in regular turn conductive layer and dielectric layer are carried out anisotropic etching,, again the patterning cover curtain layer is removed to form brake-pole dielectric layer 102 and gate electrode 104 as shown in the figure.
Afterwards, the active region AA in gate electrode 104 substrate on two sides 100 forms light doped region 106, and its formation method is with ionic-implantation admixture to be implanted not by in the substrate 100 of gate electrode 104 and shallow trench barrier assembly STI covering.
Then please refer to Figure 1B, compliance ground form a stress buffer lining 108 in gate electrode 104 both sides and part extend to substrate 100 surfaces.The thickness of above-mentioned stress buffer lining 108 is less than 500 dusts, and its material can be silica.Stress buffer lining 108 is except in order to the effect as stress buffer, also can be in order to the sidewall of protection gate electrode 104 and near the zone of channel region 114.Afterwards, on gate electrode 104 both sides stress-buffer layers 108, form a clearance wall 110.The material of above-mentioned clearance wall 110 can be the laminated of silicon nitride or silica/silicon nitride.Wherein, the formation method of stress buffer lining 108 and clearance wall 110, for example be in regular turn on the surface that substrate 100, gate electrode 104 and gate dielectric 102 are exposed compliance form skim insulating barrier and another thicker insulating barrier; Then, utilize anisotropic etching, to form a clearance wall 110 and stress buffer lining 108.
Then, do not formed dense doped region 112 by the active region AA in the substrate 100 of gate electrode 104 and clearance wall 110 coverings in gate electrode 104 both sides, its formation method is with ionic-implantation admixture to be implanted not by in the substrate 100 of gate electrode 104, clearance wall 110 and shallow trench barrier assembly STI covering.Wherein light doped region 106 and dense doped region 112 are source/drain S/D of transistor formed.
Then please refer to Fig. 1 C, utilize wet etching or dry ecthing to remove clearance wall 110, to expose stress buffer lining 108.
Wherein before removing clearance wall 110, comprise that more carrying out one aims at the silicide processing procedure automatically, forms a metal silicide layer 116 with the surface at source/drain S/D; Or after removing clearance wall 110, carry out one and aim at the silicide processing procedure automatically, form a metal silicide layer 116 with surface, shown in Fig. 1 C at source/drain S/D.In above-mentioned automatic aligning silicide processing procedure, if the material of gate electrode 104 is polysilicon, SiGe or germanic polysilicon, then its surface also can form metal silicide layer 116, as shown in the figure.
Then please refer to Fig. 1 D, after removing clearance wall 110 and finishing automatic aligning silicide processing procedure, on gate electrode 104, stress buffer lining 108 and source/drain S/D, cover a stressor layers 118, and contact with stress buffer lining 108 with gate electrode 104, use the stress that improves in the gate electrode 104 below substrates 100 channel region 114.
Above-mentioned stressor layers 118 can be compressive stress layers or tension stress layer, its material can be the laminated of silicon nitride (SiN), silicon oxynitride (SiON) or silicon nitride (SiN) and silicon oxynitride (SiON), its thickness is about between 300～700 dusts (), and its formation method can be electricity slurry enhanced chemical vapor deposition method (PECVD), Rapid Thermal process chemistry vapour deposition process (RTCVD), atomic level chemical vapour deposition technique (ALCVD), Low Pressure Chemical Vapor Deposition (LPCVD).
When stressor layers 118 when using the laminated tension stress layer of silicon nitride (SiN)/silicon oxynitride (SiON), the tensile stress that is positioned at the upper strata preferably is greater than lower floor.At this moment, the material that is positioned at laminated upper strata is preferably silicon oxynitride or the higher silicon nitride layer (silicon-rich nitride) of a silicon content, and the material that is positioned at laminated lower floor then is preferably silicon nitride or the higher silicon nitride layer (nitrogen-rich nitride) of nitrogen content.
Condition by control formation, can adjust the stress intensity of formed rete, according to research, the factor of may command stress has temperature, pressure or process gas ratio, if electricity slurry sedimentation, then the factor of may command stress also comprises electricity slurry electric power (plasma power).
To form material be silicon nitride and be that the stressor layers 118 of compression stress is an example with electricity slurry enhanced chemical vapor deposition method, required temperature is roughly between 300 ℃ and 500 ℃, required pressure is roughly between 1.0 Bristols (torr) and 1.5 Bristols, roughly between between 1000 watts (W) and 2000 watts, its process gas can be NH to required electricity slurry electric power
3: SiH
4, ratio is roughly 4～10.
To form material be silicon nitride and be that the stressor layers 118 of tensile stress is an example with Rapid Thermal process chemistry vapour deposition process, required temperature is roughly between 300 ℃ and 800 ℃, roughly between 150 Bristols and 300 Bristols, its process gas can be NH to required pressure
3: SiH
4, ratio is roughly 50～400; Perhaps its process gas can be dichlorosilane (dichlorosilane, SiH
2Cl
2, be called for short DCS): NH
3, ratio is roughly 0.1～1.
To form material be silicon nitride and be that the stressor layers 118 of compression stress is an example with Low Pressure Chemical Vapor Deposition, required temperature is roughly between 400 ℃ and 750 ℃, required pressure is roughly between 0.1 Bristol (torr) and 50 Bristols, its process gas can be dichlorosilane and NH3, and ratio is roughly 1～300.
If stressor layers 118 tool tensile stresses cover the gate electrode 104 of stressor layers 118 belows and the transistor of source/drain S/D formation and can be PMOS transistor and nmos pass transistor.In the case, the structure that does not remove clearance wall with tradition is compared, and the compression stress of the channel region 114 of cmos component of the present utility model can reduce about 93～128MPa, improves electronics and the electric hole carrier mobility at channel region by this.
If stressor layers 118 tool compression stresses, covering the gate electrode 104 of stressor layers 118 belows and the transistor of source/drain S/D formation is the PMOS transistor.In the case, the structure that does not remove clearance wall with tradition is compared, and the compression stress of the channel region 114 of cmos component of the present utility model can increase about 93～128MPa, improves the mobility of electric hole carrier at channel region by this.
In addition, also can adopt implanting ions program (not illustrating) to implant as argon (Ar) ion or oxygen (O) ion in stressor layers 118, its operation opportunity is after stressor layers 118 forms, and after finishing implanting ions, then implement one between 350 ℃～700 ℃ tempering program, to increase the compression stress of stressor layers 118, by this and appropriateness is adjusted the integrated stress in the channel region 114.
In addition, above-mentioned stressor layers 118 also can be as the etching stopping layer of follow-up contact hole processing procedure.
Then carrying out follow-up processing procedure, for example is the interconnect processing procedure.Shown in Fig. 1 E, on stressor layers 118, form inner layer dielectric layer 120, its material for example is silica, boron-phosphorosilicate glass (BPSG) or other similar this character, and at this inner layer dielectric layer 120 after planarization, by micro image etching procedure, in inner layer dielectric layer 120 and stressor layers 118, form contact window 122.In the etching step of contact hole, above-mentioned stressor layers 118 is as etching stopping layer, wait to be etched to the stressor layers of exposing in the contact window 122 118 after, change etching condition again, remove the stressor layers 118 in the contact window 122, treat online assembly district until exposing.
Second embodiment:
Fig. 2 A to Fig. 2 G has illustrated the schematic diagram of manufacture method of the cmos component of another embodiment of the utility model.
At first please refer to Fig. 2 A, a substrate 200 is provided, this substrate 200 has active region AA, and this active region AA defines by form two grooves 202 in substrate 200.Then in groove 202, form the surface of a lining 204 respectively with smoothing groove 202.Lining 204 for example is by the formed silicon oxide layer of thermal oxidation method.Then groove 202 in, reach and conformably form first stressor layers 205 in the substrate 200 and be covered on the lining 204 in the groove 202.At this, first stressor layers 205 can be with reference to the manufacture method of the stressor layers 118 among aforementioned first embodiment and is formed.Deposit an insulating material 206 in substrate 200 and insert in the groove 202 then comprehensively.
Then please refer to Fig. 2 B, the insulating material 206 that will be higher than substrate 200 surfaces by the execution as the planarisation step (not shown) of cmp program removes, and then stays an insulating barrier 206a in groove 202.Then by part first stressor layers of execution to remove substrate surface in the active region AA of an etching step (not shown), at last in groove, stay one first stressor layers 205 that conforms to flute surfaces, and in groove 202, then formed the shallow trench barrier assembly STI ' that the definition different active is used.
Please refer to Fig. 2 C, then form transistor in active region AA, this transistor can be PMOS transistor or nmos pass transistor.As shown in the figure, form a brake-pole dielectric layer 208 and gate electrode 210 in substrate 200, wherein the material of brake-pole dielectric layer 208 can be silica, and the material of gate electrode 210 can be polysilicon, metal, SiGe or germanic polysilicon.The formation method of brake-pole dielectric layer 208 and gate electrode 210 wherein, for example can be in substrate 200, to deposit one dielectric layer and conductive layer in regular turn, and on conductive layer, form a patterning cover curtain layer (not illustrating), afterwards, with the patterning cover curtain layer is the cover curtain, in regular turn conductive layer and dielectric layer are carried out anisotropic etching,, again the patterning cover curtain layer is removed to form brake-pole dielectric layer 208 and gate electrode 210 as shown in the figure.
Afterwards, the active region AA in gate electrode 210 substrate on two sides 200 forms light doped region 212, and its formation method is with ionic-implantation admixture to be implanted not by in the substrate 200 of gate electrode 210 and shallow trench barrier assembly STI ' covering.
Then please refer to Fig. 2 D, compliance ground form a stress buffer lining 214 in gate electrode 210 both sides and part extend to substrate 200 surfaces.The thickness of above-mentioned stress buffer lining 214 is less than 500 dusts, and its material can be silica.Stress buffer lining 214 is except in order to the effect as stress buffer, also can be in order to the sidewall of protection gate electrode 210 and near the zone of channel region 220.Afterwards, on gate electrode 210 both sides stress-buffer layers 214, form a clearance wall 216.The material of above-mentioned clearance wall 216 can be the laminated of silicon nitride or silica/silicon nitride.Wherein, the formation method of stress buffer lining 214 and clearance wall 216, for example can be in regular turn on the surface that substrate 200, gate electrode 210 and brake-pole dielectric layer 208 expose compliance form skim insulating barrier and another thicker insulating barrier; Then, utilize anisotropic etching, to form a clearance wall 216 and stress buffer lining 214.
Then, do not formed dense doped region 218 by the active region AA in the substrate 200 of gate electrode 210 and clearance wall 216 coverings in gate electrode 210 both sides, its formation method is with ionic-implantation admixture to be implanted not by in the substrate 200 of gate electrode 210, clearance wall 216 and shallow trench barrier assembly STI ' covering.The source/drain S/D of wherein light doped region 212 and dense doped region 218 transistor formeds.
Then please refer to Fig. 2 E, utilize wet etching or dry ecthing to remove clearance wall 216, to expose stress buffer lining 214.
Wherein before removing clearance wall 216, can comprise that more carrying out one aims at the silicide processing procedure automatically, forms a metal silicide layer 222 with the surface in source/drain S/D; Or after removing clearance wall 216, carry out one and aim at the silicide processing procedure automatically, form a metal silicide layer 222 with surface, shown in Fig. 2 E in source/drain S/D.In above-mentioned automatic aligning silicide processing procedure, if the material of gate electrode 210 is polysilicon, SiGe or germanic polysilicon, then its surface also can form metal silicide layer 222, as shown in the figure.At this, the metal silicide layer 222 that is formed at the surface of source/drain S/D also can show a compression stress for channel region 220.
Then please refer to Fig. 2 F, after removing clearance wall 216 and finishing automatic aligning silicide processing procedure, on gate electrode 210, stress buffer lining 214 and source/drain S/D, cover one second stressor layers 224, and contact with stress buffer lining 214 with gate electrode 210, use the stress that improves in the gate electrode 210 below substrates 200 channel region 220.
In addition, also can adopt implanting ions program (not illustrating) to implant as argon (Ar) ion or oxygen (O) ion in first stressor layers 205 and second stressor layers 224, its operation opportunity is after described stressor layers forms, and after finishing implanting ions, then implement one between 350 ℃～700 ℃ tempering program, to increase the compression stress of first and second stressor layers, by this and appropriateness is adjusted the integrated stress in the channel region 220.
In addition, the second above-mentioned stressor layers 224 also can be as the etching stopping layer of follow-up contact hole processing procedure.
Then carrying out follow-up processing procedure, for example is the interconnect processing procedure.Shown in Fig. 2 G, on second stressor layers 224, form inner layer dielectric layer 226, its material for example is the material of silica, boron-phosphorosilicate glass (BPSG) or other similar this character, and in this inner layer dielectric layer 226 after planarization, by micro image etching procedure, in the inner layer dielectric layer 226 and second stressor layers 224, form contact window 228.In the etching step of contact hole, the second above-mentioned stressor layers 224 is as etching stopping layer, wait to be etched to second stressor layers of exposing in the contact window 228 224 after, change etching condition again, remove second stressor layers 224 in the contact window 228, treat online assembly district until exposing.
Above-mentioned first stressor layers 205 and second stressor layers 224 can be compressive stress layers or tension stress layer, its material can be silicon nitride (SiN), silicon oxynitride (SiON), or silicon nitride (SiN) and silicon oxynitride (SiON) is laminated, its thickness is about respectively between 20～300 dusts () and 300～700 dusts (), and its formation method can be electricity slurry enhanced chemical vapor deposition method (PECVD), Rapid Thermal process chemistry vapour deposition process (RTCVD), Rapid Thermal process chemistry vapour deposition process (RTCVD), atomic level chemical vapour deposition technique (ALCVD), Low Pressure Chemical Vapor Deposition (LPCVD).When stressor layers (first stressor layers 205 or second stressor layers 224) when using the laminated tension stress layer of silicon nitride (SiN)/silicon oxynitride (SiON), the tensile stress that is positioned at the upper strata preferably is greater than lower floor.At this moment, the material that is positioned at laminated lower floor is preferably silicon oxynitride or the higher silicon nitride layer (silicon-rich nitride) of silicon content, and the material that is positioned at laminated upper strata then is preferably silicon nitride or the higher silicon nitride layer (nitrogen-rich nitride) of nitrogen content.
Condition by control formation, can adjust the stress intensity of formed rete, according to research, the factor of may command stress has temperature, pressure or process gas ratio, if electricity slurry sedimentation, then the factor of may command stress also comprises electricity slurry electric power (plasma power).
To form material be silicon nitride and be that second stressor layers 224 of compression stress is an example with electricity slurry enhanced chemical vapor deposition method, required temperature is roughly between 300 ℃ and 500 ℃, required pressure is roughly between 1.0 Bristols (torr) and 1.5 Bristols, required electricity slurry electric power is roughly between between 1000 watts (W) and 2000 watts, its process gas can be NH3: SiH4, ratio is roughly 4～10.
To form material be silicon nitride and be that second stressor layers 224 of tensile stress is an example with Rapid Thermal process chemistry vapour deposition process, required temperature is roughly between 300 ℃ and 800 ℃, required pressure is roughly between 150 Bristols and 300 Bristols, its process gas can be NH3: SiH4, and ratio is roughly 50～400; Perhaps its process gas can be dichlorosilane (dichlorosilane, SiH2Cl2 are called for short DCS): NH3, ratio is roughly 0.1～1.
To form material be silicon nitride and be that second stressor layers 224 of compression stress is an example with Low Pressure Chemical Vapor Deposition, required temperature is roughly between 400 ℃ and 750 ℃, required pressure is roughly between 0.1 Bristol (torr) and 50 Bristols, its process gas can be DCS: NH3, ratio is roughly 1～300.
If when second stressor layers, 224 tool tensile stresses and first stressor layers, 205 tool tensile stresses, be covered in the gate electrode 210 of second stressor layers, 224 belows and transistor that source/drain S/D constitutes and can be PMOS transistor and nmos pass transistor.In the case, the structure that does not remove clearance wall with tradition is compared, and the compression stress of the channel region 220 of cmos component of the present utility model can reduce about 100～900MPa, improves electronics and electric hole carrier by this in the mobility of channel region.
If second stressor layers, 224 tool compression stresses and the first stressor layers 206a tool stretch or during compression stress, being covered in the gate electrode 210 of second stressor layers, 224 belows and transistor that source/drain S/D constitutes is the PMOS transistor.In the case, the structure that does not remove clearance wall with tradition is compared, and the compression stress of the channel region 220 of cmos component of the present utility model can increase about 100～900MPa, improves electric hole carrier by this in the mobility of channel region.
In sum, utilize structure provided by the utility model, can use the transistor that forms characteristic with mechanical stress concentration at channel region with high speed operation and low-yield consume.
In making transistorized process, before the deposition stressor layers,, can make the stress of the stressor layers of deposition concentrate on transistorized channel region effectively by increasing the process that removes clearance wall together.Therefore, this method is applicable to any processing procedure that improves transistorized usefulness by the local mechanical Stress Control.In addition, with regard to the manufacturing of above-mentioned stressor layers, can make the stressor layers that meets its demand respectively according to the different demand of P channel and N channel with compression stress and tensile stress.
Therefore, the formation method of stressor layers is not limited to above-mentioned method, and other can improve the processing procedure of transistorized usefulness all applicable to the utility model by the local mechanical Stress Control.
Though the utility model discloses as above with preferred embodiment; right its is not in order to restriction the utility model; any people who has the knack of this skill; in not breaking away from spirit and scope of the present utility model; change and retouching when doing, therefore protection range of the present utility model is when being as the criterion with the scope that claim was defined.
Claims (18)
1, a kind of cmos component is characterized in that comprising:
One substrate;
One gate electrode is located in this substrate;
One source pole/drain is located in this substrate of these gate electrode both sides;
One stress buffer lining is configured in to compliance these gate electrode both sides and part extends to this substrate surface; And
One stressor layers is located on this gate electrode, this stress buffer lining and this source/drain, and contacts with this stress buffer lining.
2, cmos component as claimed in claim 1, the thickness that it is characterized in that this stress buffer lining wherein is less than 500 dusts.
3, cmos component as claimed in claim 1 is characterized in that wherein the material of this stress buffer lining is a silica.
4, cmos component as claimed in claim 1 is characterized in that wherein the material of this stressor layers is the laminated of silicon nitride, silicon oxynitride or silicon nitride and silicon oxynitride.
5, cmos component as claimed in claim 1 is characterized in that wherein this stressor layers tool tensile stress, and being covered in this gate electrode of this stressor layers below and the transistor of this source/drain formation is PMOS transistor and nmos pass transistor.
6, cmos component as claimed in claim 1 is characterized in that wherein this stressor layers tool compression stress, and being covered in this gate electrode of this stressor layers below and the transistor of this source/drain formation is the PMOS transistor.
7, cmos component as claimed in claim 1 is characterized in that wherein more comprising a metal silicide layer, is arranged between this stressor layers and this source/drain, and between this stressor layers and this gate electrode.
8, a kind of cmos component is characterized in that comprising:
One substrate is provided with at least one barrier assembly, and comprises one first stressor layers in this barrier assembly;
One gate electrode is located in this substrate;
One source pole/drain is located in this substrates of this gate electrode both sides and contacts described barrier assembly;
One stress buffer lining is configured in to compliance these gate electrode both sides and part extends to this substrate surface; And
One second stressor layers is located on this gate electrode, this stress buffer lining and this source/drain, and contacts with this stress buffer lining.
9, cmos component as claimed in claim 8, the thickness that it is characterized in that this stress buffer lining wherein is less than 500 dusts.
10, cmos component as claimed in claim 8 is characterized in that wherein the material of this stress buffer lining is a silica.
11, cmos component as claimed in claim 8 is characterized in that wherein the material of this first stressor layers is the laminated of silicon nitride, silicon oxynitride or silicon nitride and silicon oxynitride.
12, cmos component as claimed in claim 8 is characterized in that wherein the material of this second stressor layers is the laminated of silicon nitride, silicon oxynitride or silicon nitride and silicon oxynitride.
13, cmos component as claimed in claim 12 it is characterized in that wherein this silicon nitride and the laminated of silicon oxynitride are a tension stress layer, and this laminated upper strata has higher tensile force than its lower floor.
14, cmos component as claimed in claim 12 is characterized in that silicon nitride or silicon oxynitride that this lower floor's material wherein is a Silicon-rich, and the silicon nitride that this upper strata material is silicon nitride or rich nitrogen.
15, cmos component as claimed in claim 8, it is characterized in that wherein this second stressor layers tool tensile stress and this first stressor layers tool tensile stress, being covered in this gate electrode of second stressor layers below and the transistor of this source/drain formation is PMOS transistor and nmos pass transistor.
16, cmos component as claimed in claim 8, it is characterized in that wherein this second stressor layers tool compression stress and stretching of this first stressor layers tool or compression stress, being covered in this gate electrode of this second stressor layers below and the transistor of this source/drain formation is the PMOS transistor.
17, cmos component as claimed in claim 8 is characterized in that wherein more comprising a metal silicide layer, is arranged between this second stressor layers and this source/drain, and between this second stressor layers and this gate electrode.
18, cmos component as claimed in claim 16 is characterized in that wherein more comprising a metal silicide layer, is arranged between this second stressor layers and this source/drain, and between this second stressor layers and this gate electrode.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200420007675 CN2731717Y (en) | 2003-03-31 | 2004-03-30 | CMOS assembly |
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN03121501 | 2003-03-31 | ||
| CN03121501.7 | 2003-03-31 | ||
| CN 200420007675 CN2731717Y (en) | 2003-03-31 | 2004-03-30 | CMOS assembly |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN2731717Y true CN2731717Y (en) | 2005-10-05 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 200420007675 Expired - Lifetime CN2731717Y (en) | 2003-03-31 | 2004-03-30 | CMOS assembly |
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| CN (1) | CN2731717Y (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1301556C (en) * | 2003-03-31 | 2007-02-21 | 台湾积体电路制造股份有限公司 | CMOS assembly and its manufacturing method |
| CN104979294A (en) * | 2014-04-10 | 2015-10-14 | 中芯国际集成电路制造(上海)有限公司 | Manufacturing method of semiconductor device |
-
2004
- 2004-03-30 CN CN 200420007675 patent/CN2731717Y/en not_active Expired - Lifetime
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1301556C (en) * | 2003-03-31 | 2007-02-21 | 台湾积体电路制造股份有限公司 | CMOS assembly and its manufacturing method |
| CN104979294A (en) * | 2014-04-10 | 2015-10-14 | 中芯国际集成电路制造(上海)有限公司 | Manufacturing method of semiconductor device |
| CN104979294B (en) * | 2014-04-10 | 2019-10-25 | 中芯国际集成电路制造(上海)有限公司 | A kind of manufacturing method of semiconductor devices |
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Effective date of abandoning: 20040330 |
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