CN2724326Y - Automatic power control circuit for plasma TV - Google Patents
Automatic power control circuit for plasma TV Download PDFInfo
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- CN2724326Y CN2724326Y CN 200420093092 CN200420093092U CN2724326Y CN 2724326 Y CN2724326 Y CN 2724326Y CN 200420093092 CN200420093092 CN 200420093092 CN 200420093092 U CN200420093092 U CN 200420093092U CN 2724326 Y CN2724326 Y CN 2724326Y
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- 238000012545 processing Methods 0.000 claims abstract description 26
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- 238000001514 detection method Methods 0.000 claims description 24
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- 238000005070 sampling Methods 0.000 claims description 21
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Abstract
The utility model discloses an automatic power control circuit for plasma TV, comprising a code device, a data processing circuit, a data-driven controlling circuit, a pulse number processing circuit, a sample-taking resistor, a voltage amplifier, a microcontroller, a zero code checking module and a PDP module. Under the activation of a field synchronizing signal, the MCU generates the actual sustaining pulse numbers of each subfield and sends the pulse numbers to the pulse number processing circuit firstly according to input of the voltage amplifier to calculate a sum P of the standby power and the addressing power and secondly according to the comparative result between the power sum P and the valve quantity power. The utility model carries out a real-time detection towards the major output power of the power supply, according to which the course of discharge is controlled and sustained. Owing to that brightness level of the PDP changes progressively, which is hard to be detected by human eyes, so uncomfortable feeling is not caused.
Description
Technical field
The utility model belongs to plasm TV (PDP) Display Technique field, particularly a kind of automatic power control circuitry of PDP demonstration.
Background technology
Plasma display panel (PDP) is made up of a large amount of small discharge cells, is relation in parallel on electrically connecting between each discharge cell, and the average current of the each discharge of each discharge cell is certain.Like this, if the element number of discharge of same time (as a TV Field) is many more, discharging current is just big more, and what of the display unit lighted are the size of power consumption depend in other words, and the consumption of power increases along with the increase of the display unit of lighting.After being increased to a certain degree, the consumption of power may surpass the limit that can allow, if at this moment this situation is not limited, its words that develop down of leaving, concerning power supply, can cause overload, also may have influence on the discharge stability of each display unit, show unsettled situation thereby produce whole screen.
A kind of method that addresses this problem is to improve the power output of power supply, makes it that all discharge cells needed electric current that discharges simultaneously can be provided.But cost can improve like this, and in most of the cases, each pixel cell is not to light simultaneously on the screen; Another kind method is exactly the quantity of managing to reduce the unit of same time discharge, promptly reduces brightness degree and reduces power consumption.But can't address this problem well with the original brilliance control technology of PDP, the consumption of power still can surpass the limit that can allow once in a while.In order to prevent this situation, introduced automated power control (Automatic Power Control is abbreviated as APC) technology and come the mandatory down low brightness levels, so that power consumption is limited in the scope that can allow.
Traditional automatic power control system is a kind of control system that has feedback amplifier, it is sampled to the electric current of PDP power supply to power supply by sample circuit, convert level signal to, through amplifying the A/D input of sending into single-chip microcomputer, sampling through Chip Microcomputer A/D input channel, and, obtain an eight bit through after the A/D conversion.This number and a predefined numerical value compare, if greater than set point, then reduce the brightness degree of PDP gradually.
Summary of the invention
The purpose of this utility model is to provide a kind of novel automatic power-controlling device for PDP shows.This device is only monitored the main discharge process of each son field, and keeps discharge process by control and realize automated power control, has the effective and characteristic of simple structure of control.
In color PDP, a TV Field (abbreviating the field as) is divided into successively luminous a plurality of sons field.Realize that 256 grades of gray scales show, need weight to be respectively eight son fields of 1,2,4,8,16,32,64 and 128 (binary codings) at least.Various combination by these eight son fields is realized its gray scale.The procedure for displaying of each son field is subdivided into initial period, address period again and keeps the phase, and discharge process all takes place during each: the discharge process of address period is called address discharge; The discharge process of keeping the phase is called keeps discharge.The power of PDP power supply output, overwhelming majority consumption is being kept discharge process, also has quite a few to consume in the address discharge process, and the power that the discharge process of baseline consumes is seldom.Based on this, the monitoring target of automated power controlling schemes of the present utility model comprises keeps discharge process and address discharge process, and controlling object is to keep discharge process.
The automatic power-controlling device of the utility model design comprises encoder, data processing circuit, data drive control circuit, umber of pulse treatment circuit, sampling resistor, voltage amplifier, microcontroller (MCU) and PDP module.Wherein, encoder, data processing circuit, data drive control circuit and umber of pulse treatment circuit are the basic circuits of existing PDP.
Encoder is encoded to the data image signal (RGB) of input.Coding output is sent into data processing circuit and is handled, and sends into data drive control circuit control address discharge and other function after the processing respectively and sends into number of times and other function that the umber of pulse processing circuit controls is kept discharge, and these belong to prior art.
Sampling resistor comprises first sampling resistor and second sampling resistor.Correspondingly, voltage amplifier also comprises first voltage amplifier and second voltage amplifier.The output current Ia of addressing power supply Va produces first sampled voltage Ia * Ra on the first sampling resistor Ra, send into MCU after first voltage amplifier amplifies; The output current Is that keeps power supply Vs produces second sampled voltage Is * Rs on the second sampling resistor Rs, send into MCU after second voltage amplifier amplifies.
MCU is under the triggering of field sync signal, at first calculate current holding power and addressing power sum P according to the input of first, second voltage amplifier, according to the comparative result of power and P and valve value rate, produce each son actual umber of pulse of keeping and send into the umber of pulse treatment circuit again.The detection of power and control are unit with the field.
As power and P during greater than valve value rate, the PDP power supply is near overload, and MCU will current each son keeps umber of pulse and multiply by one greater than zero less than 1 multiplication factor, and the actual umber of pulse of keeping is reduced with the reduction power consumption.As power and P during less than valve value rate, belong to normal demonstration, do not need power-limiting, but the current not necessarily preset value of umber of pulse of keeping needs the current umber of pulse of keeping is adjusted back to preset value step by step.When keeping umber of pulse, carry out the current umber of pulse of keeping when current, increase the current umber of pulse of keeping divided by multiplication factor less than preset value; When keeping umber of pulse and being not less than preset value, the current umber of pulse of keeping is taken as preset value, when current with the influence of remove quantization error.Because the image that shows is continuous transition (except that camera lens switches) in terms of content, the change procedure of this brightness also is gradual change, and human eye is difficult for discovering.
After next field sync signal arrives, MCU recomputate power and P and with valve value rate relatively, if P still greater than valve value rate, then keeps on the umber of pulse basis at Shang Yichang, multiply by multiplication factor again, further reduce to keep umber of pulse ..., the rest may be inferred.
In the middle of the reality, a certain sub-field code that may occur all pixels in a field time all is zero situation, this means in all unit of this sub-field period all not luminous.Since not luminous, also just need not to carry out the addressing process of this child field correspondence and keep pulse.If can cancel the addressing process of this child field and keep pulse, will reduce the power consumption of address discharge and the switching loss of drive circuit respectively, thereby further reduce the power supply power consumption of PDP.Given this, the utility model can also carry out following improvement:
Increasing by one zero sign indicating number detection module on the original structure basis, all is that zero situation detects to a certain sub-field code of all pixels.Like this, the coding of encoder is exported one the tunnel and is entered data processing circuit, and zero sign indicating number detection module is sent on another road.Data drive control circuit and umber of pulse treatment circuit are sent in zero sign indicating number detection module output " zero code word Z ".
Zero sign indicating number detection module comprises N counter and zero testing circuit, and wherein N equates with a son number, is generally 8～12.The code signal of each son field of encoder output when sending into data processing circuit, also respectively is sent to the Enable Pin of a counter respectively.The counting clock of individual count device all is the data clock signal of data image signal, and reset signal all is a field sync signal.
If the count value that the individual count device is is respectively Q
1, Q
2..., Qn.If Q
1Be zero, zero sign indicating number detection module output Z
1Be ' 1 ', illustrate that all unit are all not luminous at the 1st sub-field period.In like manner, zero sign indicating number detection module output Zi is ' 1 ', illustrates that at the i sub-field period all unit are all not luminous.The data drive control circuit is according to zero code word Z
1, Z
2..., ' 1 ' position among the Zn, cancel the addressing process of corresponding son, reduce addressing power consumption; The umber of pulse treatment circuit is according to zero code word Z
1, Z
2..., ' 1 ' position among the Zn, cancel the pulse of keeping of corresponding son, reduce the switching loss of drive circuit, further reduced the power consumption of PDP.
Compared with prior art, the utility model technology has following advantage:
1, the main output power to power supply detects in real time, and when detection power value during greater than a certain setting threshold values, beginning reduces the brightness degree of PDP step by step so that reduce power consumption; Otherwise when the detection power value was not more than the setting threshold values, recovering step by step to keep umber of pulse was preset value.Because the brightness degree of PDP changes step by step, human eye is difficult for discovering, and can not produce uncomfortable sensation.
2, the sub-field code to data image signal carries out zero sign indicating number detection, when zero sign indicating number occurring, cancels the addressing process of this code value correspondence and keeps pulse, reduces the power consumption of address discharge and the switching loss of drive circuit respectively, has further reduced the power supply power consumption of PDP.
Below in conjunction with drawings and Examples the utility model is described further.
Description of drawings
Fig. 1 is sub-field structure schematic diagram.
Fig. 2 is the circuit structure diagram of the utility model first embodiment.
Fig. 3 produces the flow chart of actual sustain umber of pulse for MCU.
Fig. 4 is the circuit structure diagram of the utility model second embodiment.
Fig. 5 is zero a sign indicating number detection module circuit diagram among second embodiment.
Among the figure, 1 is encoder, 2 is data processing circuit, and 3 is the data drive control circuit, and 4 is first sampling resistor (Ra), 5 is second sampling resistor (Rs), 6 is first voltage amplifier, and 7 is second voltage amplifier, and 8 is microcontroller (MCU), 9 is the umber of pulse treatment circuit, and 10 is zero sign indicating number detection module.
Embodiment
In the utility model first embodiment, automatic power-controlling device does not comprise zero sign indicating number detection module.
As shown in Figure 2, the present embodiment device comprises encoder 1, data processing circuit 2, data drive control circuit 3, first sampling resistor 4, second sampling resistor 5, first voltage amplifier 6, second voltage amplifier 7, microcontroller 8, umber of pulse treatment circuit 9 and PDP module.Wherein, encoder 1, data processing circuit 2, data drive control circuit 3 and umber of pulse treatment circuit 9 are basic circuits of existing PDP.
The data image signal (RGB) of 1 pair of input of encoder is encoded.Coding output is sent into data processing circuit 2 and is handled, and sends into data drive control circuit 3 control address discharge and other functions after the processing respectively and sends into number of times and other function that discharge is kept in 9 controls of umber of pulse treatment circuit, and these belong to prior art.
The output current Ia of addressing power supply Va produces first sampled voltage Ia * Ra on first sampling resistor 4, send into microcontroller 8 after first voltage amplifier 6 amplifies Ka times; The output current Is that keeps power supply Vs produces second sampled voltage Is * Rs on second sampling resistor 5, send into microcontroller 8 after second voltage amplifier 7 amplifies Ks times.
Referring to Fig. 3, microcontroller 8 is under the triggering of field sync signal, at first calculate current holding power and addressing power sum P: the magnitude of voltage of first voltage amplifier, 6 input microcontrollers 8 is Ia * Ra * Ka, this value is converted to quantized value through the A/D of microcontroller 8 inside, this quantized value multiply by Va, promptly obtains the power output of addressing power supply again divided by the product of Ra and Ka; The magnitude of voltage of second voltage amplifier, 7 input microcontrollers 8 is Is * Rs * Ks, and this value is converted to quantized value through the A/D of microcontroller 8 inside, and this quantized value multiply by Vs, promptly obtains keeping the power output of power supply again divided by the product of Rs and Ks.
In the present embodiment, valve value rate is taken as the PDP power supply and exports 90% of specified power P r, and obviously, valve value rate can also be higher or lower than this value.As power and P during greater than valve value rate, the PDP power supply is near overload, and the umber of pulse of keeping that microcontroller 8 will current each son multiply by multiplication factor, and the result is sent to umber of pulse treatment circuit 9, thereby the actual umber of pulse of keeping is reduced with the reduction power consumption.Multiplication factor is taken as 0.95 in the present embodiment, can also be taken as other certainly less than 1 greater than 0 number, as 0.98,0.93,0.9 etc.As power and P during less than valve value rate, belong to normal demonstration, do not need power-limiting, but the current not necessarily preset value of umber of pulse of keeping, need the current umber of pulse of keeping is adjusted back to preset value step by step: when current when keeping umber of pulse less than preset value, carry out the current umber of pulse of keeping divided by multiplication factor 0.95, increase the current umber of pulse of keeping; When keeping umber of pulse and being not less than preset value, the current umber of pulse of keeping is taken as preset value, when current with the influence of remove quantization error.
After next field sync signal arrives, microcontroller 8 recomputate power and P and with valve value rate relatively, if P is still greater than 90% of rated power Pr, then keep on the umber of pulse basis, multiply by multiplication factor 0.95 again, further reduce to keep umber of pulse at Shang Yichang,, the rest may be inferred.
The present embodiment device detects in real time to the main output power of power supply, and when detection power value during greater than a certain setting threshold values, beginning reduces the brightness degree of PDP step by step so that reduce power consumption; Otherwise when the detection power value was not more than the setting threshold values, recovering step by step to keep umber of pulse was preset value.Because the brightness degree of PDP changes step by step, human eye is difficult for discovering, and can not produce uncomfortable sensation.
In the utility model second embodiment, TV Field is divided into 8 successively luminous sons, and the sub-number of fields of certain TV Field can also be other values such as 9,10,11,12, and automatic power-controlling device comprises zero sign indicating number detection module.
As shown in Figure 4, the present embodiment device comprises encoder 1, data processing circuit 2, data drive control circuit 3, first sampling resistor 4, second sampling resistor 5, first voltage amplifier 6, second voltage amplifier 7, microcontroller 8, umber of pulse treatment circuit 9, zero sign indicating number detection module 10 and PDP module.As previously mentioned, encoder 1, data processing circuit 2, data drive control circuit 3 and umber of pulse treatment circuit 9 are basic circuits of existing PDP.
Identical with first embodiment, the data image signal (RGB) of 1 pair of input of encoder is encoded.Coding output is sent into data processing circuit 2 and is handled, and sends into data drive control circuit 3 control address discharge and other functions after the processing respectively and sends into number of times and other function that discharge is kept in 9 controls of umber of pulse treatment circuit, and these belong to prior art.The output current Ia of addressing power supply Va produces first sampled voltage Ia * Ra on first sampling resistor 4, send into microcontroller 8 after first voltage amplifier 6 amplifies Ka times; The output current Is that keeps power supply Vs produces second sampled voltage Is * Rs on second sampling resistor 5, send into microcontroller 8 after second voltage amplifier 7 amplifies Ks times.Microcontroller 8 at first calculates current holding power and addressing power sum P according to the input of first voltage amplifier 6, second voltage amplifier 7, according to the comparative result of power and P and valve value rate Pr, produce each son actual umber of pulse of keeping and send into umber of pulse treatment circuit 9 again.The detection of power and control are unit with the field.
Different with first embodiment is, the coding of encoder 1 is exported one the tunnel and entered data processing circuit 2, and zero sign indicating number detection module 10 is sent on another road.Referring to Fig. 5, SF
1, SF
2..., SF
8Be the coding of each height field of encoder 1 output, DCLK is the data clock signal of data image signal, and VSYNC is a field sync signal, and zero sign indicating number detection module 10 comprises 8 counters and zero testing circuit.The code signal of 8 sons of encoder 1 output respectively is sent to the Enable Pin of a counter respectively, and the counting clock of individual count device all is the data clock signal DCLK of data image signal, and reset signal all is field sync signal VSYNC.
Counter is similar to the processing procedure of each sub-field code, only with the 1st sub-field code SF
1Passage is an example, works as SF
1For ' 1 ' time, the first counter Enable Pin EN is ' 1 ', and count value adds 1; Work as SF
1For ' 0 ' time, the first counter Enable Pin EN is ' 0 ', can not count, and promptly count value is constant.Through the processing of a field time, the count value Q of first counter
1, be illustrated in the full frame luminous pixel count of the 1st sub-field period.In like manner, Qi is illustrated in the i sub-field period, full frame luminous pixel count.
The individual count device outputs to zero testing circuit with one count value, and data drive control circuit 3 and umber of pulse treatment circuit 9 are sent in zero sign indicating number testing circuit output " zero code word Z ".Through the counting of a field time, if Q
1Be zero, zero sign indicating number testing circuit output Z
1Be ' 1 ', illustrate that all unit are all not luminous at the 1st sub-field period.In like manner, zero sign indicating number testing circuit output Zi is ' 1 ', illustrates that at the i sub-field period all unit are all not luminous.Data drive control circuit 3 is according to zero code word Z
1, Z
2..., ' 1 ' position among the Zn, cancel the addressing process of corresponding son, reduce addressing power consumption; Umber of pulse treatment circuit 9 is according to zero code word Z
1, Z
2..., ' 1 ' position among the Zn, cancel the pulse of keeping of corresponding son, reduce the switching loss of drive circuit, the power consumption of PDP is further fallen.
The present embodiment device has the advantage of first embodiment device.Simultaneously,, when zero sign indicating number occurring, cancel the addressing process of this code value correspondence and keep pulse, reduce the power consumption of address discharge and the switching loss of drive circuit respectively, thereby can further reduce the power supply power consumption of PDP owing to also comprise zero sign indicating number detection module 10.
Claims (10)
1. plasm TV automatic power control circuitry, comprise encoder (1), data processing circuit (2), data drive control circuit (3), umber of pulse treatment circuit (9) and PDP module, encoder (1) is encoded to the data image signal of input, coding output is sent into data processing circuit (2) and is handled, send into data drive control circuit (3) and umber of pulse treatment circuit (9) after the processing respectively, it is characterized in that: also comprise first sampling resistor (4), second sampling resistor (5), first voltage amplifier (6), second voltage amplifier (7) and microcontroller (8);
The output current of addressing power supply is gone up at first sampling resistor (4) and is produced first sampled voltage, sends into microcontroller (8) after first voltage amplifier (6) amplifies; Keep the output current of power supply and go up generation second sampled voltage, after second voltage amplifier (7) amplifies, send into microcontroller (8) at second sampling resistor (5);
Microcontroller (8) is under the triggering of field sync signal, at first calculate current holding power and addressing power sum P according to the input of first voltage amplifier (6) and second voltage amplifier (7), according to the comparative result of power and P and valve value rate, produce each son actual umber of pulse of keeping and send into umber of pulse treatment circuit (9) again.
2. automatic power control circuitry according to claim 1, it is characterized in that: as power and P during greater than valve value rate, microcontroller (8) multiply by one greater than zero less than 1 multiplication factor with the umber of pulse of keeping of current each son, and the actual umber of pulse of keeping is reduced to reduce power consumption; When power and P less than valve value rate, but current when keeping umber of pulse less than preset value, microcontroller (8) is carried out the current umber of pulse of keeping divided by multiplication factor, increases the current umber of pulse of keeping; When power and P less than valve value rate, but current when keeping umber of pulse more than or equal to preset value, microcontroller (8) is taken as preset value with the current umber of pulse of keeping, with the influence of remove quantization error;
After next field sync signal arrives, microcontroller (8) recomputate power and P and with valve value rate relatively, multiply by multiplication factor on the umber of pulse basis again if P still greater than valve value rate, then keeps at Shang Yichang.
3. automatic power control circuitry according to claim 1 and 2 is characterized in that: described device also comprises zero sign indicating number detection module (10);
Zero sign indicating number detection module (10) comprises N counter and zero testing circuit, wherein N equates with a son number, the code signal of each son field of encoder (1) output, when sending into data processing circuit (2), also respectively be sent to the Enable Pin of a counter respectively, the counting clock of individual count device all is the data clock signal of data image signal, and reset signal all is a field sync signal;
The individual count device outputs to zero testing circuit with one count value, and data drive control circuit (3) and umber of pulse treatment circuit (9) are sent in zero sign indicating number testing circuit output " zero code word Z "; Data drive control circuit (3) is according to zero code word Z
1, Z
2..., ' 1 ' position among the Zn, cancel the addressing process of corresponding son; Umber of pulse treatment circuit (9) is according to zero code word Z
1, Z
2..., ' 1 ' position among the Zn, cancel the pulse of keeping of corresponding son.
4. automatic power control circuitry according to claim 3 is characterized in that: described multiplication factor value is 0.95.
5. automatic power control circuitry according to claim 3 is characterized in that: described multiplication factor value is 0.98 or 0.93 or 0.9.
6. automatic power control circuitry according to claim 3 is characterized in that: described N value is 8.
7. automatic power control circuitry according to claim 4 is characterized in that: described N value is 8.
8. automatic power control circuitry according to claim 5 is characterized in that: described N value is 8.
9. automatic power control circuitry according to claim 3 is characterized in that: described N value is 9 or 10 or 11 or 12.
10. automatic power control circuitry according to claim 5 is characterized in that: described N value is 9 or 10 or 11 or 12.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200420093092 CN2724326Y (en) | 2004-09-07 | 2004-09-07 | Automatic power control circuit for plasma TV |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200420093092 CN2724326Y (en) | 2004-09-07 | 2004-09-07 | Automatic power control circuit for plasma TV |
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| Publication Number | Publication Date |
|---|---|
| CN2724326Y true CN2724326Y (en) | 2005-09-07 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 200420093092 Expired - Fee Related CN2724326Y (en) | 2004-09-07 | 2004-09-07 | Automatic power control circuit for plasma TV |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105741765A (en) * | 2016-04-06 | 2016-07-06 | 康佳集团股份有限公司 | Power control method and system of display device and smart TV |
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2004
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105741765A (en) * | 2016-04-06 | 2016-07-06 | 康佳集团股份有限公司 | Power control method and system of display device and smart TV |
| CN105741765B (en) * | 2016-04-06 | 2018-06-26 | 康佳集团股份有限公司 | A kind of Poewr control method of display device, system and smart television |
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Granted publication date: 20050907 Termination date: 20110907 |