CN2722434Y

CN2722434Y - CMOS reverse controller with multiple-grid transistor

Info

Publication number: CN2722434Y
Application number: CN 200420059368
Authority: CN
Inventors: 杨育佳; 杨富量; 胡正明
Original assignee: Taiwan Semiconductor Manufacturing Co TSMC Ltd
Current assignee: Taiwan Semiconductor Manufacturing Co TSMC Ltd
Priority date: 2004-06-10
Filing date: 2004-06-10
Publication date: 2005-08-31
Anticipated expiration: 2014-06-10

Abstract

The utility model discloses a CMOS reverse controller with multiple-grid transistor. The CMOS reverse controller with multiple-grid transistor includes that: at least a first multiple-grid transistor which includes a first source electrode connected to a power supply, a first drain electrode connected to an output end, and a first grid electrode; at least a second multiple-grid transistor which includes a second source electrode connected to a ground terminal, a second drain electrode connected to the output end, and a second grid electrode; an input end connected to the first grid electrode and the second grid electrode.

Description

Use the CMOS (Complementary Metal Oxide Semiconductor) transistor reverser of multi-gated transistor

Technical field

The utility model relates to a kind of silicon-on-insulator (silicon on insulator, circuit SOI), and particularly relevant for a kind of CMOS transistor reverser that uses multi-gated transistor.

Background technology

Metal oxide semiconductcor field effect transistor (metal-oxide-semiconductor field effecttransistor, MOSFET) technology be produce great scale integrated circuit (ultra-large scaleintegrated, ULSI) in topmost semiconductor technology.In the past in the several years, the progress that the reducing of MOSFETs size provides every Elementary Function (unit function) to continue on speed and efficiency, current densities and cost.Do more more hour when the grid length (gate length) of conventional MOS FET, the interaction between source electrode and drain electrode and channel and the grid can increase, thereby can impact channel current potential (channel potential).Therefore, have the MOSFET of short gate length, have grid actually and problem that can't the control channel Push And Release.The phenomenon that this MOSFET grid control weakens is referred to as short channel effect (short-channel effects).Generally speaking, can utilize the concentration that increases body and mix, thickness and the utmost point shallow source/drain contact methods such as (ultra-shallow source/drain iunctions) that reduces grid oxic horizon to suppress short channel effect.Yet, traditional components structure based on bulk silicon substrate (bulk silicon substrates), when its size of components entered the scope of time 50 nanometers (sub-50nm), the requirement of the body doping content under this scope, thickness of grid oxide layer and source/drain doping profile (doping profile) etc. can increase the difficulty in many realizations.Therefore, along with size of components is day by day dwindled, on the front end processing procedure, must innovate or use alternative modular construction just can avoid short channel effect to some extent.

When size of components entered the scope of time 30 nanometers, using the replacement assemblies structure with multiple-grid utmost point electrode (multiple-gateelectrodes) to control short channel effect was a suitable useful method.The multiple-gate mosfets structure is expected the ductility (scalability) of CMOS transistor (CMOS) technology can be extended beyond the restriction of conventional MOS FET, and can reach the final restriction of silicon MOSFET.The electric capacity of this extra grid meeting reinforcing grid that adds and interchannel coupling increases the control of grid to the channel current potential, helps to suppress short channel effect, and the ductility of prolongation MOSFET.

The simple case of multiple-grid utmost point assembly is exactly a bigrid MOSFET structure, and the manufacture method of this structure has description in United States Patent (USP) the 6413802nd B1 number of people such as Hu.Figure 1A is the top view of the bigrid MOSFET in the patent for this reason, and Figure 1B is the cross-sectional view along 1B-1B ' among Figure 1A.This structure has two gate electrodes at the two opposite sides of channel or silicon body (silicon body).The channel of bigrid MOSFET comprises a thin semiconductor fin 13, and this semiconductor fin 13 is to have an insulating barrier 11 on the surface (for example: form on the silicon substrate 10 silica), and use an etch shield 14 to define.Form gate dielectric 12 again in semiconductor fin 13 sides, carry out the step of gate deposition (gatedeposition) and gate patternization (gate patterning) then, form two grid structure in the side of semiconductor fin 13, gate electrode 15 is striden and is stood on the semiconductor fin 13, and the both sides that separate from semiconductor fin 13 form two grids.Etch shield 14 among United States Patent (USP) the 6413802nd B1 is retained in processing procedure in the channel region on the semiconductor fin 13 from the beginning to the end.

The element width of single semiconductor fin (device width) is defined as the twice of semiconductor fin height h1, and the semiconductor fin width of change bigrid MOSFET can't impact element width.A plurality of semiconductor fin are arranged in parallel within the width that can obtain multicompartment on the identical substrate.Fig. 2 A is two parallel connected top views of bigrid MOSFETs, and Fig. 2 B is the cross-sectional view along 2B-2B ' among Fig. 2 A.Two parallel connected element width of bigrid MOSFETs are 4h1.

Pursue the high-effect optimization technique that has forced logic and circuit designers must on their design configurations, use various delays and zone incessantly.On logic synthetic (logic synthesis), the optimization of delay seriously relies on the grid size algorithm, and the grid size algorithm is the delay that the actuating force (drive strengths) of change grid is come optimization circuits.

Nverter circuit comprises the MOSFETs of a pair of complementation, i.e. the circuit of a CMOS framework.The circuit of this CMOS framework comprises P channel MOSFET (PMOS) and N channel MOSFET (NMOS).The width that delay in the CMOS logical circuit does not just rely on actuating force at different levels and relies on PMOS and NNOS assembly is than (P/N width ratio).Concerning optimization circuits usefulness or circuit delay time, if can select a P/N width that is fit to freely than being quite favourable.

Nverter circuit can form with NMOS that comprises single or multiple semiconductor fin and PMOS.But, utilize the PMOS and the NMOS of the bigrid MOSFET structure among Fig. 1 and Fig. 2, because have identical semiconductor fin 15 height, just can not provide the P/N width ratio of successive range.For instance, if the PMOS of reverser uses two fins and NMOS to use a fin, then P/N width ratio is 2.If the PMOS of reverser uses three fins and NMOS to use two fins, then P/N width ratio is 1.5.That is to say that this P/N width can not change continuously than being the quotient of two integers.Therefore, can not directly use this bigrid MOSFET structure to make one simply and have the P/N width than 1.35 reverser.

A kind of mode of using this bigrid MOSFET structure and can changing P/N width ratio continuously is with a PMOS layer 31 and NMOS layer 32 perpendicular alignmnet and with the stack architecture of a dielectric layer 35 separations, the one deck of covering etch shield 36 is also arranged above, gate electrode 37 separates source electrode and drain electrode from the centre, as shown in Figure 3.This structure is narrated in United States Patent (USP) the 6413802nd B1, and PMOS layer 31 has a thickness t _PMOSAnd NMOS layer 32 has a thickness t _NMOS, thickness t _PMOSWith thickness t _NMOSCan when crystalline substance of heap of stone, adjust.The thickness ratio of 31 pairs of NMOS layer 32 of PMOS layer, i.e. t _PMOS/ t _NMOS, be exactly P/N width ratio, can in a big scope, change.Yet, the stack architecture shown in Fig. 3, and be difficult for making.It need have the PMOS layer 31 of one deck crystallization on dielectric layer 35, must utilize grow up the again technology of (lateral epitaxial overgrowth) of solid-state crystalline substance of heap of stone (solidphase epitaxy) and side direction, these technology are that very costliness and prouctiveness are very low.

Now design and make multiple-grid utmost point assembly for example bigrid a few thing progress is arranged, but then rare people drops into wherein aspect circuit, the Nverter circuit that for example utilizes this kind multiple-grid utmost point assembly to dispose.Yet, on the optimization of circuit, use the Nverter circuit of multiple-gate mosfets not to be suggested as yet so far merely.But finding out a simple method, provide best P/N width ratio to the reverser with multiple-gate mosfets, is quite difficult.

The utility model content

Therefore the purpose of this utility model is exactly that a kind of CMOS transistor reverser of multi-gated transistor is being provided, in order to provide can modulation P/N width ratio.

According to above-mentioned purpose of the present utility model, a kind of CMOS transistor reverser of multi-gated transistor is proposed.Source electrode to one power supply unit that connects P channel multi-gated transistor, drain electrode then is connected to output.The source electrode that connects N channel multi-gated transistor is connected to earth terminal, and drain electrode then is connected to this output.The P channel all is connected with input with the gate electrode of N channel multi-gated transistor.So can obtain a CMOS transistor reverser that utilizes multi-gated transistor to form.

According to a preferred embodiment of the present utility model, above-mentioned multi-gated transistor comprises tri-gate transistor and AOMIGE (omega: Ω) field-effect transistor.This multi-gated transistor has semiconductor fin on the substrate that covers insulating barrier, gate dielectric is positioned at the semiconductor fin surface, and gate electrode is arranged in gate dielectric surface and source electrode and drain electrode and is located in the gate electrode both sides respectively and is positioned at this semiconductor fin.This source electrode and drain surface have a conductor layer.

According to the utility model one preferred embodiment, the material of insulating barrier is a dielectric material, the material of semiconductor fin is silicon or germanium, and the material of gate dielectric is that silicon dioxide, silicon oxynitride or dielectric constant are higher than 5 high dielectric constant material for example lanthana, aluminium oxide, hafnium oxide, nitrogen hafnium oxide and zirconia.The material of gate electrode is polysilicon, polycrystalline silicon germanium or metal.The material of conductor layer is metal or metal silicide.

The beneficial effects of the utility model are, utilize multi-gated transistor to form the CMOS transistor reverser, because multi-gated transistor has better grid control than conventional transistor, can avoid short channel effect effectively.And, because have big gate area, electric current in its channel also can be big more, in the assembly running now, have the considerable time all to expend with the electric capacity charge or discharge, if available electric current is big more, required time of capacitor charge and discharge is short more, the speed of this assembly is also just fast more, the usefulness of lifting subassembly running significantly.

Description of drawings

Figure 1A is the top view of the bigrid MOSFET of prior art;

Figure 1B is the cross-sectional view along 1B-1B ' among Figure 1A;

Fig. 2 A is two parallel connected top views of bigrid MOSFETs of prior art;

Fig. 2 B is the cross-sectional view along 2B-2B ' among Fig. 2 A;

Fig. 3 is the perspective view that prior art is utilized the CMOS reverser of PMOS and NMOS storehouse composition;

Fig. 4 A is the top view of tri-gate transistor structure;

Fig. 4 B is the cross-sectional view along 4B-4B ' among Fig. 4 A;

Fig. 5 is the perspective view of Ω-FET.

Fig. 6 is the perspective view of the CMOS reverser of the utility model one preferred embodiment;

Fig. 7 is the topology layout figure of CMOS reverser among Fig. 6;

Fig. 8 is the circuit diagram of CMOS reverser among Fig. 6;

Fig. 9 A is the topology layout figure of the CMOS reverser of another preferred embodiment of the utility model;

Fig. 9 B is the topology layout figure of the CMOS reverser of another preferred embodiment of the utility model;

Figure 10 is the topology layout figure of the CMOS reverser of another preferred embodiment of the utility model;

Figure 11 A～11E is the cross-section structure schematic flow sheet that the utility model is made tri-gate transistor;

Figure 12 A～12B is the cross-section structure schematic flow sheet that the utility model is made Ω-FET;

Wherein, description of reference numerals is as follows:

10: silicon substrate 11: insulating barrier

12: gate dielectric 13: semiconductor fin

14: etch shield 15: gate electrode

31:PMOS layer 32:NMOS layer

35: dielectric layer 36: etch shield

37: gate electrode 50: substrate

51: insulating barrier 52: gate dielectric

53: semiconductor fin 55: gate electrode

561: source electrode 562: drain electrode

57: undercutting 60: substrate

61: insulating barrier 621: gate dielectric

622: gate dielectric 63: semiconductor fin

651: gate electrode 652: gate electrode

661:NMOS drain electrode 662:PMOS drain electrode

671:NMOS source electrode 672:PMOS source electrode

71: metal wire 72: metal wire

73: metal wire 74: gate contact

75: metal wire 76: drain contact

92: the two PMOS of 91: the one PMOS

94: the PMOS of 93: the one NMOS

96: the first semiconductor fin of 95: the second semiconductor fin

98: the three PMOS of 97: the three semiconductor fin

101: gate electrode 102:NMOS

103:PMOS 104: semiconductor fin

105: semiconductor fin 110: substrate

111: insulating barrier 111A: insulating barrier

112: silicon thin film 112A: semiconductor fin

113: etch shield 114: gate dielectric

114A: gate dielectric 115: gate electrode

115A: gate electrode 116: semiconductor fin top surface

117: semiconductor fin side 121: undercutting

Embodiment

The utility model proposes a kind of CMOS transistor reverser that uses multiple-gate mosfets.

In the utility model, use top surface in semiconductor fin to have the multiple-gate mosfets of a grid to dispose a Nverter circuit and solve existing problem.The top surface of this semiconductor fin has the multiple-gate mosfets of a grid to comprise three gate MOS FET and AOMIGE field-effect transistor (Ω-FET).Three gate MOS FET structures have three grids, and grid is at the top surface of semiconductor fin, and two grids are on the both sides of semiconductor fin.Because many grids at the top of semiconductor fin, three grid assemblies have better grid control than the bigrid assembly.

Fig. 4 A is the top view of three gate MOS FET, and Fig. 4 B is the cross-sectional view along 4B-4B ' among Fig. 4 A.Except the etch shield 14 at the top surface of semiconductor fin 13 loseed, three gate MOS FET and bigrid MOSFET ten minutes were similar.Gate dielectric 12 coats three of semiconductor fin 13, and gate electrode 15 is striden and stood on the semiconductor fin 13.This gate electrode 15 forms three grids: a grid is positioned at the top surface of semiconductor fin 13, and two other grid lays respectively at two sides of semiconductor fin 13.The element width of three gate MOS FET is the semiconductor fin 13 height h that the width W of semiconductor fin 13 adds twice ₂, i.e. (2h ₂+ W).Note this kind modular construction, can adjust semiconductor fin 13 width W and change element width, and the value of semiconductor fin 13 width W can adjust by revising circuit layout.

Available insulating barrier with undercutting (undercut) is promoted the grid control of three gate MOS FET, because gate electrode is that (omega: Ω) shape, this kind structure is called as Ω-FET to an alphabetical AOMIGE at its section.As shown in Figure 5, be the perspective view of Ω-FET.The structure of Ω-FET comprises semiconductor fin 53, a gate dielectric 52, a gate electrode 55 and an one source pole 561 and a drain electrode 562.Semiconductor fin 53 is positioned at a substrate 50 tops, and substrate 50 has an insulating barrier 51 in the surface, and insulating barrier 51 forms a undercutting 57 in semiconductor fin 53 bottoms, and the following erosion amount of undercutting is R, and horizontal erosion amount is E.Gate dielectric 52 is positioned at semiconductor fin 53 surfaces, and gate electrode 55 is positioned at the surface of gate dielectric 52, and source electrode 561 is located in gate electrode 55 both sides respectively with drain electrode 562, and is arranged in semiconductor fin 53.

Semiconductor fin 53 below undercutting 57 are invaded by gate electrode 55 and are formed an alphabetical AOMIGE (omega: the Ω) grid structure of shape.It is quite similar to have the grid of coating fully of outstanding ductility (Gate-All-Around, GAA) transistorized structure, and use the processing procedure that is similar to bigrid or three gate MOS FET is very easy to make.This Ω-FET has a top grid, two side grids and special grid and extends.Therefore Ω-FET is exactly the transistor that grid almost coats whole silicon body.In fact, it is long more that electrode extends, and promptly horizontal erosion amount E is big more, and this structure is just more near the transistorized structure of GAA.

The intrusion of this gate electrode 55 can help to stop the electric field line of drain electrode 562; to protect channel and to promote the control ability of grid to channel; thereby alleviate the energy barrier that causes of drain electrode 562 voltages reduce effect (drain-induced barrier lowering, DIBL) and the usefulness that can promote short channel.What the intrusion (undercutting 57) of gate electrode relied on below the semiconductor fin 53 is the excision of insulating barrier 51 on the substrate 50, therefore forms a undercutting (undercut) on the substrate of semiconductor fin 55 base portions.The element width of Ω-FET is the summation of semiconductor fin 55 width W, twice semiconductor fin 55 height h3 and the horizontal erosion amount of twice E, i.e. (W+2h3+2E) can adjust semiconductor fin 55 width W and change element width.

The utility model provides a Nverter circuit of being made up of multiple-gate mosfets such as three gate MOS FET or Ω-FET.Fig. 6 is the perspective view of the utility model one embodiment, uses three gate MOS FET among Fig. 4 A to form a Nverter circuit.In Fig. 6, this reverser is the structure of single semiconductor fin 63, is positioned at substrate 60 tops with an insulating barrier 61, covers one

deck gate dielectrics

621 and 622 above the semiconductor fin 63.This semiconductor fin 63 is made up of silicon, and as a rule, semiconductor fin 63 can be used any semiconductor element (for example germanium), semiconducting alloy (for example silicon-germanium), or semiconducting compound (for example indium phosphide or GaAs) is formed.The semiconductor fin 63 of reverser has different thickness, and semiconductor fin 63 thickness that form the NMOS part are W _NMOS, be W and form PMOS semiconductor fin 63 thickness partly _PMOSIn this embodiment, the semiconductor fin 63 of NMOS and PMOS highly is all h ₂Yet,, semiconductor fin 63 height also need not be consistent, also can be different values in zones of different.

Reverser structure among Fig. 6 is to use the transistor of a pair of complementation, this transistorized complementary pair comprises N type nmos source 671 and drains 661 by gate electrode 651 separated N channel three gate MOS FET with N type NMOS, drains 662 by gate electrode 652 separated P channel three gate MOS FET with P type pmos source 672 with P type PMOS.In this embodiment,

gate electrode

651 and 652 material are that (poly-crystalline silicon poly-Si), and is subjected to the N type and mixes polysilicon in N channel three gate MOS FET, be subjected to the P type and mix in P channel three gate MOS FET.As a rule,

gate electrode

651 and 652 operable materials have polysilicon, polysilicon-germanium (polycrystalline silicon-germanium, poly-SiGe), refractory metal (for example molybdenum, tungsten), compound (for example titanium nitride) or other electric conducting material.

The layout of reverser structure as shown in Figure 7 among Fig. 6.The

gate electrode

651 and 652 of N channel and P channel three gate MOS FET is joined together.This reverser comprises a gate contact 74, and this gate contact 74 connects

gate electrode

651 and 652 to one metal wires 75, as the input V of reverser _InAnd, in the NMOS of N channel and P channel three gate MOS

FET drain electrode

661 and 662 of PMOS drain electrodes a drain contact 76 is arranged, be connected to the output V of reverser with a metal wire 72 _OutThe nmos source 671 of N channel three gate MOS FET is with a metal wire 71 ground connection, and the pmos source 672 of P channel three gate MOS FET is connected with power supply unit with a metal wire 73.The circuit diagram of the reverser structure among Fig. 6 is a typical Nverter circuit figure as shown in Figure 8.

According to another embodiment of the present utility model, reverser also can use the multiple-gate mosfets with a plurality of different in width semiconductor fin.Shown in Fig. 9 A, the multiple-gate mosfets of forming this reverser has the semiconductor fin of two kinds of different in width, and the D among the figure represents drain electrode, and S represents source electrode.First semiconductor fin 95 comprises two parts, and some is a NMOS 93, and the semiconductor fin width is W _NMOS1, another partly is a PMOS 91, the semiconductor fin width is W _PMOS1Second semiconductor fin 96 comprises two parts, and some is the 2nd NMOS 94, and the semiconductor fin width is W _NMOS2, another partly is the 2nd PMOS92, the semiconductor fin width is W _PMOS2As a rule, semiconductor fin width W _NMOS1, W _NMOS2, W _PMOS1With W _PMOS2Not necessarily identical.Output V is all received in the drain electrode of all MOSFETs among Fig. 9 A _Out, the grid of all MOSFETs is all received input V _In, the source electrode of all PMOS is all received power supply unit, and the source electrode of all NMOS ground connection all.

Above explanation describes the reverser structure of using multiple-gate mosfets s in detail, and the reverser of this type has multiple variation to be implemented.NMOS in the utility model and PMOS assembly need be on same semiconductor fin, and Fig. 9 B is another embodiment of the utility model, illustrate to use one the 3rd semiconductor fin 97 to form the semiconductor fin width W _PMOS3The 3rd PMOS 98, other all configurations are identical with Fig. 9 A.

Figure 10 is another embodiment of the utility model, illustrates that NMOS can have different semiconductor fin width with the semiconductor fin of PMOS and material also can be inequality, and the D among the figure represents drain electrode, and S represents source electrode.NMOS102 has semiconductor fin 104, and semiconductor fin 104 width are W _NMOS, PMOS103 has semiconductor fin 105, and semiconductor fin 105 width are W _PMOS, the gate electrode of NMOS102 and PMOS105 is a gate electrode 101.Therefore, the semiconductor fin with different in width can comprise the multiple-gate mosfets s of same type, for example: two PMOS.

The manufacturing process of making three gate MOS FET and Ω-FET is below described.Figure 11 has shown the flow process of making three gate MOS FET.Figure 11 A～Figure 11 E represents the profile of three gate MOS FET in different fabrication steps.Shown in Figure 11 A, substrate 110 at the beginning is a soi structure, and covers one deck silicon thin film 112 on insulating barrier 111, and the thickness of this insulating barrier 111 is between 20 to 1000 .This insulating barrier 111 can use any dielectric material, and in this embodiment, this dielectric material uses silica.

Use an etch shield 113 to come patterned semiconductor fin 112A, shown in Figure 11 B.This etch shield 113 comprises the material that is commonly used to carry out etch process, photoresistance for example, and silica and silicon nitride etc., in this embodiment, this etch shield is to use silica.In the utility model, can select to use the fin step (fin surface smoothing step) that has an even surface to reduce the surface roughness of semiconductor fin side 117.Fin have an even surface step be semiconductor fin 112A is handled (silicon sidewall treatment) through sacrificial oxidation (sacrificialoxidation) and/or silicon side processing procedure (for example: at H ₂Carry out 1000 ℃ high annealing in the environment), can obtain good carrier transport factor (carriermobilities).

If be to use silica as etch shield 113 among the embodiment, this etch shield 113 can be removed before or after fin has an even surface step.The etch shield 113 of silica was removed before or after fin has an even surface step, and the profile that can influence semiconductor fin top surface 117 is square or circular.If use photoresistance as etch shield, then this etch shield 113 must just be removed before fin has an even surface step, with the high heat of avoiding fin to have an even surface in the step influence of photoresistance was produced bad effect to assembly.

Shown in Figure 11 C, before forming, gate dielectric 114 removes the etch shield 113 on the semiconductor fin 112A earlier, and can make semiconductor fin top surface 116 as semiconductor fin side 117, also form gate electrode, make this assembly become three gate MOS FET.If in the whole processing procedure, this etch shield 113 is left on the top of semiconductor fin 112A always, then last assembly will be the structure of bigrid MOSFET.

Ensuing processing procedure is the formation of gate dielectric 114.The method that gate dielectric 114 forms comprises thermal oxidation (thermal oxidation), chemical vapour deposition (CVD) (chemical vapor deposition) and sputter (sputtering) etc.As a rule, in the semiconductor fin side 117 with gate dielectric 114 thickness of semiconductor fin top surface 116 and inequality.According to the technology that gate dielectric 114 forms, gate dielectric 114 thickness of semiconductor fin top surface 116 are less than gate dielectric 114 thickness of semiconductor fin side 117.In one embodiment, the thickness of semiconductor fin top surface 116 gate dielectrics 114 is less than 20 .Gate dielectric 114 can use traditional material for example silicon dioxide or silicon oxynitride (siliconoxynitride), and its thickness range is from 3 to 100 , preferably less than 10 .Gate dielectric 114 also can use high-k (high-permittivity, high k) material (dielectric constant is higher than 5) for example: lanthana (lanthanum oxide), aluminium oxide (aluminum oxide), hafnium oxide (hafnium oxide), nitrogen hafnium oxide (hafnium oxynitride) or zirconia (zirconium oxide), thickness range is from 3 to 100 .

Then, deposit a gate material layers in gate dielectric 114 surfaces, the material of gate material layers can be polysilicon, polysilicon-germanium, refractory metal (for example molybdenum, tungsten), compound (for example titanium nitride) or other electric conducting material.Then, patterning grid material layer, to form a gate electrode 115 cross-over connection in the semiconductor fin side 117 with top surface 116.In preferred embodiment, the material of gate material layers is a polysilicon, and the material of gate dielectric 114 is a silicon oxynitride.Can use the electricity slurry gas of chloride and bromine to carry out electric paste etching, and stop at gate dielectric 114, between gate material layers and the transistor with gate dielectric 114 as insulation.Electric paste etching can reach high etching selection rate, and high etching selection rate is considerable for having high semiconductor fin 112A with the unusual MOSFET structure of the gate dielectric 114 of accurate dimension.

Remove the gate dielectric 114 that is not covered by gate electrode again, so far, the schematic perspective view of formed structure (not expression of clearance wall and source electrode, drain electrode) is shown in Figure 11 E.Through ion implant, electricity slurry impregnation ion implant (plasma immersion ion implantation, PIII) or other existing mode form lightly doped region (lightly-doped drain, LDD).Form clearance wall in existing mode in gate electrode sidewalls again, for example deposit the spacer material layer earlier, selective etch this gap wall material layer then, the material of spacer material layer can be dielectric material, for example silicon nitride or silicon dioxide, in preferred embodiment, the material of spacer material layer is the composite bed of silicon nitride and silicon dioxide.

Form source electrode and drain by ion implantation, the implantation of electricity slurry impregnation ion, gas or solid source diffusion or other traditional approach in semiconductor fin 112A.Any because of ion implant the lattice damage cause can in this moment again through a heating steps repair-deficiency.Grid, source electrode and drain electrode can form a conductor layer in its surface again, reducing resistance, the material of conductor layer can be metal silicide (for example titanium silicide, cobalt silicide, nickle silicide), metal nitride (for example titanium nitride, nitrogenize thallium), metal (for example tungsten, copper) or heavily-doped semiconductor (n for example ⁺Heavily doped silicon).In preferred embodiment, the material of conductor layer is a nickle silicide, and nickle silicide can (self-aligned silicide, salicide) processing procedure forms by the self-aligned metal silicide.In source electrode and drain region, can be in the semiconductor fin side 117 form conductor layers with top surface 116.Then, use prior art to form contact at source electrode, drain electrode and area of grid.It is considerable reaching low-down resistance in the nano-scale assembly.So far, then finish the making of three gate MOS FET, shown in Figure 11 D.

The processing flow of the processing flow of Ω-FET and three gate MOS FET is similar, and is before identical to the step that semiconductor fin 112A forms, i.e. step shown in Figure 11 C.Then the step of Figure 11 C forms a undercutting 121 with an etch process on insulating barrier 111A, and following erosion amount is R, and horizontal erosion amount is E, shown in Figure 12 A.This etch process is a wet etching processing procedure, use dilute hydrofluoric acid (water: the amount of dense hydrofluoric acid is about 25: 1) under 25 ℃ Celsius, to carry out wet etching 30～600 seconds, reaching the following erosion amount R of about 50～1000 , and horizontal erosion amount E simultaneously is between 20～500 .After undercutting 121 forms,, form steps such as gate dielectric 114A, formation gate electrode 115A in regular turn as the processing flow of above-mentioned three gate MOS FET.

Though the utility model discloses as above with a preferred embodiment, but be not in order to limit the utility model, any those skilled in the art, in not breaking away from spirit and scope of the present utility model, the equivalent structure transformation of being made all is included in the claim of the present utility model.

Claims

1. a CMOS transistor reverser that uses multi-gated transistor is characterized in that, this CMOS transistor reverser comprises at least:

At least one first multi-gated transistor, this first multi-gated transistor comprise one first source electrode and are connected to a power supply unit, and one first drain electrode is connected to an output, and a first grid electrode;

At least one second multi-gated transistor, this second multi-gated transistor comprise one second source electrode and are connected to an earth terminal, and one second drain electrode is connected to this output, and a second grid electrode; And

One input is connected to this first grid electrode and this second grid electrode.

2. CMOS transistor reverser as claimed in claim 1 is characterized in that, this first multi-gated transistor and this second multi-gated transistor are tri-gate transistor.

3. CMOS transistor reverser as claimed in claim 1 is characterized in that, this first multi-gated transistor and this second multi-gated transistor are the AOMIGE field-effect transistor.

4. CMOS transistor reverser as claimed in claim 1 is characterized in that, this first multi-gated transistor or this second multi-gated transistor comprise at least:

The semiconductor fin is positioned at base material top, and this layers on substrates includes an insulating barrier,

One gate dielectric is positioned at this semiconductor fin surface;

One gate electrode is positioned at this gate dielectric laminar surface; And

An one source pole and a drain electrode are located in these gate electrode both sides respectively, and are arranged in this semiconductor fin.

5. CMOS transistor reverser as claimed in claim 4 is characterized in that, the material of this semiconductor fin is a silicon.

6. CMOS transistor reverser as claimed in claim 4 is characterized in that, the material of this semiconductor fin is silicon-germanium.

7. CMOS transistor reverser as claimed in claim 4 is characterized in that the width of this semiconductor fin is uneven.

8. CMOS transistor reverser as claimed in claim 4 is characterized in that, the width of this semiconductor fin of the width of this semiconductor fin of this first multi-gated transistor and this second multi-gated transistor is inequality.

9. CMOS transistor reverser as claimed in claim 4 is characterized in that, this first multi-gated transistor is formed on this identical semiconductor fin with this second multi-gated transistor.

10. CMOS transistor reverser as claimed in claim 4 is characterized in that, this first multi-gated transistor is formed on this different semiconductor fin with this second multi-gated transistor.

11. CMOS transistor reverser as claimed in claim 4 is characterized in that, the material of this insulating barrier is a dielectric material.

12. CMOS transistor reverser as claimed in claim 4 is characterized in that, the material of this insulating barrier is a silica.

13. CMOS transistor reverser as claimed in claim 4 is characterized in that, the thickness of this insulating barrier is between 20 to 1000 .

14. CMOS transistor reverser as claimed in claim 4 is characterized in that, the material of this gate dielectric is a silicon dioxide.

15. CMOS transistor reverser as claimed in claim 4 is characterized in that, the material of this gate dielectric is a silicon oxynitride.

16. CMOS transistor reverser as claimed in claim 4 is characterized in that the material of this gate dielectric is a high dielectric constant material, is selected from one of lanthana, aluminium oxide, hafnium oxide, nitrogen hafnium oxide and zirconia.

17. CMOS transistor reverser as claimed in claim 4 is characterized in that, the material of this gate dielectric is that dielectric constant is higher than 5 high dielectric constant material.

18. CMOS transistor reverser as claimed in claim 4 is characterized in that, the thickness of this gate dielectric is between 3 to 100 .

19. CMOS transistor reverser as claimed in claim 4 is characterized in that, it is different with the thickness of top surface that this gate dielectric is positioned at this semiconductor fin side.

20. CMOS transistor reverser as claimed in claim 4 is characterized in that, the thickness that this gate dielectric is positioned at this semiconductor fin top surface is thin than the thickness that is positioned at this semiconductor fin side.

21. CMOS transistor reverser as claimed in claim 4 is characterized in that, this gate dielectric is positioned at the thickness of this semiconductor fin top surface less than 20 .

22. CMOS transistor reverser as claimed in claim 4 is characterized in that, the material of this gate electrode is a polysilicon.

23. CMOS transistor reverser as claimed in claim 4 is characterized in that, the material of this gate electrode is polysilicon-germanium.

24. CMOS transistor reverser as claimed in claim 4 is characterized in that, the material of this gate electrode is a metal.

25. CMOS transistor reverser as claimed in claim 4 is characterized in that, this source electrode and this drain surface have a conductor layer, and the material of this conductor layer is selected from one of metal, metal silicide and metal nitride.

26. CMOS transistor reverser as claimed in claim 25 is characterized in that, contacting between this conductor layer and this source electrode and this drain electrode is to be positioned at this semiconductor fin side and top surface.