CN2720640Y - Strain slotted transistor structure with crystal lattice asynmmetry area - Google Patents
Strain slotted transistor structure with crystal lattice asynmmetry area Download PDFInfo
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- CN2720640Y CN2720640Y CN 200420049930 CN200420049930U CN2720640Y CN 2720640 Y CN2720640 Y CN 2720640Y CN 200420049930 CN200420049930 CN 200420049930 CN 200420049930 U CN200420049930 U CN 200420049930U CN 2720640 Y CN2720640 Y CN 2720640Y
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Abstract
The utility model provides a strain slotted transistor structure with crystal lattice dissymmetrical area, comprising a base with a strain channel region. The base comprises the first semi-conducting material of the first natural lattice constant. The strain channel region is covered with a grid dielectric layer. The grid dielectric layer is covered with a grid electric pole. A source electrode region and a drain region are arranged in the position which is adjacent to the strain channel region. The source electrode region and/or the drain region comprises a crystal lattice dissymmetrical area composed of the second semi-conducting material of the second natural lattice constant which is different from the first natural lattice constant.
Description
Technical field
The utility model relates to a kind of semiconductor subassembly with the unbecoming district of lattice, especially in regard to a kind of strained channel transistor structure.
Background technology
In recent ten years, along with metal-oxide half field effect transistor (metal-oxide-semiconductorfield effect transistor, MOSFET) size dwindles, comprise dwindling of grid length and thickness of grid oxide layer, made that continuing to improve speed and efficiency, density and per unit IC (integrated circuits) cost becomes possibility.
In order further to promote transistorized usefulness, can utilize strain (strain) to improve carrier transport factor at transistor channel, reaching the purpose that promotes performance of transistors, and then the assembly ratio is dwindled.Below introduce several existing methods that make channel region strain:
In a common methods, as in December, 1992 in the J.Welser et al. that San Francisco, California InternationalElectron Devices Meeting is published as described in " the NMOS and PMOS transistors fabricated in strainedsilicon/relaxed silicon-germanium structures " of 1000-1002 page or leaf, one loose SiGe (SiGe) resilient coating 110 is used for doing the channel region 126 of below, shown in Figure 1A; In Figure 1B and Fig. 1 C, utilize the simple block of a different lattice constant to be illustrated in the relaxed silicon germanium layer 114 of 110 li of resilient coatings and the cross section of strained silicon layer 130; In Figure 1B, the natural lattice constant of block 135 expression silicon, this lattice constant is littler than the natural lattice constant of block 115 SiGes; In Fig. 1 C, long when relaxed silicon germanium layer 114 (block 115) is gone up when a polycrystal silicon film (block 135) of heap of stone, the elementary cell 136 meeting horizontal expansions of silicon produce a two-dimentional tensile stress in the block 135, make this polycrystal silicon film of heap of stone become strained silicon layer 130, shown in Figure 1A.In Figure 1A, a crystal pipe range is in this two-dimentional tensile stress channel region 126 on this strain crystal silicon layer 130 of heap of stone, and this natural lattice constant is the lattice constant of semiconductor under atmospheric pressure at room for this reason.In this method, relaxed silicon germanium layer 114 is one to be positioned at the stressed zone (stressor) under the channel region 126, and this stressed zone makes channel region 126 produce strains, is subjected to the silicon raceway groove of a two-dimentional tensile stress that electronics and hole mobility in the whole transistor are had very big lifting.In said method, crystal silicon layer 130 of heap of stone just strain before transistor forms, therefore, the high temperature process of the CMOS issuable strain of institute loose (strain relaxation) afterwards need be paid special attention to; In addition, because the thickness of silicon germanium buffer 110 is to grow up with the grade of micron, so this method is very expensive; In addition, have many (dislocation) out of frame phenomenon in the relaxed silicon germanium layer 114, some also can hyperplasia in strained silicon layer 130, produce high defect concentration, make performance of transistors be subjected to negative effect.
In other method, channel region is just strain after transistor forms.In the method, a high stress films 220 is formed on the whole transistor arrangement 250, as shown in Figure 2; 220 pairs of channel regions of high stress films 206 as the stressed zone produce significant impact, and it changes channel region 206 interstitial voids (lattice spacing) and produces strain; In this example, the stressed zone is positioned at whole transistor arrangement 250 tops, detailed description please refer to A.Shimizu et al., " Local mechanicalstress control (LMC): a new technique fo CMOS performanceenhancement ", pp.433-436 of the Digest of Technical Papers of the2001 Interna tional Electron Device Meeting; The strain that high stress films 220 is produced is considered to arrive the parallel one dimension direction of drain electrode with source electrode in essence, yet, lowered hole mobility at source electrode to the one dimension tensile stress-strain that drains, and the one dimension compression stress has lowered electron mobility; The ion of germanium is implanted and is used to optionally alleviate this strain, and electric hole or electron mobility can not reduced, but since N and p channel transistor very close to, so this implantation is had any problem.
Summary of the invention
Main purpose of the present utility model is for providing a kind of transistor arrangement with strained channel region.
Another purpose of the present utility model just provides a kind of strained channel transistor structure, and this structure is the unbecoming district of lattice near the part source area and the drain region of strained channel region, and the unbecoming district of this lattice is influenced by channel region.
For reaching above-mentioned purpose, the utility model provides a distortion channel transistor electrode structure, comprises a strained channel region, a gate dielectric, a gate electrode and one source pole district and drain region; Relative proximity place that first semi-conducting material, this gate dielectric that this substrate comprises one first natural lattice constant is positioned on the strained channel region, gate electrode is positioned on the gate dielectric, source area and drain region are positioned at strained channel region, and source area and/or drain region comprise the unbecoming district of a lattice, this district comprises second semi-conducting material of one second natural lattice constant, and this second natural lattice constant and the first natural lattice constant are different.
Description of drawings
Figure 1A to Fig. 1 C is a series of common strain silicon transistor profiles, and this transistor has a relaxed silicon germanium layer as the stressed zone, makes crystal silicon layer of heap of stone top produce strain;
Fig. 2 is another common strain silicon transistor profile, utilizes the stressed zone of a high stress films to make channel strain in order to explanation;
Fig. 3 A and Fig. 3 B are the profile of the strained channel transistor structure of a series of use the utility model embodiment one;
Fig. 4 A to Fig. 4 D is the profile of the strained channel transistor structure of a series of use the utility model embodiment two;
Fig. 5 is the detail flowchart of the utility model strained channel transistor structure embodiment three;
Fig. 6 A to Fig. 6 F is the fabrication steps profile of the strained channel transistor structure of a series of use the utility model embodiment three;
Fig. 7 is the detail flowchart of the utility model strained channel transistor structure embodiment four;
Fig. 8 A to Fig. 8 D is the fabrication steps profile of the strained channel transistor structure of a series of use the utility model embodiment four;
Fig. 9 is the detail flowchart of the utility model distortion trench transistor structure embodiment five;
Figure 10 A to Figure 10 G is the fabrication steps profile of the strained channel transistor structure of a series of use the utility model embodiment five;
Figure 11 A to Figure 11 D is the fabrication steps profile of the strained channel transistor structure of a series of use the utility model embodiment six.
Symbol description:
100,200,300a, 300b, 400,500,600,700,800: substrate
110: the germanium silicide resilient coating
112: germanium silicide resilient coating below
114: germanium silicide resilient coating top
115: the germanium silicide block
122,202: drain electrode
124,204: source electrode
126,206,506,606,706,806: channel region
130: strained silicon layer
135: the silicon area piece
136: the elementary cell of silicon
142,214,314a, 314b, 414,514,614,714,814: gate electrode
T: tension force
212,312a, 312b, 412,512,612,712,812: gate dielectric
216,316a, 316b, 416,516,616,715,716,816: clearance wall
220: high stress films
250: transistor arrangement
3a, 3b, 4a, 4b, 4c, 4d, 5,6,7,8: strained channel transistor structure
301a, 301b, 401,501,601,701,801: drain electrode extension area
302a, 302b, 402,502,602,702,802: dark drain region
303a, 303b, 403,503,603,703,803: source electrode extension area
304a, 304b, 404,504,604,704,804: deep source region
305a, 305b, 405a, 405b, 405c, 405d, 505,605,705,805: the unbecoming district of lattice
306a, 306b, 406a, 406b, 406c, 406d, 506 ', 606 ', 706 ', 806 ': strained channel region
307a, 307b, 407,507,607,707,807: drain region
308a, 308b, 408,508,608,708,808: source area
C
1: source electrode is to the compression stress of drain directions
T
1: the tensile stress of vertical direction
C
2: the compression stress of vertical direction
T
2: source electrode is to the tensile stress of drain directions
420,520,620,720,820: conducting shell
509,609,709: the etchback place
D: the degree of depth at etchback place
622,722: the silicon cap rock
830: implanting ions
Embodiment
For above-mentioned and other purpose of the present utility model, feature and advantage can be become apparent, cited below particularlyly go out preferred embodiment, and cooperate appended graphicly, be described in detail below:
Embodiment one:
In embodiment one of the present utility model, discussion is applied to two kinds of stress patterns of strained channel region.
In Fig. 3 A, a strained channel transistor structure 3a profile is represented the utility model embodiment one: there is a strained channel region 306a on substrate 300a surface, and this substrate comprises the semiconductor material; Gate dielectric 312a is positioned on the strained channel region 306a, and the best thickness of this layer is about 3 to 100 dusts; Gate electrode 314a is positioned on the gate dielectric 312a; Clearance wall 316a is positioned at gate electrode 314a sidewall, and covers a part of substrate 300a surface; Drain region 307a comprises that drain electrode extension area 301a and dark drain region 302a, source area 308a comprise source electrode extension area 303a and deep source region 304a, and drain region and source area are positioned at relative proximity place of strained channel region 306a; The unbecoming district of lattice 305a comprises another kind of semi-conducting material, the natural lattice constant of this semi-conducting material and the natural lattice constant of substrate 300a are different, and be positioned at dark drain region 302a and deep source region 304a, therefore, strained channel region 306a can be by the strain of the unbecoming district with lattice of the strained channel region 306a of different lattice constants 305a institute.
In the utility model embodiment one, in strained channel transistor structure 3a, substrate 300a preferably comprises the silicon that the nature lattice constant is about 5.431 dusts, and the unbecoming district of lattice 305a preferably comprises the preferably alloy semiconductor material about between 5.431 to 5.657 dusts of a natural lattice constant, as sige alloy, this constant is relevant with the concentration of germanium in sige alloy, and greater than the natural lattice constant of substrate 300a; In the utility model embodiment one, the not ear of the germanium in the unbecoming district of lattice in sige alloy preferably is about 0.1 to 0.9 than (mole fraction), make the unbecoming district of lattice 305a become a stressed zone, in strained channel region 306a, produce the compression stress C of one source pole to drain directions
1Tensile stress T with a vertical direction
1, make distortion channel region 306a be in one source pole to the tensile stress of the compression stress of drain directions and vertical direction.When this strained channel transistor structure 3a was the P raceway groove, the hole mobility of strained channel region 306a significantly increased, and drive current (drivecurrent) is promoted.
In Fig. 3 B, 3b is the profile of the strained channel transistor structure of the utility model embodiment one.There is a strained channel region 306b on substrate 300b surface, and this substrate comprises the semiconductor material; Gate dielectric 312b is positioned on the strained channel region 306b, and this layer thickness preferably is about 3 to 100 dusts; Gate electrode 314b is positioned on the gate dielectric 312b; Clearance wall 316b is positioned at gate electrode 314b sidewall, covers a part of substrate 300b surface; Drain region 307b comprises drain electrode extension area 301b and comprises source electrode extension area 303b and deep source region 304b with dark drain region 302b, source area 308b, and this drain region and source area are positioned at relative proximity place of strained channel region 306b; The unbecoming district of lattice 305b is positioned at dark drain region and deep source region, this district comprises another kind of semi-conducting material, its natural lattice constant and substrate 300b's is different, and therefore, strained channel region 306b can be by the strain of the unbecoming district with lattice of the strained channel region 306b of different crystalline lattice coefficient 305b institute.
In the strained channel transistor structure 3b of the utility model embodiment one, substrate 300b preferably comprises the unbecoming district with lattice of silicon 305b, this district preferably comprises an alloy semiconductor material, and as a silicon carbon alloy, and the natural lattice constant of this semi-conducting material is littler than substrate 300b.In the utility model embodiment one, the not ear of the carbon in the unbecoming district of lattice in silicon-carbon alloy preferably is about 0.01 to 0.04 than (mole fraction), make the unbecoming district of lattice 305b become a stressed zone, in distortion channel region 306b, produce the tensile stress C of one source pole to drain directions
2Compression stress T with a vertical direction
2, make distortion channel region 306b be in one source pole to the compression stress of the tensile stress of drain directions and vertical direction.When this distortion trench transistor structure 3b was the N raceway groove, the electron mobility of distortion channel region 306b significantly increased, and drive current is promoted, moreover, the unbecoming district of lattice may comprise germanium, becomes a silicon Germanium carbon alloy, and wherein the not ear of carbon is than the germanium that is greater than ten times.
In addition, in the strained channel region 306b of the strained channel region 306a of Fig. 3 A and Fig. 3 B, its compression strain and tensile strain are about 0.1% to 4%, preferably are about 1% to 4%; The thickness of the unbecoming district of the lattice 305b of the lattice of Fig. 3 A unbecoming district 305a and Fig. 3 B is about 10 to 1000 dusts; In the strained channel region 306b of the strained channel region 306a of Fig. 3 A and Fig. 3 B, its compression strain and tensile strain are lattice constant, thickness and the positions in drain region 307a and source area 308a of unbecoming district 306a with lattice and 306b, and the unbecoming district of lattice 306b is arranged in drain region 307b and source area 308b.
Embodiment two:
In the utility model embodiment two, discussion is positioned at the unbecoming district of lattice of drain region and source area diverse location.In Fig. 4 A to Fig. 4 D, there are strained channel transistor structure 4a to 4d, drain electrode extension area 401, dark drain region 402, drain region 407, source electrode extension area 403, deep source region 404, source area 408, the unbecoming district of lattice 405a/405b/405c/405d, strained channel region 406a/406b/406c/406d, gate dielectric 412, gate electrode 414 and clearance wall 416 in substrate 400 tops.If narration is then omitted with the utility model embodiment one identical person.
In Fig. 4 A, the unbecoming district of lattice 405a is positioned near drain region 407 and source area 408 surfaces, does not extend to drain electrode extension area 401 and source electrode extension area 403; In Fig. 4 B, the unbecoming district of lattice 405b protrudes drain region 407 and source area 408 surfaces, forms the drain region 407b of a projection and the source area 408b of projection; In Fig. 4 C, the unbecoming district of lattice 405c is positioned near drain region 407 and source area 408 surfaces, and further extends to drain electrode extension area 401 and source electrode extension area 403; In Fig. 4 D, the unbecoming district of lattice 405d is positioned at more depths of drain region 407 and source area 408 surfaces, and more extends to strained channel region 406d, drain electrode extension area 401 and source electrode extension area 403 belows.In addition, be positioned at the drain region with/or the position in the unbecoming district of lattice of source area conform to the utility model embodiment one, be not to mean to this restriction, have the knack of this skill person, can optionally further adjust the position in the unbecoming district of lattice according to the utility model.
In Fig. 4 A to Fig. 4 D, one conducting shell 420, as silicon, metal, metal silicide or aforesaid combination, optionally form in the drain region of strained channel transistor structure 4a, 4c and 4d and protrusion drain region and the protrusion source area surface of source area and strained channel transistor structure 4b.
Among this external Fig. 4 C,, electronics or hole mobility among the strained-channel structure 4c have been improved because 405c more close strained channel region 406c in the unbecoming district of lattice makes the unbecoming district of lattice 405c apply more strains in strained channel region 406c.
Embodiment three:
In the utility model embodiment three, will the manufacture method of a strained channel transistor structure be described, Fig. 5 is the flow chart of embodiment for this reason, and the description meeting of present embodiment is afterwards carried out according to the order of Fig. 5.
In Fig. 6 A, the semiconductor substrate is provided as a silicon base 500, and silicon base 500 comprises a multiple isolated area (not being shown on the figure) that forms in advance, and the multiplex assembly district (not being shown on the figure) of predefined.For example, this isolated area may be shallow trench isolation region (shallow trenchisolation).Fig. 6 A to Fig. 6 F provides the profile in a series of single components district, makes to describe to be more prone to.Silicon base 500 comprises a channel region 506 in an active region surface.When the strained channel transistor structure among Fig. 6 E 5 was the p channel transistor structure, silicon base 500 was the N type and mixes; If strained channel transistor structure 5 is the N trench transistor structure, silicon base 500 is the P type and mixes.
In Fig. 6 B, one gate dielectric 512 is formed on the channel region 506, then a gate electrode 514 is formed on this gate dielectric 512, and gate dielectric is that via nitride facture, chemical vapour deposition technique, physical vaporous deposition such as sputter or other known technology are formed again by thermal oxidation method, thermal oxidation method; Gate dielectric 512 can be silicon dioxide, silicon oxynitride (siliconoxynitride) or foregoing, and its thickness preferably is about 10 dusts or still less about between 3 to 100 dusts; Gate dielectric 512 may be a high-k (high-k) material, as aluminium oxide (Al2O3), hafnium oxide (HfO2), zirconia (ZrO2), nitrogen hafnium oxide (HfON), hafnium silicate (HfSiO4), zirconium silicate (ZrSiO4), lanthana (La2O3) or aforesaid combination, the thickness of this gate dielectric is equivalent to the oxide of about 3 dust to 100 dusts.Gate electrode 514 is polysilicon, polycrystalline silicon germanium, refractory metal such as molybdenum or tungsten, compound such as titanium nitride, aforementioned compositions or other conductive material; Implantation is used to change the work function of gate electrode 514, is considered to the implantation of kind of work function; Gate electrode 514 is to borrow deposition gate electrode material (not being shown on the figure) in substrate 500, deposit a grid cover (gate mask) (not being shown on the figure) again on gate electrode material, then define gate electrode 514, and this gate electrode material of etching forms gate electrode 514 and grid cover is removed by grid cover; Electrically, gate electrode 514 separates with channel region 506 usefulness gate dielectrics 512; In the utility model embodiment three, gate dielectric 512 is preferably silicon oxynitride, gate electrode 514 is preferably polysilicon, then can get high etching selectivity with chlorine and the etching of bromine chemistry method.
In Fig. 6 C, active region surface in substrate 500, one drain electrode extension area 501 is formed at channel region 506 relative proximities place with source electrode extension area 503, and clearance wall 516 is formed at gate electrode 514 sidewalls, this gap wall covers a part of drain electrode extension area 501 and source electrode extension area 503, and this extension area 501 that drains is to form by ion implantation, electricity slurry immersion ion implantation (PIII) or other known technology with source electrode extension area 503; The formation of clearance wall 516, preferably borrow deposition one spacer material layer (not being shown on the figure) as silicon nitride or silica and optionally etching this gap wall material layer form; In the utility model embodiment three, spacer material is a silicon nitride.
In Fig. 6 D, on the active region surface of part or all substrate 500 that is not covered by gate dielectric 512 and clearance wall 516, by chlorine and bromine chemistry method electric paste etching etchback, make to form the etchback place 509 that a degree of depth is at least d, this depth d is about 50 dust to 1000 dusts.For the of heap of stone brilliant processing procedure after, can utilize a nonessential tempering step to promote the mobility of silicon, repairing makes this etchback place 509 level and smooth because of etching causes the defective at etchback place 509, and the employed gas of this tempering step comprises nitrogen, argon, neon, helium, hydrogen, oxygen and above-mentioned composition.
In Fig. 6 E, etchback place 509 is filled the semiconductor material, as sige alloy or silicon carbon alloy, form the unbecoming district 505 of a lattice, then a dark drain region 502 is formed at the contiguous place of drain electrode extension area 501, the vicinity place that a deep source region 504 is formed at source electrode extension area 503, dark drain region 502 combines with drain electrode extension area 501 and forms drain region 507, deep source region 504 combines with source electrode extension area 503 and forms source area 508, and drain region 507 and source area 508 comprise the unbecoming district 505 of lattice; When the unbecoming district 505 of lattice formed, channel region 506 was formed a strained channel region 506 ' by strain; So far, the strained channel transistor structure 5 of the utility model embodiment three forms basically.The unbecoming district 505 of lattice borrows brilliant processing procedure of heap of stone to form, as chemical vapour deposition (CVD), high vacuum chemical vapour deposition or molecular beam epitaxy.When strained channel transistor structure 5 was the p channel transistor structure, the unbecoming district 505 of this lattice was a sige alloy, and wherein germanium is about 0.1 to 0.9 at the shared not ear ratio of this alloy; When strained channel transistor structure 5 is the N trench transistor structure, the unbecoming district 505 of this lattice is a silicon carbon alloy, and wherein carbon is about 0.0 1 to 0.04 at the shared not ear ratio of this alloy, and may further comprise germanium, form the carbon sige alloy, the not ear of this alloy germanium is than the carbon less than ten times.Utilize brilliant processing procedure of heap of stone, a silicon cap rock 522 can optionally form in the unbecoming district 505 of lattice, as chemical vapour deposition (CVD), high vacuum chemical vapour deposition or molecular beam epitaxy; In this brilliant processing procedure of heap of stone, may mix simultaneously or not mix with nonessential silicon cap rock 522 in the unbecoming district of lattice 505, when not mixing, they mix and can utilize Rapid Thermal tempering manufacturing process (rapid thermal annealing process) to come the admixture (dopants) of dopant activation afterwards.Dark drain region 502 borrows ion implantation, the implantation of electricity slurry immersion ion, gas phase or the diffusion of solid phase source or other known technology to form with deep source region 504.When forming the unbecoming district 505 of lattice, silicon cap rock 522, dark drain region 502 with deep source region 504, one tempering step can further make implants defective and noncrystallineization (amorphization) recovery, and the employed gas of this tempering step comprises nitrogen, argon, neon, helium, hydrogen, oxygen and above-mentioned composition.
In Fig. 6 F, a conducting shell 520 optionally is formed on unbecoming district 505 of lattice and drain region 507/ source area 508, and the drain region 507 and the resistance value of source area 508 are reduced; Conducting shell 520 is to utilize to aim at metal silicide (self-aligned silicide) voluntarily or other metal deposition processing procedure forms.Sheath (passivation layers) and assembly contact hole (contacts) form subsequently, and the assembly of the strained channel transistor structure 5 of the utility model embodiment three is finished.
Embodiment four:
In the utility model embodiment four, will the manufacture method of a strained channel transistor structure be described, this unbecoming district of transistorized lattice can not extend to drain electrode extension area and source electrode extension area.Fig. 7 is the flow chart of embodiment for this reason, and description meeting is afterwards carried out according to the order of Fig. 7.
In Fig. 8 A, the semiconductor substrate is provided as a silicon base 600, and silicon base 600 comprises a multiple isolated area (not being shown on the figure) that forms in advance and the multiplex assembly district (not being shown on the figure) of predefined, and for example this isolated area may be shallow trench isolation region.Fig. 8 A to Fig. 8 D provides the profile in a series of single components district, makes to describe to be more prone to.Silicon base 600 comprises a common transistor arrangement, this structure comprises a channel region 606, and is positioned at gate dielectric 612, on the channel region 606 and is positioned at the source area 608 and drain region 607 that gate electrode 614, on the gate dielectric 612 is positioned at channel region 606 relative proximities place in the active region surface of substrate 600, and one is positioned at the clearance wall 616 of gate electrode 614 sidewalls, and the active region surface of this gap wall cover part substrate 600.Drain region 607 comprises a drain electrode extension area 601 and a dark drain region 602, source area 608 comprise an one source pole extension area 603 and a deep source region 604.In Fig. 8 C, when strained channel transistor structure 6 was the p channel transistor structure, silicon base 600 was the N type and mixes; When strained channel transistor structure 6 is the N trench transistor structure, then mix for the P type.
In Fig. 8 B, active region surface in part or all substrate 600 that is not covered by gate dielectric 612 and clearance wall 616, by chlorine and bromine chemistry method electric paste etching etchback, make to form the etchback place 609 that a degree of depth is at least d, this depth d is about 50 dust to 1000 dusts.For the of heap of stone brilliant processing procedure after, can utilize a nonessential tempering step to promote the mobility of silicon, repairing makes this etchback place 609 level and smooth because of etching causes the defective at etchback place 609, and the employed gas of this tempering step comprises nitrogen, argon, neon, helium, hydrogen, oxygen and above-mentioned composition.
In Fig. 8 C, etchback place 609 is filled the semiconductor material, as sige alloy or silicon carbon alloy, forms the unbecoming district 605 of a lattice; Drain region 607 and source area 608 comprise the unbecoming district 605 of lattice; When the unbecoming district 605 of lattice formed, channel region 606 was formed a strained channel region 606 ' by strain; So far, the strained channel transistor structure 6 of the utility model embodiment four forms basically.Drain region 607 and source area 608 surfaces can be protruded in the unbecoming district 605 of lattice, form the drain region of a projection and the source area of projection; The unbecoming district 605 of lattice borrows brilliant processing procedure of heap of stone to form, as chemical vapour deposition (CVD), high vacuum chemical vapour deposition or molecular beam epitaxy.When strained channel transistor structure 6 was the p channel transistor structure, the unbecoming district 605 of this lattice was a sige alloy, and wherein germanium is about 0.1 to 0.9 at the shared not ear ratio of this alloy; When strained channel transistor structure 6 is the N trench transistor structure, the unbecoming district 605 of this lattice is a silicon carbon alloy, and wherein carbon is about 0.01 to 0.04 at the shared not ear ratio of this alloy, and may further comprise germanium, form the carbon sige alloy, the not ear of this alloy germanium is than the carbon less than ten times.Utilize brilliant processing procedure of heap of stone, as chemical vapour deposition (CVD), high vacuum chemical vapour deposition or molecular beam epitaxy, a silicon cap rock 622 can optionally form in the unbecoming district 605 of lattice.The unbecoming district 605 of lattice and nonessential silicon cap rock 622 doping simultaneously in this brilliant processing procedure of heap of stone.
In Fig. 8 D, one conducting shell 620 optionally is formed on unbecoming district 605 of lattice and drain region 607/ source area 608, the drain region 607 and the resistance value of source area 608 are reduced, and conducting shell 620 is to utilize to aim at metal silicide voluntarily or other metal deposition processing procedure forms.Sheath and assembly contact hole form subsequently, and the assembly of the strained channel transistor structure 6 of the utility model embodiment four is finished.
Embodiment five:
In the utility model embodiment five, will the manufacture method of a strained channel transistor structure be described.This unbecoming district of transistorized lattice can extend to drain electrode extension area and source electrode extension area.Fig. 9 is the flow chart of embodiment for this reason, and description meeting is afterwards carried out according to the order of Fig. 9.
In Figure 10 A, the semiconductor substrate is provided as a silicon base 700, silicon base 700 comprises a multiple isolated area (not being shown on the figure) that forms in advance and the multiplex assembly district (not being shown on the figure) of predefined, and for example this isolated area may be shallow trench isolation region.Figure 10 A to Figure 10 G provides the profile in a series of single components district, makes to describe to be more prone to.Silicon base 700 comprises one in the channel region 706 on active region surface.Among Figure 10 D, when strained channel transistor structure 7 was the p channel transistor structure, silicon base 700 was the N type and mixes; When strained channel transistor structure 7 is the N trench transistor structure, then mix for the P type.
In Figure 10 B, at first a gate dielectric 712 is formed on the channel region 706, and a gate electrode 714 is formed on the gate dielectric 712, and last clearance wall 715 is formed at gate electrode 714 sidewalls, and the active region surface of this gap wall cover part substrate 700.Gate dielectric 712 is that via nitride facture, chemical vapour deposition technique, physical vaporous deposition such as sputter or other known technology are formed again by thermal oxidation method, thermal oxidation method; Gate dielectric 712 can be silicon dioxide, silicon oxynitride or foregoing, and its thickness preferably is about 10 dusts or still less about between 3 to 100 dusts; Gate dielectric 712 may be a high-k material, and as aluminium oxide, hafnium oxide, zirconia, nitrogen hafnium oxide, hafnium silicate, zirconium silicate, lanthana or aforesaid combination, the thickness of this gate dielectric is equivalent to the oxide of about 3 dust to 100 dusts.Gate electrode 714 is polysilicon, polycrystalline silicon germanium, refractory metal such as molybdenum or tungsten, compound such as titanium nitride, aforementioned compositions or other conductive material; Implantation is used to change the work function of gate electrode 714, is considered to the implantation of kind of work function; Gate electrode 714 is to borrow deposition gate electrode material (not being shown on the figure) in substrate 700, deposit a grid cover (not being shown on the figure) again on gate electrode material, then define gate electrode 714, and this gate electrode material of etching forms gate electrode 714 and grid cover is removed by grid cover; Electrically, gate electrode 714 separates with channel region 706 usefulness gate dielectrics 712; In the utility model embodiment five, gate dielectric 712 is preferably silicon oxynitride, gate electrode 714 is polysilicon, then can get high etching selectivity with chlorine and the etching of bromine chemistry method.For the sidewall of brilliant step gate electrode 714 of heap of stone after protecting, clearance wall 715 is to utilize deposition and anisotropic etching technology to form.
In Figure 10 C, on the active region surface of part or all substrate 700 that is not covered by gate dielectric 712 and clearance wall 715, by chlorine and bromine chemistry method electric paste etching etchback, making and forming a degree of depth is the etchback place of d, and this depth d is about 50 dust to 1000 dusts.For the of heap of stone brilliant processing procedure after, can utilize a nonessential tempering step to promote the mobility of silicon, repairing makes this etchback place 709 level and smooth because of etching causes the defective at etchback place 709, and the employed gas of this tempering step comprises nitrogen, argon, neon, helium, hydrogen, oxygen and above-mentioned composition.
In Figure 10 D, etchback place 709 is filled the semiconductor material, as sige alloy or silicon carbon alloy, form the unbecoming district 705 of a lattice, a drain electrode extension area 701 forms in strained channel region 706 ' relative proximity place with source electrode extension area 703 afterwards, so far, the strained channel transistor structure 7 of the utility model embodiment five forms basically.The unbecoming district 705 of lattice borrows brilliant processing procedure of heap of stone to form, as chemical vapour deposition (CVD), high vacuum chemical vapour deposition or molecular beam epitaxy.When the unbecoming district 705 of lattice formed, channel region 706 was formed a strained channel region 706 ' by strain.When strained channel transistor structure 7 was the p channel transistor structure, the unbecoming district 705 of this lattice was a sige alloy, and wherein germanium is about 0.1 to 0.9 at the shared not ear ratio of this alloy; When strained channel transistor structure 7 is the N trench transistor structure, the unbecoming district 705 of this lattice is a silicon carbon alloy, and wherein carbon is about 0.01 to 0.04 at the shared not ear ratio of this alloy, and may further comprise germanium, form the carbon sige alloy, the not ear of this alloy germanium is than the carbon less than ten times.Utilize brilliant processing procedure of heap of stone, as chemical vapour deposition (CVD), high vacuum chemical vapour deposition or molecular beam epitaxy, a silicon cap rock 722 can optionally form in the unbecoming district 705 of lattice.When in brilliant processing procedure of heap of stone, does not mix with nonessential silicon cap rock 722 in the unbecoming district 705 of lattice, but the available Rapid Thermal tempering manufacturing process of doping afterwards activates admixture.Drain electrode extension area 701 and source electrode extension area 703 comprise unbecoming district 705 of lattice and nonessential silicon cap rock 722.
In Figure 10 E, a clearance wall 716 covers and is formed on the former clearance wall 715, and clearance wall 716 is to borrow deposition and selective etch one spacer material (not being shown on the figure) to form, and this gap wall material is silicon nitride or silicon dioxide; In the utility model embodiment five, clearance wall 716 is a silicon nitride.
In Figure 10 F, a dark drain region 702 is formed at the contiguous place of drain electrode extension area 701, and deep source region 704 is formed at the contiguous place of source electrode extension area 703.When the unbecoming district of lattice 705 effectively the time, dark drain region 702 can combine with drain electrode extension area 701, and not necessary cap rock 722 can form drain region 707 effectively the time; When the unbecoming district of lattice 705 effectively the time, deep source region 704 can combine with source electrode extension area 703, and not necessary cap rock 722 can form source area 708 effectively the time.Dark drain region 702 borrows ion implantation, the implantation of electricity slurry immersion ion, gas phase or the diffusion of solid phase source or other known technology to form with deep source region 704.
In Figure 10 G, a conducting shell 720 optionally is formed on drain region 707 and the source area 708, and the drain region 707 and the resistance value of source area 708 are reduced; Conducting shell 720 is to utilize to aim at metal silicide voluntarily or other metal deposition processing procedure forms.Sheath and assembly contact hole form subsequently, and the assembly of the strained channel transistor structure 7 of the utility model embodiment five is finished.
Embodiment six:
In the utility model embodiment six, utilize ion implantation manufacture process to form the manufacture method in the unbecoming district of lattice in the strained channel transistor structure with describing one.
In Figure 11 A, the semiconductor substrate is provided as a silicon base 800, silicon base 800 comprises a multiple isolated area (not being shown on the figure) that forms in advance and the multiplex assembly district (not being shown on the figure) of predefined, and for example this isolated area may be shallow trench isolation region.Figure 11 A to Figure 11 D provides the profile in a series of single components district, makes to describe to be more prone to.Silicon base 800 comprises a common transistor arrangement, and this transistor arrangement comprises a channel region 806, and this district is positioned at the active region surface of substrate 800; One gate dielectric 812 is positioned on the channel region 806, a gate electrode 814 is positioned on the gate dielectric 812, one source pole 808 is positioned at channel region 806 relative proximities place with drain electrode 807, and a clearance wall 816 is positioned at gate electrode 814 sidewalls, and the active region surface of this gap wall cover part substrate 800.Drain region 807 comprises a drain electrode extension area 801 and comprises one source pole extension area 803 and deep source region 804 with dark drain region 802, source area 808.In Figure 11 C, when strained channel transistor structure 8 was the p channel transistor structure, silicon base 700 was the N type and mixes; When strained channel transistor structure 8 is the N trench transistor structure, then mix for the P type.
In Figure 11 B, an ion implantation manufacture process is used for ion 830 is implanted in drain region 807 and the source area 808, and this implanted ion is one or more atoms, and the radius of this atom is different with substrate 800; When this ion implantation manufacture process carries out, gate electrode 814 can be used as one with clearance wall 816 and implants cover (implantation mask), and whether the unbecoming district 805 of the visual lattice of the thickness of clearance wall 816 extends into drain electrode extension area 801 and source electrode extension area 803 adjusts.
In Figure 11 C, tempering is done in substrate 800, make the unbecoming district of lattice be formed at drain region 807 and source area 808, so drain region 807 and source area 808 comprise the unbecoming district of lattice.When the unbecoming district 805 of lattice formed, channel region 806 was formed a strained channel region 806 ' by strain.So far, the strained channel transistor structure 8 of the utility model embodiment six forms basically.When strained channel transistor structure 8 was the p channel transistor structure, the unbecoming district 805 of this lattice was a sige alloy, and wherein germanium is about 0.1 to 0.9 at the shared not ear ratio of this alloy; When strained channel transistor structure 8 is the N trench transistor structure, the unbecoming district 805 of this lattice is a silicon carbon alloy, and wherein carbon is about 0.01 to 0.04 at the shared not ear ratio of this alloy, and may further comprise germanium, form the carbon sige alloy, the not ear of this alloy germanium is than the carbon less than ten times.
In Figure 11 D, a conducting shell 820 optionally is formed on drain region 807 and the source area 808, and the drain region 807 and the resistance value of source area 808 are reduced; Conducting shell 820 is to utilize to aim at metal silicide voluntarily or other metal deposition processing procedure forms.Sheath and assembly contact hole form subsequently, and the assembly of the strained channel transistor structure 8 of the utility model embodiment six is finished.
Claims (20)
1. strained channel transistor structure with the unbecoming district of lattice is characterized in that described strained channel transistor structure comprises:
One strained channel region comprises first semi-conducting material with first natural lattice constant;
One covers the gate dielectric layer of this distortion channel region;
One covers the gate electrode of this gate dielectric layer; And
The one source pole district is positioned at the relative adjacent of this distortion channel region with the drain region, this source electrode and drain electrode comprise the unbecoming district of a lattice, the unbecoming district of this lattice comprises second semi-conducting material with second natural lattice constant, and this second natural lattice constant and this first natural lattice constant are different.
2. the strained channel transistor structure with the unbecoming district of lattice according to claim 1 is characterized in that: the thickness in this unbecoming zone of lattice is 10 to 1000 dusts.
3. the strained channel transistor structure with the unbecoming district of lattice according to claim 1 is characterized in that: this first semi-conducting material comprises silicon.
4. the strained channel transistor structure with the unbecoming district of lattice according to claim 1 is characterized in that: this second semi-conducting material comprises silicon and germanium or silicon and carbon.
5. the strained channel transistor structure with the unbecoming district of lattice according to claim 4 is characterized in that: germanium shared not ear ratio in this second semi-conducting material is 0.1 to 0.9.
6. the strained channel transistor structure with the unbecoming district of lattice according to claim 4 is characterized in that: carbon shared not ear ratio in this second semi-conducting material is 0.01 to 0.04.
7. the strained channel transistor structure with the unbecoming district of lattice according to claim 4 is characterized in that: this second semi-conducting material still comprises germanium, and in this second semiconductor, the not ear of germanium is than the carbon less than ten times.
8. the strained channel transistor structure with the unbecoming district of lattice according to claim 1 is characterized in that: this strained channel region is subjected to the compression stress effect of one source pole to the tensile stress and a vertical direction of drain directions.
9. the strained channel transistor structure with the unbecoming district of lattice according to claim 8 is characterized in that: this tensile stress be 0.1% to 4% and compression stress be 0.1% to 4%.
10. the strained channel transistor structure with the unbecoming district of lattice according to claim 1 is characterized in that: this strained channel region is subjected to the tensile stress effect of source electrode to the compression stress and the vertical direction of drain directions.
11. the strained channel transistor structure with the unbecoming district of lattice according to claim 10 is characterized in that: this compression stress be 0.1% to 4% and tensile stress be 0.1% to 4%.
12. the strained channel transistor structure with the unbecoming district of lattice according to claim 1 is characterized in that: still comprise a cover layer that is positioned at this unbecoming district of lattice.
13. the strained channel transistor structure with the unbecoming district of lattice according to claim 12 is characterized in that: this cover layer comprises this first semi-conducting material.
14. the strained channel transistor structure with the unbecoming district of lattice according to claim 1 is characterized in that: this source area comprises an one source pole extension area and a deep source region, and the drain region comprises a drain electrode extension area and a dark drain region.
15. the strained channel transistor structure with the unbecoming district of lattice according to claim 14 is characterized in that: the unbecoming zone of this lattice extends laterally to source electrode extension area and drain electrode extension area.
16. the strained channel transistor structure with the unbecoming district of lattice according to claim 1 is characterized in that: the unbecoming zone of this lattice further extends beyond this source electrode extension area and drain electrode extension area.
17. the strained channel transistor structure with the unbecoming district of lattice according to claim 1, it is characterized in that: the relative dielectric constant of this gate dielectric layer is greater than 5.
18. the strained channel transistor structure with the unbecoming district of lattice according to claim 1 is characterized in that: the thickness of this gate dielectric layer is 3 to 100 dusts.
19. the strained channel transistor structure with the unbecoming district of lattice according to claim 1, it is characterized in that: this gate electrode comprises polysilicon or polycrystalline silicon germanium.
20. the strained channel transistor structure with the unbecoming district of lattice according to claim 1 is characterized in that: this source area and surface, drain region still comprise one deck conductive materials.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
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| CN 200420049930 CN2720640Y (en) | 2004-04-26 | 2004-04-26 | Strain slotted transistor structure with crystal lattice asynmmetry area |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200420049930 CN2720640Y (en) | 2004-04-26 | 2004-04-26 | Strain slotted transistor structure with crystal lattice asynmmetry area |
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| CN2720640Y true CN2720640Y (en) | 2005-08-24 |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102412259A (en) * | 2010-09-21 | 2012-04-11 | 英飞凌科技奥地利有限公司 | Semiconductor body with strained region |
| CN102931222A (en) * | 2011-08-08 | 2013-02-13 | 中国科学院微电子研究所 | Semiconductor device and manufacturing method thereof |
| CN103426905A (en) * | 2012-05-16 | 2013-12-04 | 英飞凌科技奥地利有限公司 | Semiconductor structure, semiconductor device having a semiconductor structure, and method for manufacturing a semiconductor structure |
| WO2013177855A1 (en) * | 2012-05-30 | 2013-12-05 | Tsinghua University | Semiconductor structure and method for forming the same |
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2004
- 2004-04-26 CN CN 200420049930 patent/CN2720640Y/en not_active Expired - Lifetime
Cited By (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102412259A (en) * | 2010-09-21 | 2012-04-11 | 英飞凌科技奥地利有限公司 | Semiconductor body with strained region |
| US8889531B2 (en) | 2010-09-21 | 2014-11-18 | Infineon Technologies Austria Ag | Semiconductor device having two monocrystalline semiconductor regions with a different lattice constant and a strained semiconductor region between |
| CN102412259B (en) * | 2010-09-21 | 2015-11-18 | 英飞凌科技奥地利有限公司 | There is the semiconductor body by stress area |
| US9245943B2 (en) | 2010-09-21 | 2016-01-26 | Infineon Technologies Austria Ag | Semiconductor body with strained monocrystalline region |
| CN102931222A (en) * | 2011-08-08 | 2013-02-13 | 中国科学院微电子研究所 | Semiconductor device and manufacturing method thereof |
| WO2013020255A1 (en) * | 2011-08-08 | 2013-02-14 | 中国科学院微电子研究所 | Semiconductor device and manufacturing method thereof |
| US8754482B2 (en) | 2011-08-08 | 2014-06-17 | Institute of Microelectronics, Chinese Academy of Sciences | Semiconductor device and manufacturing method thereof |
| CN102931222B (en) * | 2011-08-08 | 2015-05-20 | 中国科学院微电子研究所 | Semiconductor device and manufacturing method thereof |
| CN103426905A (en) * | 2012-05-16 | 2013-12-04 | 英飞凌科技奥地利有限公司 | Semiconductor structure, semiconductor device having a semiconductor structure, and method for manufacturing a semiconductor structure |
| CN103426905B (en) * | 2012-05-16 | 2016-08-31 | 英飞凌科技奥地利有限公司 | Semiconductor structure, there is its semiconductor device and for the method manufacturing it |
| WO2013177855A1 (en) * | 2012-05-30 | 2013-12-05 | Tsinghua University | Semiconductor structure and method for forming the same |
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