CN2715237Y - CDMA signaling analyzer based on parallel port - Google Patents
CDMA signaling analyzer based on parallel port Download PDFInfo
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- CN2715237Y CN2715237Y CNU2004200603759U CN200420060375U CN2715237Y CN 2715237 Y CN2715237 Y CN 2715237Y CN U2004200603759 U CNU2004200603759 U CN U2004200603759U CN 200420060375 U CN200420060375 U CN 200420060375U CN 2715237 Y CN2715237 Y CN 2715237Y
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Abstract
The utility model relates to a CDMA (Code Division Multiple Access) signaling analyzer based on a parallel port, which adopts a modular construction, comprising a notebook computer and the mainframe of a signaling analyzer. By the receiving and transmitting module of signaling data, communication is done between the notebook computer and the mainframe of the signaling analyzer adopting an EPP (Enhanced Parallel Port)mode. The data and addresses are all sent and received by the data port of a computer parallel port. A communication buffer is realized by adopting a double-port RAM (Random Access Memory), and massage data are sent at the mode of the connecting of the parallel port, which realizes quick-speed and real-time data communication. The signaling analyzer of the structure has fast data transmission rate and can completely realize real-time signaling monitoring and analysis. The utility model has the advantages of easy use, small volume, light weight, big displayed information capacity, etc.; the CDMA signaling analyzer based on a parallel port is convenient to carry; the software of the utility model is conveniently upgraded.
Description
Technical field
The utility model relates to the communication system measuring instrument, relates in particular to the data transmit-receive mode of CDMA signaling test analyser.
Background technology
The signalling analysis instrument majority that is used for telecommunications network at present is the industrial computer formula, and the split type instrument of minority is also arranged.Adopt the Signaling Analyzer of industrial computer formula structure, monitoring software, decoding and displaying, hardware all is integrated in one, and it is fast to have speed, stable performance, the advantage of specialty, but cost an arm and a leg the software upgrading inconvenience.And split type Signaling Analyzer adopts microcomputer as signalling analysis and decoding display terminal, upgrade software easily, and price is also relatively cheap a lot.But split type Signaling Analyzer in the market generally adopts the communication port between string shape interface or pci interface conduct and the microcomputer, the speed of string shape interface is too low, signal collecting for multilink, its speed obviously is not enough, the speed of pci interface is very fast, but do not support plug and play, use very inconvenient.
Summary of the invention:
Technical problem to be solved in the utility model provides a kind of cost performance height, and software upgrading is convenient, and data transfer rate is fast, and the data presented capacity is big, is convenient for carrying, and supports the signaling system analyser of plug and play.
The technical scheme that its technical matters that solves the utility model adopts is: EPP (the Enhanced Parallel port that adopts parallel port of computer, strengthen parallel interface) pattern, DPRAM is provided (Dual port staticRAM, the dual-port static storer) data/address line of data/address wire compatibility, finish reception and the transmission of computing machine to signaling data, by a data transmit-receive module circuit based on parallel port, control read-write by the address control circuit that the code translator sum counter is formed, can realize continuation address operation fast.The utility model adopts the brick pattern instrument structure of international popular, constitute with Signaling Analyzer slave two parts by the Signaling Analyzer main frame, the Signaling Analyzer main frame is by the collection of line interface realization to original signaling data stream, deposit in the memory buffer, send to the Signaling Analyzer slave through signaling data transceiver module circuit, Control Software, signalling analysis software are installed on slave, are used for message data is carried out analyzing and processing, demonstration.Adopt the EPP pattern to communicate by CDMA signaling data transmission circuit module between Signaling Analyzer main frame and slave, data and address all are that the data port by parallel interface sends and receives.Communication buffer utilizes dual port RAM to realize, transmits message data with the parallel port ways of connecting, realizes real-time data communication fast.
CDMA signaling data transmission circuit modular circuit based on parallel port comprises DPRAM, the circuit driver module, 16 bit address generation modules, latch, code translator, octal bus treiver, computer parallel interface, in the time will reading and writing data among the DPRAM, earlier low eight address is delivered to the address location of 16 bit address generation modules by latch from the data port of computer parallel interface, in the control mouth, send a control word simultaneously and notify 16 bit address generation modules to receive low eight bit address, and then send the high eight-bit address to 16 bit address generation modules by code translator.Send the control word process code translator control address generation module of read write command by the control mouth and send via line driver module driving back, address, and read and write through the enable signal control DPRAM that code translator is sent to DPRAM.The signaling data of analysis to be tested transmits between DPRAM and data port by octal bus treiver then.The Signaling Analyzer slave receives the data that main frame is gathered by its parallel port, analyzes, handles, and the result is sent demonstration.
This Signaling Analyzer is by based on realizing rapid data transmission between the data transmit-receive circuit module of parallel port and the microcomputer parallel port, message transmission rate is fast, can reach 1Mbit/s, can satisfy the monitoring and the analysis of cdma mobile communication network real-time signaling message fully, support plug and play, the Signaling Analyzer of this structure is little except volume, in light weight, easy to carry, outside the advantages such as the information capacity that shows is big, another very big advantage is to have broken through the incorporate restriction of traditional communication instrument, realized separating of data acquisition and data analysis, and can enjoy the superiority of Windows multiple task operating system to the full, in the operational monitoring program, also can move other window application, and can upgrade rapidly along with notebook computer, promote performance.
Description of drawings:
The utility model is described in further detail below in conjunction with drawings and Examples.
Figure 1 shows that CDMA signaling system analyser basic structure schematic diagram
Figure 2 shows that signaling data transceiver module schematic block circuit diagram
Embodiment
As shown in Figure 1, this Signaling Analyzer comprises Signaling Analyzer host machine part and Signaling Analyzer slave part, sets up real-time data channel fast by the signaling data transceiver module employing that is integrated in the main frame based on the EPP pattern of parallel port between Signaling Analyzer main frame and slave.This Signaling Analyzer host machine part comprises parallel interface, memory buffer circuit, line interface circuit; The Signaling Analyzer slave can adopt microcomputer, preferably adopts notebook computer, and the signalling analysis testing software is installed thereon.Port R1a, the R1b of line interface, R2a, R2b etc. insert test link, line interface is sent into memory buffer after partly gathering the signaling data of test to be analyzed, send into notebook computer by the signaling data transceiver module that is connected with the parallel interface of notebook computer then, notebook computer partly provides the platform of man-machine I and centralized control and the operation of message analysis process software, the signaling data that receives is monitored analysis, analysis processing result is shown by display.Communication buffer utilizes dual port RAM to realize, uses dual port RAM can be set up a larger capacity between two modules buffer zone, and two modules all can be at any time read and write data to arbitrary storage unit of dual port RAM, do not need mutual wait.This signalling analysis tester can be upgraded to 8 links, can insert 8 links simultaneously and carry out test analysis.T is for keeping the signaling test port.
Be illustrated in figure 2 as the data transmit-receive module circuit block diagram, this data transmit-receive module adopts the EPP pattern of parallel port of computer, and the data/address line of DPRAM data/address wire compatibility is provided, and finishes collection and the transmission of computing machine to hardware data.The pin of parallel port of computer can be divided into three groups by function: data port, control mouth, state mouth.The EPP agreement provides four kinds of data manipulation cycles, that is: data write cycle, data read cycle, address write cycle time, address read cycle.Under the EPP pattern, the transmitting-receiving of data is finished by data port, and the operation of counterpart finishes with single-step instruction, has improved message transmission rate greatly.
This data transmit-receive module comprises memory buffer DPRAM, 16 bit address generation modules, circuit driver module, latch, code translator, octal bus treiver.It is the DPRAM of 2K byte that Data Buffer Memory has been selected capacity for use.Because its address wire is 11, so 8 position datawires of parallel port of computer must be sent the address at twice, 16 bit address generation modules in this circuit module, have been adopted, in the time will reading and writing data among the DPRAM, earlier low eight address is delivered to the address location of 16 bit address generation modules by latch from the data port of parallel interface, from the control mouth of parallel interface, send a control word simultaneously and receive low eight bit address, and then send the high eight-bit address to address generating module by code translator Notify Address generation module.Send the control word of read write command from the control mouth and send via line driver module driving back, address to DPRAM, and a control mouthful enable signal control DPRAM who sends through code translator reads and writes through code translator control address generation module.The signaling data of analysis to be tested transmits between DPRAM and data port by octal bus treiver then.When the data address of reading and writing is a consecutive hours, can send the address by the control mouth and control the address increase and decrease of preserving in the 16 bit address generation modules by code translator from the control word that increases or subtract certainly, need send the frequent address function of address when so just having avoided data of each read-write for twice, improve the read or write speed of parallel port greatly.
In this data transmit-receive module circuit, data and address all are that the data port by computer parallel interface sends and receives, eight bit address data multiplex buses of data port are connected to 16 bit address generation modules after by latch and are used to produce 16 bit address, simultaneously the multiply-connected bi-directional that is used for data to the bidirectional bus transceiver of data line.Because data port has only eight, need to send the address from data port at twice and could carry out addressing 16 bit address space, in order to reduce the number of times of sending the address, we have designed one 16 bit address generation module in the notebook data transceiver module, and the address can be latched in this address generating module, can be removed the address in the 16 bit address generation modules by a control mouthful control signal that produces, collect low eight bit address, collect the high eight-bit address, the address is from increasing, and operation such as subtracts certainly.So just can send and make the control port address from increasing or subtracting certainly by simple order, when the data of read-write continuation address, can reduce the address frequent send operation, improved the read or write speed of parallel port greatly.
This Signaling Analyzer adopts notebook computer as slave, can upgrade to software easily, need not change hardware configuration, only need in slave, to install different analysis software, same instrument can realize ISDN (ISDN(Integrated Service Digital Network)) (30B+D), the monitoring and the analysis of V5, NO.7 (Signaling System Number 7), GSM (global system for mobile communications), CDMA signaling systems such as (CDMAs), have very high cost performance.
Claims (5)
1. CDMA Signaling Analyzer based on parallel port, comprise: the Signaling Analyzer main frame, the Signaling Analyzer slave, wherein the Signaling Analyzer main frame comprises: memory buffer, the data transmit-receive module of the signaling data that line interface, storage collect from line interface; The Signaling Analyzer slave comprises: parallel interface, signaling message analysis part, display part is characterized in that: the Signaling Analyzer main frame is connected by the parallel interface of data transmit-receive module with the Signaling Analyzer slave, adopts the EPP pattern to communicate.
2. CDMA Signaling Analyzer according to claim 1 is characterized in that: described data transmit-receive module comprises:
Parallel interface: have data port and control mouth;
Latch: be connected with data port by data line, latch the address signal that sends from data port, and be sent to address generating module;
Code translator: the control mouth that connects parallel interface, receive the control signal of control mouth, its decoding back is produced the control word that the Notify Address generation module receives low section and high sector address, and the control address generation module sends the address to the control word of DPRAM, and the read-write control signal of DPRAM is sent in decoding;
Bus transceiver: be connected between data port and DPRAM by data line;
Address generating module: connect latch by address wire, receive high section, low sector address according to control word;
The circuit driver module: be connected between address generating module and DPRAM, DPRAM is arrived in the address that driving address generating module provides;
DPRAM: by address wire be connected with the circuit driver module, data line is connected with bus transceiver, parallel interface provides the read-write control command through code translator to it.
3, CDMA Signaling Analyzer according to claim 1 is characterized in that: described Signaling Analyzer slave is a notebook computer.
4, CDMA Signaling Analyzer according to claim 2 is characterized in that: described address generating module is 16 bit address generation modules, and memory buffer adopts dual port RAM to realize.
5,,, can also realize monitoring and analysis to GSM, ISDN, V5, NO.7 communication network signaling message by increasing different protocal analysis software according to one of them described CDMA Signaling Analyzer of claim 1-4.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNU2004200603759U CN2715237Y (en) | 2004-07-19 | 2004-07-19 | CDMA signaling analyzer based on parallel port |
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| Application Number | Priority Date | Filing Date | Title |
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| CNU2004200603759U CN2715237Y (en) | 2004-07-19 | 2004-07-19 | CDMA signaling analyzer based on parallel port |
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| CN2715237Y true CN2715237Y (en) | 2005-08-03 |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102867445A (en) * | 2012-09-12 | 2013-01-09 | 南通智翔信息科技有限公司 | CDMA (Code Division Multiple Access) signaling analysis teach simulated training equipment |
| CN106101277A (en) * | 2016-08-11 | 2016-11-09 | 昆明民安消防设备有限公司 | A kind of fire-fighting remote data acquisition and feedback starter |
| CN106125720A (en) * | 2016-08-25 | 2016-11-16 | 北京交大思诺科技股份有限公司 | The digital IO mouth flash chamber of test fixture |
| CN106354678A (en) * | 2016-08-25 | 2017-01-25 | 北京交大思诺科技股份有限公司 | Digital input and output expansion device and method of testing tooling |
-
2004
- 2004-07-19 CN CNU2004200603759U patent/CN2715237Y/en not_active Expired - Fee Related
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102867445A (en) * | 2012-09-12 | 2013-01-09 | 南通智翔信息科技有限公司 | CDMA (Code Division Multiple Access) signaling analysis teach simulated training equipment |
| CN102867445B (en) * | 2012-09-12 | 2015-08-05 | 上海智翔信息科技股份有限公司 | CDMA signalling analysis teaching simulation Practical training equipment |
| CN106101277A (en) * | 2016-08-11 | 2016-11-09 | 昆明民安消防设备有限公司 | A kind of fire-fighting remote data acquisition and feedback starter |
| CN106125720A (en) * | 2016-08-25 | 2016-11-16 | 北京交大思诺科技股份有限公司 | The digital IO mouth flash chamber of test fixture |
| CN106354678A (en) * | 2016-08-25 | 2017-01-25 | 北京交大思诺科技股份有限公司 | Digital input and output expansion device and method of testing tooling |
| CN106125720B (en) * | 2016-08-25 | 2018-08-31 | 北京思诺信安科技有限公司 | Digital IO mouth flash chamber |
| CN106354678B (en) * | 2016-08-25 | 2023-08-18 | 黄骅市交大思诺科技有限公司 | Digital input/output port capacity expansion device and method of test fixture |
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| Date | Code | Title | Description |
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| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| ASS | Succession or assignment of patent right |
Owner name: CHONGQING CHONGYOU DONGDIAN COMMUNICATION TECHNOL Free format text: FORMER OWNER: CHONGQING UNIVERSITY OF POST AND TELECOMMUNICATIONS Effective date: 20061110 |
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| C41 | Transfer of patent application or patent right or utility model | ||
| C56 | Change in the name or address of the patentee |
Owner name: CHONGQING UNIVERSITY OF POST AND TELECOMMUNICATION Free format text: FORMER NAME OR ADDRESS: CHONG QING POST AND TELECOMMUNICATION COLLEGE |
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| CP03 | Change of name, title or address |
Address after: 400065 Chongqing Nan'an District huangjuezhen pass Fort Park No. 1 Patentee after: CHONGQING University OF POSTS AND TELECOMMUNICATIONS Address before: 400065 Chongqing Nan'an District huangjuezhen pass Fort Park No. 1 Patentee before: Chongqing University of Posts and Telecommunications |
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| TR01 | Transfer of patent right |
Effective date of registration: 20061110 Address after: 401121, Chongqing North New District hi tech park, Star Road, 62, Neptune technology building, D District, 7 floor Patentee after: CHONGQING CHONGYOU DONGDIAN COMMUNICATION TECHNOLOGY Co.,Ltd. Address before: 400065 Chongqing Nan'an District huangjuezhen pass Fort Park No. 1 Patentee before: Chongqing University of Posts and Telecommunications |
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| C17 | Cessation of patent right | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20050803 Termination date: 20120719 |