CN2700952Y - Non-CPU integrated circuit card for optimizing memory logic partition structure - Google Patents
Non-CPU integrated circuit card for optimizing memory logic partition structure Download PDFInfo
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- CN2700952Y CN2700952Y CNU200320100564XU CN200320100564U CN2700952Y CN 2700952 Y CN2700952 Y CN 2700952Y CN U200320100564X U CNU200320100564X U CN U200320100564XU CN 200320100564 U CN200320100564 U CN 200320100564U CN 2700952 Y CN2700952 Y CN 2700952Y
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Abstract
The utility model discloses an integrated circuit board for optimizing the logic partition structure of a memorizer, comprising an address counter, a memorizer, an I/O interface and a controller. The logic partition of the memorizer comprises a control area and a pluraligy of user data areas. The control area can be written by access authority control words; the access authority of user data areas is identified respectively by the different control bits of the control words. The controller also comprises a memorizer accessing mode register; the controller makes logical operation according to a partition indicator signal, an operation indicator signal and the value of the corresponding control bit of the register, so as to control the operation of each user data area to generate signals. The multiple user data areas of the IC card of the utility model is made access authority set respectively by the issuers, so as to meet the different requirements for each data area authority and volume of IC card memorizer because of business change, and thus the development time and cost is greatly saved.
Description
Technical field
The utility model relates to a kind of integrated circuit card (IC-card), particularly relates to the IC-card that a kind of physical storage is divided into a plurality of logical partitions and does not comprise CPU.
Background technology
In information society, people have higher requirement to aspects such as the security of information carrier, reliability, ease for use.IC-card with abilities such as storage, encryptions, with its tight data security, application flexibility and strong functions extendability widely are for the processing and the transmission of present information provides a kind of convenient reliable means.
Fig. 1 is the structural representation that does not comprise the IC-card chip of CPU in the prior art, is made up of address counter 1, controller 2, I/O interface 3 and storer 4, and CLK, RST and IO are respectively external clock input signal, reset signal and input/output signal.Wherein, storer 4 is divided into release data district, key district and data field, as shown in Figure 2; Address counter 1 produces address signal ADDR under CLK and the effect of RST signal; Controller 2 is according to the access rights of external input signal, ADDR signal and each logical partition of storer, be controlled to storer memory address signal, write enable signal WE, wipe and enable ER and to the generation of reading enable signal RE of I/O interface 3; I/O interface 3 will be stored data and output to the outside when the RE signal is effective.
The structured flowchart of above-mentioned controller 2 is made up of address decoder 21, logical partition selector switch 22, memory access drm controller 23 and memory access type decision device 24 as shown in Figure 3.21 pairs of ADDR signal interpretations of address decoder produce memory address signal and decode results signal; Logical partition selector switch 22 produces corresponding subregion indicator signal according to the decode results signal; Memory access type decision device 24 is operated indicator signal accordingly according to the combination results of CLK and RST; Memory access drm controller 23 pairs of operations indicator signal and subregion indicator signal are carried out computing by the logic of setting, and whether decision produces corresponding operation enable signal, thereby realize the control to outside reference-to storage.Wherein, the access rights of each logical partition of storer are that hardware circuit by memory access drm controller 23 decides.Thereby the size and the access rights of above-mentioned each logical partition are promptly set during fabrication, and the publisher also can't change, and can only be applicable to a certain fixed mode business.
But, at different business or in, be diversified to the requirement of data field access rights, and have only an a kind of data field of fixedly authority in the above-mentioned storer the increment of business, expansion, can not be provided with neatly by the publisher, this has just limited the practical application of IC-card greatly.
Further, even the logical partition in the above-mentioned storer has had needed various access rights, but because the size of each logical partition is fixed, still carrying out of business having been produced very big restriction in actual applications, is that example is illustrated with the phone IC-card below.
For example, sometimes need in the phone IC-card, store many group keys, like this in the process of the identification IC-card true and false, the inner employed key of logical encrypt computing of card can be by stored any group key in the authentication initiating signal selection card of external unit, under the situation that a group key is broken, can start other spare key and participate in computing, whole public telephone system is still run well.At this moment, the data field that will seek survival and have bigger " inaccessible " authority in the reservoir.
And for example, the publisher need bind one group of fixing IP phone account number in the release data district of storer sometimes, and phone will start the IP account number in the IC-card automatically when the user dials trunk call, avoid the loaded down with trivial details of subscriber dialing.At this moment, the data field that will seek survival and have bigger " read-only " authority in the reservoir.
And for example, sometimes require to have in the storer data field of bigger " readable erasable " authority, the user can write down some telephone numbers that often use in this zone, operator then can be with these telephone numbers as " Familiarity Number ", provide preferential to its conversation rate, to attract more client.Or the like.
The memory span of prior art IC-card is limited, and the access rights of each logical partition can't arbitrarily adjust, thereby can't be applicable to the needs of above multiple business simultaneously, must carry out chip design and manufacturing again.But,, be devoted to constantly to release new business, value-added service or carry out upgrading service as the distribution commercial city of IC-card and attract the consumer along with IC-card application more and more widely.Professional more and more diversified, the professional cycle of upgrading is also more and more faster, if all will carry out chip design and manufacturing again at every turn, promptly increased cost widely, developing the required time also will have a strong impact on professional rapid release, and therefore pressing for provides a kind of IC-card with bigger application flexibility.
The most direct way is the capacity that increases storer.But storer plays decisive role to area of chip, power consumption, yield rate, and is very sensitive to the increase of area because the IC-card area of chip is all smaller, increases memory span and will bring a series of problem.Therefore, effectively utilize existing memory, the reasonable distribution storage space improves the service efficiency of storer, and under the prerequisite that does not increase chip area, providing more, select more flexibly for the user of chip is the direction that the IC-card chip designer makes great efforts.
The utility model content
In view of this, the technical problems to be solved in the utility model provides a kind of integrated circuit card of optimize storage logical partition structure, the access rights of user data area are set respectively by the publisher, and can adjust the size of the data field with a certain access rights.
In order to solve the problems of the technologies described above, the utility model provides a kind of non-CPU integrated circuit card of optimize storage logical partition structure, comprise address counter, be divided into the storer of a plurality of logical partitions, I/O interface and controller, described controller comprises address decoder, produce the logical partition selector switch of subregion indicator signal according to decode results, produce the memory access type decision device of operation indicator signal according to external input signal, and according to setting authority and described operation, the memory access drm controller that the subregion indicator signal conducts interviews and controls, wherein
But the memory access mode control zone that comprises a write-access control of authority word in the logical partition of described storer, and some user data areas of determining access rights by the different control bits of described control word respectively;
Described controller also comprises a memory access mode register, is used for the described control word of readout memory and it is latched; Described controller carries out logical operation according to the value of corresponding control bit in subregion indicator signal, operation indicator signal and the described memory access mode register, and output is to the operation enable signal of each user data area.
Also comprise in the logical partition of above-mentioned storer and have fixedly the release data district and the key district of access rights.
Above-mentioned storer is preferable to be divided into 3～5 user data areas.
Above-mentioned memory access control of authority is made up of read operation control module, write operation control module and wiping operation control unit, in each operation control unit, the subregion indicator signal elder generation of each user data area carries out logical operation with the corresponding control bit in the described memory access mode register, after carrying out logical operation between the consequential signal of output, carry out logical operation with the operation indicator signal again, produce the operation enable signal.
As from the foregoing, IC-card of the present utility model is a plurality of by user data area is divided into, and can be by conduct interviews the respectively setting of authority of publisher, thereby can obtain the user data area of different access authority, and can set the size that identical or different access rights are regulated the data field with certain access rights by giving each user data area, have good application flexibility.Therefore, IC-card of the present utility model can adapt to professional the variation each the data field authority of IC-card storer and the different demands of capacity, needn't carry out chip design and manufacturing again, development time and cost have been saved greatly, for upgrading and expansion based on the value-added service of IC-card provide efficiently, hardware platform flexibly.
Description of drawings
Fig. 1 is not for comprising the structural representation of the IC-card chip of CPU in the prior art;
Fig. 2 is the logical partition synoptic diagram of storer among Fig. 1;
Fig. 3 is the structured flowchart of Fig. 1 middle controller;
Fig. 4 is the logical partition synoptic diagram of storer in the utility model example I C the core of the card sheet;
Fig. 5 is the structured flowchart of the utility model example I C the core of the card tablet controller;
Fig. 6 be among Fig. 5 in the memory access drm controller write operation control module with the logical schematic of user data area relative section.
Embodiment
To be example with the phonecard below, describe the structure and the principle of the non-CPU IC card chip of the utility model in detail.This IC-card chip also is to be connected to form by address counter 1 ', controller 2 ', I/O interface 3 ' and storer 4 ', and as shown in Figure 1, still, the logical partition of its storer and the structure of controller are unlike the prior art.
Storer 4 ' adopts EEPROM, its logical partition is divided into seven logical partitions as shown in Figure 4 altogether: release data district, key district, memory access mode control zone (MACB) and user data area one to four (user data area in the utility model is meant the logical partition that can be write its access rights of data setting by the publisher).The access rights of release data district, key district and memory access mode control zone are fixed as read-only, inaccessible and read-only respectively, and wherein, the publisher can write the access rights control word to each user data area in memory access mode control zone; The access rights of four user data areas are determined by independently one or two control bits separately, can be set at a kind of in inaccessible, read-only, read-write, the readable access rights such as erasable respectively, can be the same or different.The corresponding relation of control bit in the present embodiment memory access mode control zone and user data area, access rights is as shown in the table:
| Memory access mode control zone | The data field | Access rights |
| DF1 | User data area one | Read-only/read-write |
| DF2 | User data area two | Read-only/readable erasable |
| DF3 | User data area three | Inaccessible/read-only/readable erasable |
| DF4 | ||
| DF5 | User data area four | Inaccessible/read-only/readable erasable |
| DF6 |
To set different access rights for each user data area, only need to write corresponding value and get final product, thereby its control mode be very flexible at corresponding control bit.In the present embodiment, the when issued merchant is made as read-write, erasable, inaccessible and inaccessible respectively with the access rights of user data area one to four.
The division of above-mentioned storage logic partition, and control bit is to realize by the hardware configuration of controller 3 ' to the control of affiliated logical partition accessing operation.
The structure of controller 3 ' is made up of address decoder 31, logical partition selector switch 32, memory access drm controller 33, memory access mode register 34 and memory access type decision device 35 as shown in Figure 5.Wherein:
Address decoder 31, to the result of address counter, i.e. ADDR signal interpretation, the row address and the column address of generation storer are sent to logical partition selector switch 32 with the decode results signal simultaneously;
Logical partition selector switch 32 is judged the logical partition that it is affiliated according to the decode results signal, makes the indicator signal of address logical partition pointed effective, and delivers to memory access drm controller 33;
Memory access type decision device 35 produces different operation indicator signals according to the various combination form of CLK and RST, as reads indicator signal RE1, writes indicator signal WE1 or wipe indicator signal ER1, outputs to memory access drm controller 33;
Memory access mode register 34 is used to read the control word of memory access mode control zone and it is latched, promptly this register has been inherited the numerical value of memory access mode control zone, a certain position or certain two access rights of stipulating the counterlogic subregion in the register;
The value of 33 pairs of subregion indicator signals of memory access drm controller, operation indicator signal and memory access mode register is carried out logical operation, the generation that control is write enable signal WE accordingly, wiped enable signal ER and read enable signal RE.Wherein, WE and ER signal output to storer 4 ', storer is write wiped operation, and the RE signal outputs to I/O interface 3 ', outside the reading storer 4 ' data of control.Produce corresponding enable signal (WE and ER signal are directly used in wiping and writing of data) for legal accessing operation; If this logical partition is forbidden this accessing operation, then can not produce the enable signal of this operation, thereby realize control outside equipment access memory;
Above address decoder 31 and memory access type decision device 35 can be realized with traditional hardware circuit.The same with prior art, logical partition selector switch 32 is used to realize the logical partition division, and produce the indicator signal of subregion under it according to address signal, but need set up a memory access mode control zone, and an original user data area is divided into four.A kind of hardware implementations is: for the address of each byte in the storer 4 ', address decoder 31 all has a decode results output line corresponding with it, size according to seven logical partitions setting, the output line of all address correspondences in each subregion is carried out inclusive-OR operation in a logical block, its operation result is as the indicator signal output of this subregion, just can reach the division logical partition, and make the indicator signal effective aim of address subregion pointed.
And the memory access drm controller 33 of present embodiment except that subregion and operation indicator signal, is gone back the value of combined memory access mode register 34 control bits and is carried out logical operation together when user data area being conducted interviews control.Fig. 6 in the memory access drm controller write operation control module with the logical schematic of user data area relative section, suppose that high level is effective.As shown in the figure, (FQ1～FQ4) is earlier with (DF1～DF6) carries out AND operation to the subregion indicator signal of user data area one to four in the control corresponding position in the memory access mode register 34, when certain subregion indicator signal effectively and its control bit be set at when allowing operation, its output signal is (among the CNTL1-CNTL4 one) effectively; After carrying out inclusive-OR operation between the CNTL1-CNTL4 signal, again with write indicator signal WE1 and carry out AND operation, as long as have a signal effective among the CNTL1-CNTL4, then allow the WE1 signal to pass through, produce and write enable signal WE, can carry out write operation the corresponding units of storer, if CNTL1-CNTL4 is a disarmed state, just do not allow the WE1 signal to pass through, the WE signal remains disarmed state, can not carry out write operation to storer.In the memory access drm controller 33 read operation and wipe operation control unit and the structure of user data area relative section similarly, explanation no longer one by one.
For instance, the user data area one of present embodiment has read-only or read-write two kinds of access modes to select, and it is effective to suppose that signal is high level, its be set to read-write, then can the memory access mode register in the value of DF1 be set to 1.When write operation will be carried out to user data area one in the outside, after FQ1 signal value effective and DF1 is carried out AND operation, the CNTL1 signal of output also is a high level, carry out AND operation with current effective operation signal WE1 again, WE is effective, allows to carry out write operation; Otherwise, if that it is set to is read-only, then the value of DF1 can be made as " 0 ", when write operation will be carried out to user data area one in the outside, the FQ1 signal was effective, after carrying out AND operation with the value of DF1, the CNTL1 signal of output is a low level, because other subregion indicator signal is all invalid, so CNTL2～CNTL4 is also invalid, WE is invalid after the computing, forbids write operation.In addition because two kinds of optional access modes in this district all allow to carry out read operation, can be directly with its subregion indicator signal with read indicator signal RE1 and carry out and the operation (not shown), need not control bit and control.
In addition, 3 kinds of user data area three and four optional access right existences, so control bit is two, thereby may need earlier to deliver to corresponding operation control unit more respectively, as shown in FIG. through a code translator.What should be illustrated in addition is, for the user data area of inaccessible, still is readable in the inside of IC-card chip, just at the I/O interface it is shielded.
Usually, there is one in the release data district and is used for identifying distribution pattern and user model, under the distribution pattern, the publisher can be in the release data district, key district and memory access mode control zone write data, when distribution finishes, will be this reset, chip enters user model, just can not write data again.Under user model, the access rights of above-mentioned logical partition are to determine that by the logical circuit that adopts this is consistent with existing disposal route.
Logical block among the figure can adopt with door or door, not gate or its combination and realize at an easy rate, and the concrete structure of computing can have multiple, as, as long as with AND operation still is that the definition of inclusive-OR operation and signal significant level has relation, therefore can be by correct logical relation realization access control.
By above structure, make and on storer, divide a plurality of user data areas, and can be set to possibility respectively its access rights.Following table has been listed 7 kinds of concrete application combination:
| Subregion | Combination 1 | Combination 2 | Combination 3 | Combination 4 | Combination 5 | Combination 6 | Combination 7 |
| User data area one | Can write | Can write | Can write | Can write | Can write | Read-only | Read-only |
| User data area two | Erasable | Erasable | Erasable | Read-only | Read-only | ||
| User data area three | Inaccessible | Inaccessible | Inaccessible | Erasable | Inaccessible | ||
| User data area four | Erasable | Erasable |
Combination 1 is the scheme among the embodiment, and the user data area of this combination has three kinds of different access rights.Make up simultaneously 1 and combination 6 user data area three and four access rights are arranged to the state of inaccessible, just can deposit more private datas at this, as many group keys, the security performance of enhancing IC-card.Combination 3 all is arranged to erasable state with user data area two, three and four access rights, makes the continuous space of this sector address open fully to the user, with can just writing down more personal information, as some telephone numbers that often uses, conveniently use.Combination 6 and combination 7 all are arranged to a read states with the access rights of two and four user data areas respectively, increased the capacity in read-only data district, the publisher just can write the read-only release data of more users in this zone, carrying out fixed service, as binds one group of fixing IP phone account number.Certainly, possible combination is not limited to above-mentioned 7 kinds, and possible application also is diversified, enumerates no longer one by one at this.
It should be noted that the utility model is arranged to user data area a plurality of, enlarged the application flexibility of IC-card significantly.If have only a user data area, even the publisher can set its access rights, its array mode will be confined to limited several, and a lot of assembled schemes of the present utility model can not realize that all applicable type of service will be dwindled greatly.For example, by unique user data area is set as inaccessible, though can be used for depositing many group keys, but compare with the scheme of combinations thereof 1, just lacked and can write and erasable subregion, and made up 6 and compare and then lacked readable subregion, opposite, the utility model can obtain the effect the same with it by four user data areas all are made as inaccessible, thereby its dirigibility is nothing like the utility model.
In sum, non-CPU integrated circuit card of the present utility model, the publisher can be according to the needs of using, a plurality of user data areas in its storer are set to different access rights, and the size of different purposes data field adjusted, thereby the greatly application of the Feng Fu IC-card that does not comprise the CPU card, the publisher can carry out multiple business on a kind of IC-card, and needn't carry out the design and the manufacturing of chip again, development time and cost of development have been saved, also avoided causing original IC can't use the waste that brings, therefore had tangible technique effect and application prospects because of business changes.
Abovely the utility model is illustrated in conjunction with a kind of embodiment of the present utility model; but the utility model is not limited thereto; for those of ordinary skills; can carry out variations and modifications to above-mentioned embodiment under the situation that does not deviate from the utility model essence, these are all within protection domain of the present utility model.For example, storer is not limited to adopt EEPROM, can adopt dissimilar storeies in different application; The size of each logical partition and quantity can be set as required in the storer, as long as include a plurality of data fields that can set access rights by the publisher, because the access rights type that often adopts in the reality has only 3,4 kind, the quantity of user data area is preferable to be set to 3～5, or the like.
Claims (4)
1, a kind of non-CPU integrated circuit card of optimize storage logical partition structure, comprise address counter, be divided into storer, I/O interface and the controller of a plurality of logical partitions, described controller comprises address decoder, produce the logical partition selector switch of subregion indicator signal according to decode results, produce the memory access type decision device of operation indicator signal according to external input signal, and, it is characterized in that according to setting the memory access drm controller that authority and described operation, subregion indicator signal conduct interviews and control:
But the memory access mode control zone that comprises a write-access control of authority word in the logical partition of described storer, and some user data areas of determining access rights by the different control bits of described control word respectively;
Described controller also comprises a memory access mode register, is used for the described control word of readout memory when powering on and it is latched; Described controller carries out logical operation according to the value of corresponding control bit in subregion indicator signal, operation indicator signal and the described memory access mode register, and output is to the operation enable signal of each user data area.
2, integrated circuit card as claimed in claim 1 is characterized in that, also comprises in the logical partition of described storer to have fixedly the release data district and the key district of access rights.
3, integrated circuit card as claimed in claim 1 is characterized in that, described storer is divided into 3～5 user data areas.
4, integrated circuit card as claimed in claim 1, it is characterized in that, described memory access control of authority is made up of read operation control module, write operation control module and wiping operation control unit, in each operation control unit, the subregion indicator signal elder generation of each user data area carries out logical operation with the corresponding control bit in the described memory access mode register, after carrying out logical operation again between the consequential signal of output, carry out logical operation with the operation indicator signal again, produce the operation enable signal.
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| CNU200320100564XU CN2700952Y (en) | 2003-10-15 | 2003-10-15 | Non-CPU integrated circuit card for optimizing memory logic partition structure |
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| Application Number | Priority Date | Filing Date | Title |
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| CNU200320100564XU CN2700952Y (en) | 2003-10-15 | 2003-10-15 | Non-CPU integrated circuit card for optimizing memory logic partition structure |
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| CN2700952Y true CN2700952Y (en) | 2005-05-18 |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115757218A (en) * | 2022-11-22 | 2023-03-07 | 重庆鹰谷光电股份有限公司 | Computational logic system applied to semiconductor chip data storage |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115757218A (en) * | 2022-11-22 | 2023-03-07 | 重庆鹰谷光电股份有限公司 | Computational logic system applied to semiconductor chip data storage |
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