CN2664948Y - Electric automobile multiple source power assembly control apparatus of MPC500 type - Google Patents

Abstract

Disclosed is a control device of a processor type electric vehicle multi-energy power train, belonging to the automobile electronic control technology field , which is characterized in that a 32 bit automobile special structure embedded microprocessor is a core hardware; an extended interface for control bus and address/ data bus, a serial communication interface, a BDM debugging port and various of I/O signal interfaces are designed as a core main board which is connected with an I/O expansion board with a double-port RAM interface through a contact pin between boards standard connectors; the core main board and the I/O expansion board are composed of a hardware platform. Therefore, the system integration, the security of the vehicle and the technical performance are improved; the control device can be connected with an ECU of every part of an electric vehicle multi-energy power system through a CAN bus interface and the double-port RAM interface so that the flexibility and the portability are improved. The utility model can be adapted to the needs of different types of electric vehicles such as the electric vehicle, the hybrid electric vehicle and the fuel cell electric vehicle by the necessary software modules being changed.

Description

MPC500 processor formula electric automobile multiple-energy-source Powertrain control device

Technical field

MPC500 processor formula electric automobile multiple-energy-source Powertrain control device belongs to auto electronic control technology, relates in particular to the electric automobile Multi-Energy Dynamic Assemble Control System field that fuel cell consists of.

Background technology

Power assembly control system has produced great impact as a kind of new design concept to Automobile Design and manufacturing. U.S. Ford Motor Company points out that the exploitation of power assembly control system has become one of core link in the automotive development process in June, 2000 in the startup report of MOBIES engineering project, relevant research and development is found everywhere through the world. But " Multi-Energy Dynamic Assemble Control System " then is the new system concept that country's " 15 " 863 Program proposes, and this concept comes from orthodox car and only has a power source, and present electric automobile has a plurality of power sources. Power assembly such as fuel cell car is made of various energy resources such as fuel cell engine, battery, ultracapacitors. The automobile power assembly that is made of multiple-energy-source has proposed new specification requirement to software and hardware structure, the control algolithm of control system, such as the composition of the dynamic Control of multiple-energy-source and rationally assignment problem, control system and architectural question etc. The main task of Multi-Energy Dynamic Assemble Control System is to selected each parts of power assembly system of car load, develops each parts carrier on the basis of control system separately, and whole dynamical system is implemented comprehensive control. Electric automobile multiple-energy-source Powertrain control device based on MPC500 series microprocessor only need be by changing necessary software module, the needs that just can adapt to the dissimilar electric automobiles such as pure electric automobile, hybrid power electric automobile and fuel cell car, the hardware platform of formation multiple-energy-source dynamical system control system.

Patent has been declared by Shanghai Fuel Battery Automobile Power System Co., Ltd's " a kind of fuel-cell car power assembly method for designing ". The invention discloses a kind of fuel-cell car power assembly method for designing. Method of the present invention can be used for the fuel-cell car product development process to finish the design of its power assembly parameter. The method is analyzed as the basis with multi-state, can optimize fuel-cell car power assembly allocation plan, calculate exactly fuel-cell car drives sub-unit, Multi-Energy Dynamic Assemble Control System to the fuel cell engine sub-unit in the power assembly, other energy supply sub-unit, electricity performance requirement, determine simultaneously dynamic characteristic and the efficacious workaround of power assembly, and provide clear and definite target and the direction of effort for the design of each sub-unit. The method can support multiple-energy-source combination drive automotive development process to finish its power system parameter design.

Patent has been declared by China No.1 Automobile Group Co's " a kind of novel hybrid electric vehicle power assembly ". A kind of novel hybrid electric vehicle power assembly relates to take fuel oil and the power assembly of electricity as the hybrid vehicle of the energy. The above-mentioned shortcoming that exists to solve present hybrid vehicle, improve hybrid vehicle serviceability, improve its fuel economy, realize minimum discharge. It is comprised of engine, main clutch, motor, power synthesis device, speed changer, battery, power transmission shaft, back axle and wheel, characterized by further comprising time clutch, two inputs of power synthesis device link by the output shaft of main clutch, inferior clutch and engine, the output shaft of motor respectively, and the output of power synthesis device and the power shaft of speed changer link.

Patent has been declared by Wuhan University of Technology " multiple-energy-source power assembly semi-hardware type simulation test system ". A kind of multiple-energy-source power assembly semi-hardware type simulation test system. Comprise a desktop computer, 8 road modulus A/D capture cards, 8 way mould D/A transition cards, 32 way switch amount I/O cards and the digital signal generator that is connected with High Speed Serial USB converter, Software Development Platform Matlab/simulink, the starter that replaces actual vehicle operating, explosive motor, motor, battery, clutch, speed changer, wheel, vehicle body, the dynamic calculation model of low-voltage distribution system assembly, use the travel energy balance of each assembly of establishing equation of the dynamics of automobile, each assembly model is pressed self-characteristic work, use A/D, D/A, the I/O integrated circuit board, SCI and usb communication are set up contacting of Multi-energy Powertrain Controller and normatron, Multi-energy Powertrain Controller is carried out parameter control and logic control to model, the output parameter of model all passes through A/D, D/A, I/O, the mode of CAN integrated circuit board and SCI communication is transmitted, actual controller, various signal transducer cards and be used for replacing the simulation model of true assembly device to form together closed loop test system.

Patent has been declared by Dong Feng Auto Corporation's " multiple-energy-source stand arrangement of hybrid power electric automobile ". The invention belongs to the automobile test technology, particularly a kind of multiple-energy-source stand arrangement of hybrid power electric automobile; This scheme is implemented by following steps: the A. engine is connected with gearbox by clutch, main motor is connected in the gearbox rear end, power by behind the gearbox through the two-way output of differential mechanism, by reductor two-way output is synthesized to the output of axle, to realize being connected of dynamometer machine and dynamical system; B. engine air throttle controller ECU1, ISG controller ECU2, AMT controller ECU3, main electric machine controller PMU and power-supply management system BMU be with after the car load controller connects, again by the stand control system to car load controller sending and receiving signal. This test-bed scheme is suitable for hybrid vehicle multiple-energy-source power assembly, can be used for verifying parts and the systemic-functions such as engine, motor, gearbox, ISG, AMT, battery, ECU, wire harness.

Patent has been declared by Dong Feng Auto Corporation's " motor vehicle integrated control system for whole vehicle of hybrid power electric automobile ". The invention belongs to the automobile control technology; be particularly related to a kind of motor vehicle integrated control system for whole vehicle of hybrid power electric automobile; it is characterized in that: described integrated control system mainly forms by Multi-Energy Dynamic Assemble Control System with by the integrated car load control system set of the light current control in traditional car load control, strong power management, car load error protection, car load coordination and instrument signal management, and the power of described multiple-energy-source power assembly major control engine and motor distributes. This system has the function of car load control and multiple-energy-source Powertrain control. Compare with Multi-Energy Dynamic Assemble Control System with traditional car load control system, function has increased, and volume reduces greatly, and reliability is enhanced, and the validity of control and economy all have obvious raising.

" FC-EV Multi-Energy Dynamic Assemble Control System " is the research and development content of the responsible fuel cell city bus parts problem of department of computer science, Tsinghua university. Technical characteristic is the hardware platform of developing as core with 32 MPC500 series microprocessors take the automobile of a new generation of company of Motorola (MOTOROLA). So far, not yet see based on the multiple-energy-source Powertrain control device of MPC500 series microprocessor developing. Software platform adopts the embedded real time operating system of the OSEK of Tsing-Hua University that meets " open system of automotive electronics and interface software standard thereof " (OSEK standard), independent research, and multiple-energy-source Powertrain control algorithm. This shows that the development of Multi-Energy Dynamic Assemble Control System is not only to FC-EV project itself, and the development of auto industry all is significant.

Above-mentioned patent of having applied for. Shanghai Fuel Battery Automobile Power System Co., Ltd be a kind of fuel-cell car power assembly method for designing; China No.1 Automobile Group Co be a kind of composition structure of novel hybrid electric vehicle power assembly; The patent of Wuhan University of Technology is a kind of multiple-energy-source power assembly semi-hardware type simulation test system; " the multiple-energy-source stand arrangement of hybrid power electric automobile " patent of Dong Feng Auto Corporation is a kind of multiple-energy-source bench test arrangement. Although these several patents are relevant with electric automobile multiple-energy-source power assembly system, and control device does not have the technology correlation.

" motor vehicle integrated control system for whole vehicle of hybrid power electric automobile " patent and the degree of correlation of the present invention of Dong Feng Auto Corporation are higher. This patent is a kind of motor vehicle integrated control system for whole vehicle of hybrid power electric automobile, it is characterized in that Multi-Energy Dynamic Assemble Control System and traditional car load control combination are carried out integrated control together. Be a kind of novel hierarchy of control structure, but do not relate to the special control device for electric automobile multiple-energy-source power assembly based on concrete microprocessor.

Summary of the invention

The application's main purpose is for the limitation that overcomes prior art and weak point, proposes a kind of novel electric automobile multiple-energy-source Powertrain control device. This device is take 32 automobile special microprocessors (running temperature is-45 ℃～+ 125 ℃) as hardcore, disposed the SRAM of 2M byte and 2M byte the FLASH memory, designed expansion interface, serial communication interface, CAN EBI, BDM debug port and various I/O signaling interface to control bus, address/data bus, hardware integrated level and the technical performance of control device are greatly improved. Hardware platform is made of core mainboard and I/O expansion board two parts electronic circuit board, and the I/O expansion board has also designed special-purpose 72 needle sockets of automobile ECU, and the support to dual-port RAM interface is provided. Make control device both can also can pass through dual-port RAM interface by the CAN EBI, communicate and realize control with the ECU (ECU, Electric Control Unit) of each parts of electric automobile multiple-energy-source dynamical system. Control device only need just can adapt to by changing necessary software module the needs of the dissimilar electric automobiles such as pure electric automobile, hybrid power electric automobile and fuel cell car.

Of the present utility model being characterised in that, it also contains:

The core mainboard is made of following part:

The MPC500 microprocessor;

The following each several part that links to each other with this MPC500 microprocessor;

Pin type AN connector between circuit board, it comprises:

JP1: extend out the control bus interface;

JP2: extend out address bus, extend out data/address bus interface and power module interface;

JP3: time processing unit interface;

JP4: modulus translation interface and SPI;

JP5: pulsewidth modulation interface PWM, difunctional MIOS (modular input output system) interface, MIOS parallel input/output interface MPIO, 2 CAN (controller LAN) EBIs and 2 serial communication interfaces.

Also have: background debug mode port BDM;

Join serial interface chip and CAN interface chip that car is used with 72 needle connectors;

Outside FLASH;

Outside SRAM;

Latch the hardware reset control word switch that chip links to each other with this microprocessor MPC500 through data;

Crystal oscillator drives chip with the bus that is controlled by the hardware deploy switch;

In addition, also have power supply and reset chip.

For the I/O expansion board that the interface signal on the core mainboard is effectively expanded, it links to each other with the core mainboard by pin type AN connector JP1～JP5 between circuit board, and be equipped with special-purpose 72 needle sockets of automobile ECU (ECU), consisted of by following part:

Special-purpose 72 needle sockets of automobile ECU, it includes:

The electric power system interface: it with the foregoing circuit plate between among the JP2 of pin type AN connector the power module interface link to each other;

PWM and analog signal output interface: the PWM interface of PWM output interface and JP5 links to each other, and analog signal output interface links to each other through the PWM interface of high speed light lotus root and JP5;

Analog input interface: it with the foregoing circuit plate between among the JP4 of pin type AN connector the modulus translation interface link to each other;

Digital quantity I/O interface: it with the foregoing circuit plate between among the JP5 of pin type AN connector the parallel input/output interface MPIO of MIOS link to each other;

TPU (time processing unit) interface: it with the foregoing circuit plate between the JP3 of pin type AN connector link to each other;

Communication system interface, it comprises:

Serial communication interface: it with the foregoing circuit plate between among the JP5 of pin type AN connector serial communication interface link to each other;

The CAN communication interface: it with the foregoing circuit plate between among the JP5 of pin type AN connector the CAN EBI link to each other;

Dual-port RAM interface.

Data/address bus drives chip: it with the foregoing circuit plate between extend out the data/address bus interface among the JP2 of pin type AN connector and link to each other with above-mentioned dual-port RAM interface;

Address bus drives chip: it with the foregoing circuit plate between extend out address bus interface among the JP2 of pin type AN connector and link to each other with above-mentioned dual-port RAM interface;

The address decoding chip: it extends out among the JP1 of pin type AN connector and extends out the control bus interface among address bus interface, the JP1 and link to each other with above-mentioned dual-port RAM interface respectively with between the foregoing circuit plate.

Switch S1: totally 8, wherein

If the VPP position is set to one state, do the inner erasable operation of FLASH of MPC500 and program voltage;

The EPEE position is one state, and expression can be programmed and erasable FLASH;

MODCK[1:3] three: latch chip through data and drive, link to each other with MPC500, to dispose phaselocked loop (PLL)/clock operation pattern;

Switch S2, S3 and S4: each 8, latch chip by other three data respectively and link to each other with data/address bus, to realize hardware reset control;

Switch S5: totally 8, above-mentioned SRAM and FLASH are done sheet select.

The experimental prototype (THECU-2002) based on the electric automobile multiple-energy-source Powertrain control device of MPC500 microprocessor of having finished has disposed 72 needle connectors of automobile ECU special use and has passed through EMC test by national standard GB/T17619-1998.

Compare with existing power assembly system of electric vehicle control device, concrete technique effect of the present utility model is:

1) employing of automobile-used 32 the embedded microprocessors of PowerPC structure of a new generation has improved the integrated level of system, vehicle-mounted reliability and systems technology performance. So far, not yet see based on the electric automobile multiple-energy-source Powertrain control device of MPC500 series microprocessor developing.

2) increased dual-port RAM interface on the I/O expansion board electronic circuitry design. Make control device both can also can pass through dual-port RAM interface by the CAN EBI, communicate and realize control with the ECU of each parts of electric automobile multiple-energy-source dynamical system. Make application flexibility, the portability of control device bring up to a new height.

3) the control device communications anti-jamming can raising and the quickening (detailed introduction is arranged in the back) of computing control rate, the Optimized Operation of the power system of electric automobile distributed control network that makes multinode and interfacing level, multi-energy system with manage the control level and greatly improve.

Description of drawings

Fig. 1. FC-EV multiple-energy-source power assembly system structured flowchart

Fig. 2. FC-EV multiple-energy-source Powertrain control device THECU-2002 type experimental prototype hardware structure diagram

The hardware principle block diagram of Fig. 3 .THECU-2002 type experimental prototype core mainboard

The hardware principle block diagram of Fig. 4 .THECU-2002 type experimental prototype I/O expansion board

Fig. 5 .MPC555 microprocessor pin distribution map

Fig. 6. the memory expansion schematic diagram

Fig. 7 .I/O expansion board circuit theory diagrams

The read cycle sequential chart of Fig. 8 .SRAM memory

The write cycle time sequential chart of Fig. 9 .SRAM memory

The specific embodiment

The embodiment based on the electric automobile multiple-energy-source Powertrain control device of MPC500 series microprocessor that the utility model proposes is to have developed FC-EV Multi-Energy Dynamic Assemble Control System THECU-2002 type experimental prototype, is elaborated below in conjunction with accompanying drawing and embodiment.

FC-EV multiple-energy-source power assembly system framework as shown in Figure 1. Dynamical system is made of motor controller, fuel cell, battery, DC/DC converter etc., realizes physical connection by electric bus. Realize communicating by letter by CAN (controller LAN) bus between power assembly ECU and parts ECU. The utility model relates to power assembly ECU part (Powertrain ECU).

FC-EV Multi-Energy Dynamic Assemble Control System THECU-2002 type experimental prototype is take the MPC555 microprocessor as core, the sufficient expansion that its function is carried out, external memory storage FLASH and SRAM have extended out respectively the byte of 2M, whole experimental prototype is take 72 needle connectors of automobile ECU special use as physical interface, for automobile provides the communication of CAN bus, serial communication, the defeated A/ output of digital quantity, analog quantity I/O, pulsewidth modulation (PWM) is exported and the function of time processing unit (TPU) interface. In addition, also design flexibly dual-port RAM interface, made control device both can also can pass through dual-port RAM interface by the CAN EBI, communicated and realized control with the ECU of each parts of electric automobile multiple-energy-source dynamical system. This experimental prototype can be worked under mobile, harsh at a high speed environment, has design flexibility, system reliability and the powerful expanded function of height, and is fit in enormous quantities, low-cost production. Control device is supported the communication of CAN bus, has stronger antijamming capability, and GB/T17619-1998 has passed through EMC test by national standard.

THECU-2002 type experimental prototype hardware platform is made of two parts electronic circuit board: core mainboard and I/O expansion board. As shown in Figure 2.

The theory diagram of THECU-2002 type experimental prototype core mainboard as shown in Figure 3. The exploitation of core mainboard is 32 embedded automobile-used MPC500 series microprocessors that adopt U.S. MOROROLA company, is equipped with serial communication interface, CAN EBI, BDM debug port and various I/O signaling interface. Realized control bus, address/data bus expansion interface, TPU interface, PWM pulsewidth modulation interface, A/D interface and I/O system interface etc., the memory aspect respectively is the 2M byte according to actual conditions design SRAM and FLASH.

In order more to be fit to application needs of electric automobile multiple-energy-source Powertrain control, the function of enhancing core mainboard is also effectively expanded the interface signal on the core mainboard. We have further developed the I/O expansion board of model machine. This I/O expansion board links to each other with the core mainboard by pin type AN connector between the circuit board, has consisted of the overall structure of THECU-2002 type experimental prototype, and its hardware principle block diagram as shown in Figure 4. I/O expansion board major function is that the interface signal of core mainboard is expanded, be made of 5 large interface modules altogether: the JP1 interface module is the expansion to control bus, JP2 is the expansion to address/data bus, JP3 is the expansion to the TPU module, JP4 is the expansion of A/D module and SPI, and JP5 is the expansion to CAN bus, SCI, MDA, PWM, MPIO function. Also increased on the expansion board in addition 72 needle connectors of automobile ECU special use have been disposed in support and the design of dual-port RAM interface.

The circuit structure of THECU-2002 type experimental prototype forms and comprises: 72 needle connector interface circuits of microprocessor MPC555, electric power system, reset circuit, outer extension memory, hardware configuration control word switch, background debug port (BDM), dual-port RAM interface circuit, communication interface part, digital-to-analogue conversion circuit and automobile ECU special use etc. Referring to accompanying drawing 5,6,7, the main circuit part is as follows.

(1) microprocessor is selected the MPC555 of MOTOROLA company, outside crystal oscillator 4MHz. Main pin title and function description see Table 1. All pin titles of MPC555 are referring to accompanying drawing 5.

(2) the main chip of electric power system certain applications has two (seeing Fig. 7): LT1374I5 and LT1587-CT3.3. These two products that chip all is LINEAR company. LT1374I5 switching mode voltage-stablizer (Switching Regulator) has following functions characteristic: 6V～25V DC input voitage, 5V/4.5A output. Operating temperature-40 ℃～125 ℃. The supply voltage of 5V is provided for system. The LT1587-CT3.3 input voltage is 4.75V～7V, 3.3V output, output current 0mA～3A; For MPC555 provides the 3.3V supply voltage.

The pin title	Function
		PORESET	Upper reset.
HRESET	Hardware reset.
		SRESET	The software reset.
A[8:31]	Address bus.
		D[0:31]	Data/address bus.
RD/WR	The read/write signal line, the designation data transmission direction.
		OE	Output effectively.
WE[0:3]	With effect, WE0 confirms D[0:7] data, WE1 confirms D[8:15], WE2 confirms D[16:23], WE3 confirms D[24:31].
		CS[0:3]	The chip selection signal line.
RSTCONF	Configuration-input resets. Configuration resets when the HRESET signal is confirmed.
		VPP	The erasable operating voltage input of inner FLASH.
EPEE	The erasable operating control signal line of inner FLASH.
		MODCK[1:3]	Clock module configuration word.
A_CNTX0	CAN controller serial data output signal line.
		B_CNTX0	CAN controller serial data output signal line.
A_CNRX0	CAN controller input serial data signal line.
		B_CNRX0	CAN controller input serial data signal line.
TxD[1:2]	The serial data output signal line of SCI.
		RxD[1:2]	The input serial data signal line of SCI.
PWM[0:7]	The pulse width modulating signal line.
		MPIO[0:15]	General I/O holding wire.
A_TPU[0:4]	The TPU functional pin.
		DSCK	Exploitation port serial clock
DSDI	Exploitation port serial input pin

The main pin function description of table 1 MPC555

(3) reset circuit has adopted the DS1233 reset chip (seeing Fig. 7) of DALLAS company, and its operating temperature range is-40 ℃～85 ℃. DS1233 provides Power Supply Monitoring, and (effectively improve voltage monitoring precision and the reliability of system, when any input voltage drops into corresponding detection thresholding when following, chip produces the output that resets. ) and two kinds of functions of push-button reset. In this control device, we have used the push-button reset control function of DS1233. PORESET (power reset) button connects the RST output pin of DS1233, when pressing the PORESET button, DS1233 will produce 350 milliseconds reset pulse (Low level effective) until release-push, the PORESET pin of MPC555 is confirmed to enter the power reset state after the reseting pulse signal. When DS1233 not among the reset cycle, its continuous monitoring RST signal is waited for low level rising edge, if detect this rising edge, DS1233 will bounce and switch that to put the RST signal be low level. After timer internal is overtime, DS1233 will continue the level of monitoring RST holding wire. If holding wire is still low level, DS1233 will continue this holding wire of monitoring and seek rising edge, until detect a release signal, DS1233 will put the RST signal to be low level and to keep 350 milliseconds.

The function of two other SR (HRESET and SRESET) is to make MPC555 produce hardware reset and software reset's operation. After pressing HRESET (hardware reset) button, will send a low level signal to the HRESET pin of MPC555, detect the affirmation of a HRESET low level signal as MPC555 after, enter the hardware reset state. Equally, if after pressing SRESET (software reset) button, will send a low level signal to the SRESET pin of MPC555, detect the affirmation of a SRESET low level signal as MPC555 after, enter software reset's state.

(4) outer extension memory of THECU-2002 type experimental prototype comprises FLASH and SRAM (seeing Fig. 6). FLASH selects the AM29LV800BB-90EC of AMD, totally two. Total memory capacity is the 2M byte. Read-write operation supply voltage scope 2.7～3.6V, the access time was 90 nanoseconds. Main pin title and function declaration thereof are as shown in table 2:

Pin	Functional description	Circuit connects
			A[0:18]	The address input.	Address pin A[29:11 with MPC555] link to each other.
DQ[0:14]	15 data I/O.	The DQ[0:15 of first AM29LV800BB-90EC] D[15:0 of pin and MPC555] data wire links to each other the DQ[0:15 of second AM29LV800BB-90EC] D[31:16 of pin and MPC555] data wire links to each other.
			DQ15/A-1	DQ15 (data I/O, word pattern), A-1 (address input pin, byte mode).
CE	Chip is effective.				Controlled by the S5 switch.
		OE	Output effectively.	Link to each other with the RD/WR pin of MPC555.
WE	Write operation is effective.				Link to each other with the OE pin of MPC555.
		RESET	The hardware reset pin, low level activates.	Link to each other with the HRESET pin of MPC555.
BYTE					Connect high level.

The main pin explanation of table 2 AM29LV800BB-90EC chip and circuit connect

Wherein BYTE controls data I/O (input and output) pin DQ[0:15] operation is with the pattern of word or with the configuration of the pattern of byte. Namely select 16 (word) patterns or 8 (byte) patterns. If BYTE is made as logical one, FLASH is configured to the pattern of word, DQ[0:15] pin is activated and by the control of CE, OE pin. If BYTE is set to logical zero, FLASH will be configured to byte mode. DQ[0:7] pin is activated and by the control of CE, OE pin. DQ[8:14] pin is in three-state (tri-stated) state. Under byte mode, DQ15 will realize the A-1 address function as input pin. In our system, BYTE is set to high level, namely FLASH is configured to word pattern, DQ[0:15] be used as data I/O pin.

SRAM selects the IC61LV5128-12K chip of ISSI company, and totally four, total memory capacity is the 2M byte. Access time was 12 nanoseconds. Supply voltage 3.3V. Main pin function declaration is as shown in table 3:

Pin

Functional description

Circuit connects

A[0:18]	The address input.	Address pin A[29:11 with MPC555] link to each other.
			CE	Chip is effective.	Controlled by the S5 switch.
OE	Output effectively.	Link to each other with the OE pin of MPC555.
			I/O[0:7]	The I/O port.	The I/O[0:7 of four IC61LV5128-12K] pin connects respectively the data wire D[31:24 of MPC555], D[23:16], D[15:8], D[7:0].
WE	Write operation is effective.	The WE pin of four IC61LV5128-12K connects respectively the WE[0:3 of MPC555] pin.

The main pin explanation of table 3 IC61LV5128-12K chip and circuit connect

(5) five hardware configuration control word switches (8 DIP switches). Function is as shown in table 4.

The switch title	Functional description
			The S1 switch, totally 8.	The VPP position	If the conducting state of being set to, will be as MPC555 inside FLASH erasable and programming 5V supply voltage.
The EPEE position	The control signal of the inner FLASH programming of MPC555 or erasable operation. Be set to conducting state, the expression erasable FLASH that can programme.
		MODCK[1:3] three		Through the driving of the 74LVC125 chip of PHILIPS company, with the MODCK[1:3 of MPC555] pin links to each other. Function is the configurable clock generator operator scheme.
The EN_CFG position	If the conducting state of being set to will allow the control word that resets of configuration MPC555, otherwise, the default value of the control word that resets used.
		S2, S3, S4 switch, each 8.		Be respectively D[16:23], D[24:31] and D[0:7] hardware reset control word switch. S2, S3, the S4 switch 74LVC573A by 3 PHILIPS companies latchs chip and links to each other with data/address bus, realizes hardware reset control function.
The S5 switch, totally 8.	Four chip selection signal CS0～CS3 of control MPC555, four of fronts are SRAM sheet selected control switches processed, four of back are FLASH sheet selected control switches processed. The SRAM chip selection signal is CS1 in this control device, and the FLASH chip selection signal is CS0.

Table 4 hardware configuration control word switching function table

(6) communication system interface comprises the communication of CAN bus, serial communication and dual-port RAM interface. CAN control unit interface chip is selected the PCA82C250 of PHILIPS company. Because built-in two the TouCAN modules of MPC555 (CAN bus control unit) are so select two PCA82C250 as interface chip. The supply voltage scope is 4.5V～5.5V. Operating temperature range is-40 ℃～125 ℃. Main pin function is as shown in table 5:

Pin	Functional description	Circuit connects
			TxD	The input of transmission data.	A_CNTX0 and B_CNTX0 pin with MPC555.
RxD	Receive data output.	The A_CNRX0 and the B_CNRX0 pin that connect MPC555.
			CANL	The low level of CAN voltage I/O	Connect 72 pin automobile ECU private jacks
CANH	The high level of CAN voltage I/O.	Connect 72 pin automobile ECU private jacks
			Rs	The slope resistance input.	Ground connection

The main pin explanation of table 5 PCA82C250 interface chip and circuit connect

Wherein the Rs pin is the slope resistance input, is controlled by wire jumper. Totally three kinds of different operator schemes are selected: at a high speed, slope control and standby mode. Under the high speed operator scheme, send the transistor of output with fast as far as possible switching, the without limits measurement of rising and descending slope. Use shielded cable (RFI:radio frequency interference) problem to avoid radio frequency to disturb. Can select fast mode by Rs pin ground connection. For the situation of low transmission rate or short total line length, bus can adopt unshielded twisted pair or parallel line. Disturb in order to reduce radio frequency, should limit the slope that rises and descend. The Rs pin is controlled the ratio of slope by connecting resistance. If Rs connects high level, will enter the low current standby mode. Under this pattern, transmitting terminal will be closed, and receiving terminal switches to low current mode. Microprocessor could work by transmitting terminal is switched normal manipulation mode. In this control device, we select fast mode, namely make Rs pin ground connection.

The interface chip of serial communication is selected the MAX233AEWP of MAXIM company. Operating temperature is-40 ℃～85 ℃. Main pin function declaration is as shown in table 6.

Pin	Functional description	Circuit connects
			T1 INAnd T2IN	The TTL/CMOS input.	SCI module TxD[1:2 with MPC555] pin links to each other.
R1 OUTAnd R2OUT	The TTL/CMOS output.	SCI module RxD[1:2 with MPC555] pin links to each other.
			T1 OUTAnd T2OUT	The RS-232 output.	Link to each other with 72 pin automobile ECU private jacks
R1 INAnd R2IN	The RS-232 input.	Link to each other with 72 pin automobile ECU private jacks

The explanation of table 6 MAX233AEWP serial communication interface chip pin and circuit connect

Dual-port RAM interface circuit is as shown in table 7. The interface of dual-port RAM is included in the 72 pin automobile ECU private jacks.

Pin	Functional description	Circuit connects
			A[0:10]	Address wire	A[31:21 with MPC555] pin links to each other. The address space of the dual-port RAM of 2K is provided.
D[0:7]	Data wire	D[0:7 with MPC555] pin links to each other. 8 data width.
			WR	With effect	The WE0 pin that connects MPC555
CS	Chip selection signal	The CS2 pin that connects MPC555
			RD	Read effectively	The RD/ WR pin that connects MPC555

The explanation of table 7 dual-port RAM interface circuit and circuit connect

(7) analog quantity I/O, PWM, digital quantity I/O and the explanation of TPU functional pin are as shown in table 8.

Pin	Functional description	Circuit connects
			ACC_IN	The analog quantity input	The A_AN0 pin that connects the QADC module of MPC555.
BRK_IN	The analog quantity input	The A_AN1 pin that connects the QADC module of MPC555.
			AIN[2:7]	The analog quantity input	The A_AN[2:7 that connects the QADC module of MPC555] pin.
PW[0:3]	PWM output	The PWM[0:3 that connects MPC555] pin.
			AO[0:3]	Analog quantity output	The PWM[4:7 of MPC555] holding wire through high speed light lotus root 6N137 isolation after output.

DIN[0:7]	The digital quantity input	The MPIO[0:7 that connects MPC555] pin
			DOT[0:7]	The digital quantity input	The MPIO[8:15 that connects MPC555] pin
TPU[0:4]	The TPU function is supported	The A_TPU[0:4 that connects MPC555] pin.

The I/O of table 8 analog quantity, PWM, digital quantity I/O and the explanation of TPU functional pin

(8) 72 needle connector function groups of automobile ECU special use.

The function of first group of pin is the electric power system for control device.

Second group of pin provides 4 road pwm signals and 4 tunnel simulation output signals.

The 3rd group of pin provides 8 road analog input signals. Be connected with ADC (modulus conversion) module of MPC555, realize that the automobile analog signal is to the conversion of data signal.

The 4th group of pin provides 16 railway digital signal input/output functions.

The 5th group of pin provides communication function, comprises serial communication, the communication of CAN bus.

The 6th group of pin provides the TPU function.

The 7th group of pin provides the support to dual-port RAM interface.

Table 9 has provided pinout and the functional description of 72 needle connectors.

Group name	The pin name	Character	Physical significance	Remarks
					First group of POWER	VBAT		The input of 24V power supply
VBAT
				DVIN			The voltage input	The input of digital quantity reference voltage
GND		Systematically
				GND
Second group of AO/PWM	AO0	Imitated output quantity	Water temperature control (+)						Range: 0-4.5V represents-20 ℃-100 ℃
				AO1	Imitated output quantity	Water temperature control (-)
	AO2	Imitated output quantity	Motor speed control (+)					Range: 0-4.5V represents 0-5400rpm
				AO3	Imitated output quantity	Motor speed control (-)
	PWM0	PWM output
				PWM1	PWM output
	PWM2	PWM output
				PWM3	PWM output
	The 3rd group of A_IN	ACC_IN	The analog input amount					Accelerator pedal
BRK_IN				The analog input amount	Brake pedal
		AIN2	The analog input amount				Automobile GES (+)	Range: 0-9V
AIN3				The analog input amount
		AIN4	The analog input amount
AIN5				The analog input amount
		AIN6	The analog input amount
AIN7				The analog input amount

The 4th group of D_I/O	DIN0	Digital input amount	Fuel Cell Engine switch
					DIN1	Digital input amount	Emergency switch
	DIN2	Digital input amount	R shelves (reverse gear)
					DIN3	Digital input amount	The I shelves
	DIN4	Digital input amount	The II shelves
					DIN5	Digital input amount	N shelves (neutral gear)
	DIN6	Digital input amount	Key is in the ON position	Expression enters real driving condition
					DIN7	Digital input amount	Hydrogen leaks
	DOT0	Digital output	The water temperature temperature alarm
					DOT1	Digital output	The Ready signal
	DOT2	Digital output
					DOT3	Digital output
	DOT4	Digital output
					DOT5	Digital output
	DOT6	Digital output
					DOT7	Digital output
	The 5th group of COM_Port	CANH		The CAN bus					High level CAN voltage I/O end
CANL						The CAN bus	Low level CAN voltage I/O end
		CANH		The CAN bus				High level CAN voltage I/O end
CANL						The CAN bus	Low level CAN voltage I/O end
		TXD1		RS232				The serial communication transmitting terminal
RXD1						RS232	The serial communication receiving terminal
		TXD2		RS232				The serial communication transmitting terminal
RXD2						RS232	The serial communication receiving terminal
		The 6th group of TPU	TPU0
TPU1
			TPU2
TPU3
			TPU4
The 7th group of DPRAM	ADDR0					Dual-port address ram line
		ADDR1		Dual-port address ram line
	ADDR2					Dual-port address ram line
		ADDR3		Dual-port address ram line
	ADDR4					Dual-port address ram line
		ADDR5		Dual-port address ram line
	ADDR6					Dual-port address ram line

	ADDR7		Dual-port address ram line
					ADDR8		Dual-port address ram line
	ADDR9		Dual-port address ram line
					ADDR10		Dual-port address ram line
	DATA0		Dual-port RAM data wire
					DATA1		Dual-port RAM data wire
	DATA2		Dual-port RAM data wire
					DATA3		Dual-port RAM data wire
	DATA4		Dual-port RAM data wire
					DATA5		Dual-port RAM data wire
	DATA6		Dual-port RAM data wire
					DATA7		Dual-port RAM data wire
	/WR		Dual-port RAM write signal
					/CS		Dual-port RAM chip selection signal
	/RD		Dual-port RAM read signal

72 needle connector functional interpretations of table 9 automobile ECU special use

The main hardware circuit that has more than provided control device forms structure and realizes principle, and the below will describe the course of work of system in detail.

(1) working-flow before and after the upper reset.

Before system powered up, fibrous root was configured work according to using the difference that needs to control device, mainly is to finish the setting of wire jumper and the set of hardware deploy switch. Now illustrate as follows.

MODCK[1:3 among the S1] be set to " 010 ". The reset of EN_CFG position. " 1 " expression conducting, " 0 " represents not conducting. The 2nd that puts S5 is one state, makes the CS1 conducting, chooses outside SRAM. The 5th CS0 of S5 is set to one state, chooses outside FLASH.

After system powers on, through voltage-stablizer LT1374I5 input voltage is converted to 5V, for the chip of 5V power voltage supply on the electronic circuit board provides voltage. Through the voltage-stablizer LT1587-CT3.3 of fixing output 3.3V, be 3.3V voltage with the 5V voltage transitions again. Chip power supply for MPC555 microprocessor and 3.3V supply voltage. Arrive this, the electric power system of whole control device is finished.

When powering on reset operation, MPC555 will detect the low level input signal of PORESET, enter the reset mode that powers on after the affirmation, according to MODCK[1:3] signal determine crystal oscillator frequency, phaselocked loop (PLL:phase-locked loop) multiplier parameter, cycle Abort Timer clock (PITRCLK) and time base clock source (TMBCLK). And MPC555 also confirms HRESET and the input of SRESET pin. When the rising edge of PORESET, will determine the state of MODCK pin, MODCK[1:3 in this example] be set to " 010 ", because the frequency of crystal oscillator is 4MHz, so the primary timing reference frequency is 4MHz, PLL is effective, and normal manipulation mode, multiplier parameter are 5, the TMBCLK clock is with 4 frequency divisions, and the PITRCLK clock is with 256 frequency divisions. Obtained system clock frequency this moment. After withdrawing from the reset mode that powers on, MPC555 will continue to drive HRESET and the SRESET pin continues 512 system clock cycles. After confirming the HRESET signal, in the sampling time (HRESET is low level), RSTCONF is identified, in this control device, the RSTCONF signal is determined by the EN_CFG position of hardware deploy switch S1, the RSTCONF signal should be the high level input, and this moment, the 20th HC at the hardware reset configuration word register of MPC555 was 0, and system will start from external memory storage. The configuration word that resets this moment is provided by the CMFCFIG register. Starting relevant position with device in this register has as follows:

The BDIS position is 0, and after expression resetted, Memory Controller Bank0 was activated, and the BR0 register is effective, and the CS0 chip selection signal of MPC555 is effective, and by the 5th bit switch gating CS0 of S5, system will start from FLASH.

The IP position is 0, and after expression resetted, the IP position in machine status register(MSR) (MSR) register equaled 0, and exception vector table will begin from the physical address 0x0,000 0000 of FLASH. Because be the hardware reset operation, it is unusual to have produced system reset, according to exception vector table, program pointer should point to 0x0,000 0100 place, and system program should take this address as entrance, be carried out.

After the driving of SRESET pin was identified, the configuration of debug port will be from DSCK and the sampling of DSDI pin.

After 512 clock cycle, MPC555 stops to drive HRESET and SRESET pin, and the reset operation that powers on is finished. In the reset operation that once powers on, comprised that reseting logic and PLL state reset, system's configuration resets, clock module resets, the HRESET pin drives, the debug port configuration, other internal logics reset and the SRESET pin drives.

More than with an example described system from power on before the switch configuration of hardware circuit and wire jumper work be set begin, the signal flow direction and the associative operation of reset MPC555 microprocessor on the system, and finish the overall process that resets. The reset mechanism that mainly powers on when this example has also illustrated the work of this control device.

(2) memory operation flow process

For extending out the FLASH memory, we can be as seen from Table 10, reset, the pin state of FLASH chip during read and write operation.

When FLASH resetted, the RSET pin linked to each other with the HRESET pin of MPC555, and when confirming that MPC555 has reset operation, RSET is low level, and each pin state of FLASH device sees table 10 for details.

Annotate: " L " represents low level, and " H " represents high level, and "-" expression does not affect operation

The state of each pin during table 10 FLASH storage operation

When reading the FLASH operation, the RD/WR of MPC555 and CS0 pin output low level signal drive FLASH memory OE, the CE pin is low level. Address bus provides stable address signal, and the CE signal is used for choosing the FLASH memory, and OE is data output control signal, allows data output. The WE pin should keep exporting high level. At this moment, the data pin of FLASH memory will be exported effective data, send the data pin of MPC555 microprocessor to by data/address bus, finish the receive data operation, namely data be read the address of appointment.

The write operation of FLASH comprises the programming of FLASH and erasable operation. WE and CE are driven to low level, and OE is high level.

Before explanation SRAM memory read/write cycle sequential, at first given the time response of read/write cycles by table 11.

Label	Describe	Minimum time	Maximum time	Chronomere
					t RC	Tead cycle time	12	-	Nanosecond
t AA	The address access time	-	12	Nanosecond
					t WC	Write cycle time	12	-	Nanosecond
t SA	Address Time Created	0	-	Nanosecond
					t PWE	Write pulse width	8	-	Nanosecond
t SD	Data are established to writes end	6	-	Nanosecond
					t HD	Write the data hold time after the end	0	-	Nanosecond

Table 11 SRAM memory read/write characteristic cycle time

The read cycle sequential of SRAM requires such as Fig. 8, and at A point place, MPC555 send access unit address, from then on read cycle begins to calculate, and at tRC after the time, the data of reading are really stable at data/address bus, so require after address signal is effective, chip selection signal CE is effective. If after address signal was effective, CE can not in time arrive significant level, then probably only data occur at internal data bus, and data can not be delivered on the data/address bus of system. After the C point, the output data become effectively, and as long as address signal and output allow signal OE not cancel, export so data and will remain valid always. In the whole read cycle, the WE signal should keep high level.

The write cycle time sequential of SRAM requires such as Fig. 9, when write cycle time begins, one sector address tSA Time Created is arranged first, at B point place, address signal is effective, at this moment, MPC555 puts chip selection signal CE and write signal WE is low level, for data writing, as long as when CE and WE are low level, data can be stablized and get final product. Write cycle time tWC be exactly the A point to the time between the D point, it the time address tSA Time Created, write pulse width tPWE and write operation tHD three's recovery time sum.

(3) special-purpose 72 needle sockets of automobile ECU

Special-purpose 72 needle sockets of automobile ECU of the utility model design configuration, for the application of automobile control provides the several functions interface, comprise that powered battery, analog quantity I/O, PWM output, digital quantity I/O, TPU function, serial communication, CAN bus are communicated by letter and to the support of dual-port RAM interface.

Provide the 24V power supply by the VBAT pin for system, can obtain 5V and 3.3V voltage through the electric power system circuit control device. The signals such as the accelerator pedal of automobile, brake pedal and the speed of a motor vehicle can be by the input of the analog quantity input pin among 72 needle sockets, analog-to-digital conversion module through control device will be converted to digital quantity with the analog input amount of getting on the car, and transfer to the MPC555 microprocessor and process. The analog quantitys such as water temperature control and motor speed control will be from the analog quantity output pin output of 72 needle sockets. Control device can also receive the digital input amounts such as Fuel Cell Engine switching value, emergency switch, R shelves, I shelves, II shelves, N shelves and hydrogen leakage, the digital outputs such as output water temperature temperature alarm, Ready signal. In addition, control device also provides 4 tunnel pwm signal output and the support of TPU function. As the control device of power assembly, need to communicate and transmission of control signals with other ECU continually, for this reason, we provide communication interface system in 72 needle sockets, comprise serial communication, the communication of CAN bus and to the support of dual-port RAM. The below will introduce the course of work of these three kinds of communications in detail.

Serial communication:

In the built-in queue-type serial multi-channel module (QSMCM:Queued Serial Multi-Channel Module) of MPC555, dual serial communication interface submodule (SCI:Serial Communication Interface) is arranged, communicate with other ECU by universal serial bus and ancillary equipment. In the process of control device by SCI output data, MPC555 delivers to data in the parallel data output register of SCI (TDR:Transmit Data Register), then being transferred to serial sends in the shift register (serial shifter), serial shift register becomes serial data with the method for displacement with parallel data, then the pin TxD[1:2 by MPC555] be sent to the MAX233AEWP interface chip, the function of MAX233AEWP is that Transistor-Transistor Logic level is converted to RS-232 mouth level, can link to each other with the computer serial ports, sampled data is sent to computer in real time so that monitoring.

When receiving the data of universal serial bus, at first make level conversion by the MAX233AEWP chip, data are from the RxD[1:2 of MPC555] the pin serial input is to receiving the shift register, receiving shift register and will arrive RxD[1:2] serial data of pin carries out shifting function, become parallel data and be sent in the parallel data input register (RDR:Receive Data Register), then be sent among the CPU.

Serial communication adopts asynchronous sending mode, after the transmission of putting SCI control register (SCCR) allows position (TE) for " 1 ", just begins process of transmitting. After the reception of putting the SCCR register allows position (RE) for " 1 ", will begin receive data. Data transmission format is 10 frame formats (without strange/even parity check position) of 1 start bit, 8 data bit and 1 position of rest. The baud rate of data transmission is 9600 bps.

The communication of CAN bus:

Because built-in two CAN bus control unit TouCAN modules so need not external CAN controller chip in our control device, only need to connect the interface chip PCA82C250 of CAN bus control unit in the MPC555 microprocessor. The function of PCA82C250 interface chip is to provide differential receiving ability to the CAN controller, provides differential transmitting capacity to the CAN bus. The TouCAN module provides four pins, and A_CNTX0 and B_CNTX0 are the transmitting terminal of serial data, and A_CNRX0 and B_CNRX0 are the serial data input. 16 message buffers are provided in each TouCAN module, and each message buffer has the sending and receiving dual-use function, also has in addition the dual serial data buffer zone in the TouCAN module, is responsible for respectively the sending and receiving of data. Can only activate one of them at one time.

When sending data, the TouCAN module is sent data into serial data and is sent buffering area from message buffer, send through A_CNTX0, B_CNTX0 pin, send to the TxD pin of PCA82C250 interface chip, the CANH pin of process PCA82C250 chip sends to data on the CAN bus from 72 pin interfaces. When receive data, data on the CAN bus send to A_CNRX0, the B_CNRX0 end of TouCAN through PCA82C250 interface chip RxD pin, receive message buffer by the Serial data receiving buffering area of TouCAN module.

The support of dual-port RAM interface:

Dual-port RAM interface provides 8 position datawire D0～D7, and 11 bit address line A21～A31 cooperate work with WR, CS and RD, realizes the data exchange of control device and other ECUs. The dual-port RAM of the compatible 2K of DPRAM interface and 1K, dual-port RAM write signal was effective when WR was low level, and when CS was low level, dual-port RAM chip selection signal was effective, and when RD was low level, dual-port RAM read signal was effective.

(4) control device technique effect

Compare with existing power system of electric automobile control device, concrete technique effect of the present utility model is embodied in, the employing of automobile-used 32 the embedded microprocessors of PowerPC structure of a new generation has improved the integrated level of system, vehicle-mounted reliability and systems technology performance. Design has increased the support of dual-port RAM interface in 72 pin automobile ECU private jacks, make control device both can also can pass through dual-port RAM interface by the CAN EBI, communicate and realize control with the ECU of each parts of electric automobile multiple-energy-source dynamical system. The application flexibility of control device, portability are brought up to a new height. The control device communications anti-jamming can raising and the quickening of computing control rate, the Optimized Operation of the power system of electric automobile distributed control network that makes multinode and interfacing level, multi-energy system with manage the control level and greatly improve.

The control device technique effect is to concrete experimental test scheme when:

That the motor vehicle integrated control system for whole vehicle of the hybrid power electric automobile of Dong Feng Auto Corporation adopts is microprocessor of 16 bit MC912DG128A, and its maximum operating frequency is 8MHz. Data/address bus is 16,2 groups of A/D conversion mouths, and every group of 8 passages, 4 PWM outputs need external CAN bus control unit, without outer extension memory. And adopt 32 automobile special microprocessor MPC555 based on the electric automobile multiple-energy-source Powertrain control device of MPC500 series microprocessor, the clock work frequency is 40MHz, 5 times of MC912DG128A microprocessor, improved the arithmetic speed of system, and MPC555 also has the double-precision floating point unit, can process complicated floating-point operation, the Optimized Operation of multi-energy system and the management control level of system are all greatly improved. Simultaneously, 32 data-bus width, so that the throughput ratio microprocessor of 16 bit of memory has increased by one times, owing to MPC555 is that MOTOLORA company is the special microprocessor that automotive development is produced, so its technical performance is very suitable for automobile power assembly ECU controller. It provides 2 32 tunnel A/D modular converter, totally 64 tunnel analog input channel, and the output of 8 road pwm signals, the TPU function, integrated CAN bus control unit TouCAN, it meets the CAN2.0B standard, and communication speed can reach 1Mbit/s. The design of control device circuit has been simplified in the raising of controller integrated level, also so that the control device operation is more stable and reliable. This control device has also extended out the FLASH of 2M byte and the SRAM of 2M byte, can satisfy the needs of software development memory space, real time operating systems such as the operation OSEK of Tsing-Hua University, μ C/OS-II and embedded LINUX etc. in this control device are no matter at memory space or this control device all can meet the demands on processing speed.

For control device communication system interface part, we adopt between three control device (A, B, C) testing program of carrying out data communication by the CAN bus mode to test. Three control device all move the embedded real time operating system of the OSEK of Tsing-Hua University, the transmission task of 7 CAN communications of control device A operation, each task will send data on the CAN bus, message transmission rate is 1Mbit/s, control device B, C operation reception task, receive the data that A passes from the CAN bus, the serial ports that is sent to PC by serial communication interface shows. Result of the test shows that this control device can be realized the CAN bus communication based on operating system, has strengthened communication capacity and reliability. In addition, the experimental prototype (THECU-2002) based on the electric automobile multiple-energy-source Powertrain control device of MPC500 microprocessor has passed through EMC test by national standard GB/T17619-1998. Be 20MHz～1000MHz in scan frequency, under the test field intensity 60V/m environment, this control device is working properly.

Claims (2)

1.MPC500 processor formula electric automobile multiple-energy-source Powertrain control device comprises microprocessor, it is characterized in that it also contains:

The core mainboard is made of following part:

The MPC500 microprocessor;

The following each several part that links to each other with this MPC500 microprocessor;

Pin type AN connector between circuit board, it comprises:

JP1: extend out the control bus interface;

JP2: extend out address bus, extend out data/address bus interface and power module interface;

JP3: time processing unit interface;

JP4: modulus translation interface and SPI;

JP5: pulsewidth modulation interface PWM, difunctional MIOS (modular input output system) interface, MIOS parallel input/output interface MPIO, 2 CAN (controller LAN) EBIs and 2 serial communication interfaces.

Also have: background debug mode port BDM;

Join serial interface chip and CAN interface chip that car is used with 72 needle connectors;

Outside FLASH;

Outside SRAM;

Latch the hardware reset control word switch that chip links to each other with this microprocessor MPC500 through data;

Crystal oscillator drives chip with the bus that is controlled by the hardware deploy switch;

In addition, also have power supply and reset chip.

For the I/O expansion board that the interface signal on the core mainboard is effectively expanded, it links to each other with the core mainboard by pin type AN connector JP1～JP5 between circuit board, and be equipped with special-purpose 72 needle sockets of automobile ECU (ECU), consisted of by following part:

Special-purpose 72 needle sockets of automobile ECU, it includes:

The electric power system interface: it with the foregoing circuit plate between among the JP2 of pin type AN connector the power module interface link to each other;

PWM and analog signal output interface: the PWM interface of PWM output interface and JP5 links to each other, and analog signal output interface links to each other through the PWM interface of high speed light lotus root and JP5;

Analog input interface: it with the foregoing circuit plate between among the JP4 of pin type AN connector the modulus translation interface link to each other;

Digital quantity I/O interface: it with the foregoing circuit plate between among the JP5 of pin type AN connector the parallel input/output interface MPIO of MIOS link to each other;

TPU (time processing unit) interface: it with the foregoing circuit plate between the JP3 of pin type AN connector link to each other;

Communication system interface, it comprises:

Serial communication interface: it with the foregoing circuit plate between among the JP5 of pin type AN connector serial communication interface link to each other;

The CAN communication interface: it with the foregoing circuit plate between among the JP5 of pin type AN connector the CAN EBI link to each other;

Dual-port RAM interface.

Data/address bus drives chip: it with the foregoing circuit plate between extend out the data/address bus interface among the JP2 of pin type AN connector and link to each other with above-mentioned dual-port RAM interface;

Address bus drives chip: it with the foregoing circuit plate between extend out address bus interface among the JP2 of pin type AN connector and link to each other with above-mentioned dual-port RAM interface;

The address decoding chip: it extends out among the JP1 of pin type AN connector and extends out the control bus interface among address bus interface, the JP1 and link to each other with above-mentioned dual-port RAM interface respectively with between the foregoing circuit plate.

2. MPC500 processor formula electric automobile multiple-energy-source Powertrain control device according to claim 1 is characterized in that, described hardware configuration control word switch includes:

Switch S1: totally 8, wherein

If the VPP position is set to one state, do the inner erasable operation of FLASH of MPC500 and program voltage;

The EPEE position is one state, and expression can be programmed and erasable FLASH;

MODCK[1:3] three: latch chip through data and drive, link to each other with MPC500, to dispose phaselocked loop (PLL)/clock operation pattern;

Switch S2, S3 and S4: each 8, latch chip by other three data respectively and link to each other with data/address bus, to realize hardware reset control;

Switch S5: totally 8, above-mentioned SRAM and FLASH are done sheet select.

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