The utility model content
The purpose of this utility model just provides a kind of three primary colors that can make and reaches the consistent primary colours apparatus for correcting based on digital light processing (DLP) Display Technique.
For achieving the above object, can realize, comprise three input latches that are used to make primary colours input signal and clock synchronization by following technical scheme; Three nonlinear gamma rectification modules that are used to correct DLP display unit optical characteristics; A full crossing operation that is used for input signal and output signal makes every kind of primary colours and complementary color all be transferred to consistent crossing operation module; Three are used for the display gray scale of DLP display unit is improved 2bit or the spatial diffusion module more than the 2bit; A synchronizing relay device that is used for the synchronizing signal delay process; A parity field parity line odd even pixel identification module; Three primary colors digital input signals input crossing operation module behind separately input latch, gamma rectification module wherein, the three primary colors digital input signals after the output of crossing operation module is handled is transported to the DLP display unit through spatial diffusion module separately; Synchronizing relay device one tunnel outputs to the Synchronization Control interface that the DLP display unit is used to show, another road outputs to parity field parity line odd even pixel identification module; The signal that parity field parity line odd even pixel identification module produces outputs to the control signal input port of spatial diffusion module.
The described gamma rectification module of the utility model device is made up of a two-port RAM and a gamma correction table writing controller, and color signal channel uses a port that is operated in reading mode, signal input link address line, and signal output connects data wire; Gamma correction table writing controller uses another to be operated in the port of WriteMode; The initial address that gamma correction table writing controller is set is 0, peripheral control unit is whenever write a complete gamma and is corrected data, then gamma correction table writing controller can these data of elder generation write two-port RAM, then the address is added 1, after having write whole addresses, the next operation cycle can reset to 0 again.
The described crossing operation module of the utility model device is made up of nine multipliers and three three port adders, it is one group that nine multipliers are divided into three, every group of multiplier inserts a kind of primary colour signal separately, and the output of each multiplier is cross connected to each adder according to the crossing operation rule in every group of multiplier.
After advantage of the present utility model is to adopt three primary colors crossing operation module, the colourity of every kind of primary colours can both be transferred to consistent with brightness, this can make in the assembly wall display system that a plurality of screens form each screen no matter when display color or white the colourity and the luminance deviation of its color all can reach the degree that human eye almost can't be differentiated, when the wall high-resolution pictures is put in order in demonstration, whole wall color height is consistent and bright-coloured sharp keen, can satisfy high-resolution fully and piece together the conforming requirement of wall display system color height.
Embodiment
As shown in Figure 1 and Figure 2, the utility model comprises three input latches that are used to make primary colours input signal and clock synchronization; Three nonlinear gamma rectification modules that are used to correct DLP display unit optical characteristics; A full crossing operation that is used for input signal and output signal makes every kind of primary colours and complementary color all be transferred to consistent crossing operation module; Three are used for the display gray scale of DLP display unit is improved 2bit or the spatial diffusion module more than the 2bit; A synchronizing relay device that is used for the synchronizing signal delay process; A parity field parity line odd even pixel identification module.
Wherein red digital input signals delivers to that input latch 1a, green digital input signals deliver to input latch 1b, blue digital input signals is delivered to input latch 1c, input latch makes all input signals and clock synchronization, overcome because of the inconsistent signal that causes of external transmission time-delay asynchronously, this can make image colored noise occur.
The gamma rectification module is made up of a two-port RAM and a gamma correction table writing controller, and color signal channel uses a port that is operated in reading mode, signal input link address line, and signal output connects data wire; Gamma correction table writing controller uses another to be operated in the port of WriteMode; The initial address that gamma correction table writing controller is set is 0, peripheral control unit is whenever write a complete gamma and is corrected data, then gamma correction table writing controller can these data of elder generation write two-port RAM, then the address is added 1, after having write whole addresses, the next operation cycle can reset to 0 again.Danger signal after latching enters that gamma rectification module 2a, the green after latching enter gamma rectification module 2b, the blue signal after latching enters gamma rectification module 2c, and the gamma rectification module is used to correct the non-linear of DLP display unit optical characteristics.Danger signal after gamma rectification module 2a corrects, the green after gamma rectification module 2b corrects and the blue signal after gamma rectification module 2c corrects are delivered to crossing operation module 3 respectively.
Crossing operation module 3 is made up of nine multipliers and three three port adders, it is one group that nine multipliers are divided into three, every group of multiplier inserts a kind of primary colour signal separately, and the output of each multiplier is cross connected to each adder according to the crossing operation rule in every group of multiplier.Crossing operation module 3 is the cores in this device, and input signal could really be realized the unanimity of primary colours tone through behind its full crossing operation, and the crossing operation rule of crossing operation module 3 can be represented (see figure 2) by following expression formula:
Red_out’=Red_in’*Reg_Krr+Green_in’*Reg_Kgr+Blue_in’*Reg_KbrGreen_out’=Green_in’*Reg_Kgg+Red_in’*Reg_Krg+Blue_in’*Reg_KbgBlue_out’=Blue_in’*Reg_Kbb+Red_in’*Reg_Krb+Green_in’*Reg_Kgb
The R-G-B signals of exporting after 3 computings of crossing operation module is delivered to spatial diffusion module 6a, 6b, 6c respectively.The spatial diffusion module is an adjusting unit with four or more picture element, after the signal of input carried out three-dimensional (two-dimensional space and one dimension time) diffusion, can make the gray level resolution of DLP display unit improve 2bit or more than the 2bit, can overcome GTG sudden change problem like this because of occurring in details in a play not acted out on stage, but told through dialogues after correcting through gamma.Signal after the diffusion of spatial diffusion module is delivered to the DLP display unit at last and is shown.
Line synchronizing signal Hsync_in, field sync signal Vsync_in and data useful signal DDE_in deliver to synchronizing relay device 7, after 7 time-delays of synchronizing relay device, deliver to the line synchronizing signal input port of DLP display unit respectively, field sync signal input port and data useful signal input port, the Synchronization Control that is used for the RGB data-signal, line synchronizing signal and field sync signal after 7 time-delays of synchronizing relay device delivered to parity field parity line odd even pixel identification module 10 simultaneously, the parity field signal that parity field parity line odd even pixel identification module 10 produces, parity line signal and odd even pixel signal are delivered to spatial diffusion module 6a simultaneously, 6b, 6c control spatial diffusion logic.
Line synchronizing signal, field sync signal and data useful signal are before through synchronizing relay device 7 and have the identity logic form afterwards, but life period is poor between the two, time difference between the two can be regulated by the value of regulating register, its unit is a clock cycle, and its value is identical with the time-delay of (time-delay from Red_in to Red_out, from Green_in to Green_out and from Blue_in to Blue_out equates) from Red_in to Red_out usually.
Parity field parity line odd even pixel identification module 10 has once promptly generated required parity field signal at the rising edge of each field sync signal with the negate of parity field signal, simultaneously the parity line signal is put 0, rising edge in each line synchronizing signal has once promptly generated required parity line signal with the negate of parity line signal, simultaneously the odd even pixel signal is put 0, the negate of odd even pixel signal signal has once promptly been generated required odd even pixel signal at the rising edge of each clock.
Be the structured flowchart of the utility model device specific embodiment as shown in Figure 3, the red input signal of 8bit is delivered to input latch 1a, the green input signal of 8bit is delivered to input latch 1b, the blue input signal of 8bit is delivered to input latch 1c, input latch makes all signals and clock synchronization, overcome because of the inconsistent signal that causes of external transmission time-delay asynchronous, input enables latch input signal when effective, otherwise latch signal is 0, this can be combined into primary colours and complementary color signal when the complete white resolution chart of input, be used for the adjusting of colour consistency.
Danger signal after latching enters 8 and advances 10 and go out gamma rectification module 2a, green after latching enters 8 and advances 10 and go out gamma rectification module 2b, blue signal after latching enters 8 and advances 10 and go out gamma rectification module 2c, the gamma rectification module is used to correct the non-linear of DLP display unit optical characteristics, the gamma rectification module by the gamma correction table write control module 9a, 9b, 9c is provided with.The 10bit danger signal of exporting behind gamma rectification module 2a is delivered to multiplier 3a, 4a, 4b respectively, the 10bit green of exporting behind gamma rectification module 2b is delivered to multiplier 3b, 4c, 4d respectively, and the 10bit blue signal of exporting behind gamma rectification module 2c is delivered to multiplier 3c, 4e, 4f respectively.
The value of 10bit danger signal that multiplier 3a will export behind gamma rectification module 2a and the 10bit red primary gain register Reg_Krr high 10bit that gets the result that multiplies each other delivers to adder 5a, 10bit danger signal that multiplier 4a will export behind gamma rectification module 2a and the red value to green gain register Reg_Krg of the 8bit high 8bit that gets the result that multiplies each other delivers to adder 5b, and 10bit danger signal that multiplier 4b will export behind gamma rectification module 2a and the red value to blue gain register Reg_Krb of the 8bit high 8bit that gets the result that multiplies each other delivers to adder 5c.The value of 10bit green that multiplier 3b will export behind gamma rectification module 2b and the 10bit green primary gain register Reg_Kgg high 10bit that gets the result that multiplies each other delivers to adder 5b, 10bit green that multiplier 4c will export behind gamma rectification module 2b and the green value to red gain register Reg_Kgr of the 8bit high 8bit that gets the result that multiplies each other delivers to adder 5a, and 10bit green that multiplier 4d will export behind gamma rectification module 2b and the green value to blue gain register Reg_Kgb of the 8bit high 8bit that gets the result that multiplies each other delivers to adder 5c.The value of 10bit blue signal that multiplier 3c will export behind gamma rectification module 2c and the 10bit blue primary gain register Reg_Kbb high 10bit that gets the result that multiplies each other delivers to adder 5c, the blue value to red gain register Reg_Kbr of the 10bit blue signal that multiplier 4e will export behind gamma rectification module 2c and the 8bit high 8bit that gets the result that multiplies each other delivers to adder 5a, and 10bit blue signal that multiplier 4f will export behind gamma rectification module 2c and 8bit indigo plant are delivered to adder 5b to the value of the green gain register Reg_Kbg high 8bit that gets the result that multiplies each other.
Deliver to spatial diffusion module 6a behind the 8bit signal plus of the 8bit signal of the 10bit signal that adder 5a exports multiplier 3a, multiplier 4c output and multiplier 4e output, deliver to spatial diffusion module 6b behind the 8bit signal plus of the 8bit signal of the 10bit signal that adder 5b exports multiplier 3b, multiplier 4a output and multiplier 4f output, deliver to spatial diffusion module 6c behind the 8bit signal of the 10bit signal that adder 5c exports multiplier 3c, multiplier 4b output and the 8bit signal plus that multiplier 4d exports.Adder 5a, 5b, 5c are the saturation limiting adder, if promptly result of calculation was less than 1023 o'clock output actual calculation results, if result of calculation is fixed as 1023 more than or equal to 1023 o'clock output results.
Space diffuse module 6a carries out the 10bit signal of adder 5a output to become the 8bit signal is delivered to the DLP display unit behind output buffer 11a red input port after three-dimensional (two-dimensional space and the one dimension time) diffusion; Space diffuse module 6b carries out the 10bit signal of adder 5b output to become the 8bit signal is delivered to the DLP display unit behind output buffer 11b green input port after three-dimensional (two-dimensional space and the one dimension time) diffusion, and space diffuse module 6c carries out the 10bit signal of adder 5c output to become the 8bit signal is delivered to the DLP display unit behind output buffer 11c blue input port after three-dimensional (two-dimensional space and the one dimension time) diffusion. RGB output enable register Reg_Eoutred, Reg_Eoutgreen, Reg_Eoutblue control the RGB output signal respectively, if certain output enable register is the signal of passage output after spatial diffusion of logical one then corresponding color, otherwise exports 0.
Line synchronizing signal Hsync_in, field sync signal Vsync_in and data useful signal DDE_in deliver to synchronizing relay device 7, after 7 time-delays of synchronizing relay device, deliver to the line synchronizing signal input port of DLP display unit respectively, field sync signal input port and data useful signal input port, the Synchronization Control that is used for the RGB data-signal, line synchronizing signal and field sync signal after 7 time-delays of synchronizing relay device delivered to parity field parity line odd even pixel identification module 10 simultaneously, the parity field signal that parity field parity line odd even pixel identification module 10 produces, parity line signal and odd even pixel signal are delivered to spatial diffusion module 6a simultaneously, 6b, 6c control spatial diffusion logic.
Register read writing module and register file 8 are interfaces of internal module and peripheral control unit, can be carried out the read-write register operation by peripheral control unit, and the value of register is used for inner each module of control simultaneously.
Concrete enforcement means for this device, can adopt the customization asic chip also can adopt FPGA, if exploitation and small lot batch manufacture can be adopted FPGA, if produce in enormous quantities, the logic that FPGA can be verified is transplanted in the asic chip of customization, can obtain the optimality price ratio like this.