CN2626131Y - Integrated circuit for step motor - Google Patents
Integrated circuit for step motor Download PDFInfo
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- CN2626131Y CN2626131Y CN 03231282 CN03231282U CN2626131Y CN 2626131 Y CN2626131 Y CN 2626131Y CN 03231282 CN03231282 CN 03231282 CN 03231282 U CN03231282 U CN 03231282U CN 2626131 Y CN2626131 Y CN 2626131Y
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Abstract
The utility model relates to a stepper motor integrated circuit, which comprises a first D trigger, a second D trigger, a third D trigger, the output signals of the first, second and third D trigger provide all the input signals to the first, second and third D trigger by the arrangement of a CMOS gate circuit. The stepper motor integrated circuit achieves single six beat positive rotating or reversed rotating function, and achieves circuit auto diaplasis and maintaining function by the arrangement of the CMOS gate circuit, thus increasing the output drive ability to drive the motor normal operation.
Description
Technical field
The utility model relates to a kind of integrated circuit, particularly a kind of stepping motor integrated circuit.
Background technology
The circuit of existing STEPPING MOTOR PULSE DISTRIBUTOR as shown in Figure 1, its major function designs for three-phase stepper motor pulse control, after cooperating three groups of suitable function drive circuits, can control two triple times or single six of three-phase stepper motor and clap forward or reverse.Yet this STEPPING MOTOR PULSE DISTRIBUTOR can not provide and automatically reset and keep function satisfying different demands, also can not provide enough output driving forces to run well to guarantee pushing motor simultaneously.
The utility model content
The purpose of this utility model is to provide a kind of stepping motor integrated circuit, and when realizing that motor list six is clapped the forward or reverse function, realization automatically resets and keeps function and increase its output driving force.
For achieving the above object, the utility model provides a kind of stepping motor integrated circuit, comprises first, second and third d type flip flop, it is characterized in that:
Its first clock pulse input terminal is through inverter and the inverter access first or the door of band protection; first clock allows end through Schmidt trigger access first or door; the second clock pulse input end is through inverter and the inverter access second or the door of band protection; the retentive control end inserts first NAND gate through the inverter of band protection; second clock allows end to insert first NAND gate through Schmidt trigger; the output access second or the door of first NAND gate; first or the door output with second or output insert second NAND gate; the output of this second NAND gate inserts first; the C clock pulse input terminal of second and third d type flip flop, the output of this second NAND gate inserts first through inverter; the XC clock pulse input terminal of second and third d type flip flop.
Its described first clock allows end through Schmidt trigger access first and door, the 3rd with the door, the 5th with the door, first clock allows end through Schmidt trigger and inverter access second and door, the 4th with the door, the 6th with the door, the output access first and the door of 3d flip-flop, the 4th with the door, the output access second and the door of second d type flip flop, the 5th with the door, the XQ output of first d type flip flop insert the 3rd with the door, the 6th with the door, first with the door output with second and output insert first NOR gate, the 3rd with the door output with the 4th with output insert second NOR gate, the 5th with the door output with the 6th with output insert the 3rd NOR gate, this first NOR gate, second NOR gate, the output of the 3rd NOR gate inserts first d type flip flop through inverter respectively, d type flip flop, the D input of 3d flip-flop.
The Q output of described first, second and third d type flip flop inserts the 3rd NAND gate, the output of the 3rd NAND gate insert first d type flip flop directly put 1 end XS, second d type flip flop directly put 0 end XR 3d flip-flop directly put 0 end XR.
The XQ output of described first d type flip flop, second d type flip flop and 3d flip-flop is respectively through the inverter place in circuit output of two inverters and band protection.
The utility model provides a kind of and realizes that single six clap the stepping motor integrated circuit of forward or reverse functions, by the setting of a cover CMOS gate circuit, can realize that circuit automatically resets and keeps function, and can increase the output driving force and run well with pushing motor.
Below in conjunction with accompanying drawing and embodiment the utility model is further described.
Description of drawings
Fig. 1 is the circuit interconnect pattern of prior art.
Fig. 2 is a circuit interconnect pattern of the present utility model.
Fig. 3 is a circuit working principle oscillogram of the present utility model.
Fig. 4 is a package outline drawing of the present utility model.
Embodiment
As shown in Figure 2, the utility model stepping motor integrated circuit comprises first d type flip flop 1, second d type flip flop 2,3d flip-flop 3, and provide each input signal of first, second, third d type flip flop 1,2,3 with the output signal of first, second, third d type flip flop 1,2,3 by a cover C MOS gate circuit setting.
The d type flip flop of CMOS is represented with symbol FF2 among Fig. 2; C MOS two input NAND gate are represented with symbol ON2; CMOS three input NAND gate are represented with symbol AN3; the CMOS inverter is represented with symbol 11,13; CMOS two inputs represent with symbol A1 that with door CMOS two input NOR gate represent that with symbol AN2 CMOS two inputs or door are represented with symbol A2; the cmos schmitt trigger represents that with symbol IP the inverter of CMOS band defencive function is represented with symbol IP2, IOB, OB.
The first clock pulse input terminal CL1 of the present utility model through the inverter IOB of band protection and an inverter 11 insert first or door 41, the first clocks allow end CN1 to insert first or door 41 through Schmidt trigger IP.Second clock pulse input end CL2 is through inverter IOB and an inverter 11 accesses second or the door 42 of band protection; retentive control end DL inserts first NAND gate 51 through the inverter IP2 of band protection; second clock allows end CN2 to insert the output access second or the door 42 of first NAND gate, 51, the first NAND gate 51 through Schmidt trigger IP.First or door 41 output insert second NAND gate 52 with second or 42 output.The output of this second NAND gate 52 inserts the, the C clock pulse input terminal of second and third d type flip flop 1,2,3, and the output of this second NAND gate 52 inserts the XC clock pulse input terminal of first, second and third d type flip flop 1,2,3 through inverter 11.
First clock allows end CN1 through Schmidt trigger IP access first and door the 61, the 3rd and door the 63, the 5th and door 65.First clock allows end CN1 through Schmidt trigger IP and inverter 11 accesses second and door the 62, the 4th and door the 64, the 6th and door 66.The XQ output of 3d flip-flop 3 insert first with the XQ output of door the 61, the 4th and door 64, the second d type flip flops 2 insert second with the XQ output of door the 62, the 5th and door 65, the first d type flip flops 1 insert the 3rd with door the 63, the 6th and door 66.First inserts first NOR gate 71 with door 61 output and second and 62 output, the 3rd inserts the 3rd NOR gate 73 with door 63 output and the 4th output that inserts second NOR gate 72, the five and door 65 with the output of door 64 and the 6th and 66 output.The output of this first NOR gate 71, second NOR gate 72, the 3rd NOR gate 73 inserts the D input of first d type flip flop 1, second d type flip flop 2,3d flip-flop 3 respectively through inverter 11.
The output that the Q output of first, second and third d type flip flop 1,2,3 inserts the 3rd NAND gate 53, the three NAND gate 53 insert first d type flip flop 1 directly put 1 end XS, second d type flip flop 2 directly put 0 end XR and 3d flip-flop 3 directly put 0 end XR.
The XQ output of first d type flip flop 1, second d type flip flop 2 and 3d flip-flop 3 is respectively through inverter OB place in circuit output QA, OB, the QC of two inverters 11,13 and band protection.
With " 1 " table high level, " 0 " table low level, then in the utility model when clock pulse input CL1 and CL2 are the rising edge pulse, the clock permission holds CN1 and CN2 must connect " 1 "; When clock pulse input CL1 and CL2 were the trailing edge pulse, clock allowed end CN1 and CN2 must connect " 0 ".Circuit working principle oscillogram of the present utility model as shown in Figure 3, the Q output of establishing initial condition and be first d type flip flop, second d type flip flop and 3d flip-flop is output as " 1 ", " 0 ", " 0 " successively, i.e. the A phase.
According to the utility model circuit connection Fig. 2 and in conjunction with CL1 shown in Figure 3, CL2, CN1, CN2 and DL waveform, analyze the utility model operation principle.Each circuit working point operating state shown in Figure 3 exemplifies following (D1, D2, D3 are respectively the D input signal of first, second, third d type flip flop, and Q1, Q2, Q3 and XQ1, XQ2, XQ3 are respectively the Q output signal and the XQ output signal of first, second, third d type flip flop):
L1 point operating state: when clock pulse CL1=" 0 ", CL2=" 1 ", CN1=" 1 ", CN2=" 1 ", DL=" 0 ", A=among Fig. 2 " 1 ", B=" 1 ", C1=" 0 ", D=" 0 ", E=" 1 ", F=" 1 ", G=" 1 ", H=" 1 ", I=" 0 ", J=" 1 ", K=" 0 ", C=" 0 ", XC=" 1 ", D1=" 1 ", D2=" 1 ", D3=" 0 ", because C=" 0 ", so the output of circuit maintains the original state, promptly QA=" 1 ", QB=" 0 ", QC=" 0 " are the A phase.
L2 point operating state: when clock pulse CL1=" 1 ", CL2=" 0 ", CN1=" 1 ", CN2=" 1 ", during DL=" 0 ", A=" 0 ", B=" 1 ", C 1=" 1 ", D=" 1 ", E=" 1 ", F=" 0 ", G=" 1 ", H=" 1 ", I=" 0 ", J=" 0 ", K=" 1 ", C=" 1 ", XC=" 0 ", because previous status Q1=" 1 ", XQ 1=" 0 ", Q2=" 0 ", XQ2=" 1 ", Q3=" 0 ", XQ3=" 1 ", so D1=" 1 ", D2=" 0 ", D3=" 1 ", circuit is output as QA=" 1 ", QB=" 0 ", QC=" 1 ", i.e. AC phase.
L3 point operating state: when clock pulse CL1=" 1 ", CL2=" 0 ", CN1=" 1 ", CN2=" 1 ", during DL=" 0 ", A=" 0 ", B=" 1 ", C1=" 1 ", D=" 1 ", E=" 1 ", F=" 0 ", G=" 1 ", H=" 1 ", I=" 0 ", J=" 0 ", K=" 1 ", C=" 1 ", XC=" 0 ", because previous status Q1=" 1 ", XQ1=" 0 ", Q2=" 0 ", XQ2=" 1 ", Q3=" 1 ", XQ3=" 0 ", so D1=" 0 ", D2=" 0 ", D3=" 1 ", circuit is output as QA=" 0 ", QB " 0 ",=QC " 1 ", i.e. C phase.
L4 point operating state: when clock pulse CL1=" 1 ", CL2=" 0 ", CN1=" 1 ", CN2=" 1 ", during DL=" 0 ", A=" 0 ", B=" 1 ", C1=" 1 ", D=" 1 ", E=" 1 ", F=" 0 ", G=" 1 ", H=" 1 ", I=" 0 ", J=" 0 ", K=" 1 ", C=" 1 ", XC=" 0 ", because previous status Q1=" 0 ", XQ1=" 1 ", Q2=" 0 ", XQ2=" 1 ", Q3=" 1 ", XQ3=" 0 ", so D1=" 0 ", D2=" 1 ", D3=" 1 ", circuit is output as QA=" 0 ", QB=" 1 ", QC=" 1 ", i.e. BC phase.
L5 point operating state: when clock pulse CL1=" 1 ", CL2=" 0 ", CN1=" 1 ", CN2=" 1 ", during DL=" 0 ", A=" 0 ", B=" 1 ", C1=" 1 ", D=" 1 ", E=" 1 ", F=" 0 ", G=" 1 ", H=" 1 ", I=" 0 ", J=" 0 ", K=" 1 ", C=" 1 ", XC=" 0 ", because previous status Q1=" 0 ", XQ1=" 1 ", Q2=" 1 ", XQ2=" 0 ", Q3=" 1 ", XQ3=" 0 ", so D1=" 0 ", D2=" 1 ", D3=" 0 ", circuit is output as QA=" 0 ", QB=" 1 ", QC=" 0 ", i.e. B phase.
L6 point operating state: when clock pulse CL1=" 1 ", C L2=" 0 ", CN1=" 1 ", CN2=" 1 ", during DL=" 0 ", A=" 0 ", B=" 1 ", C1=" 1 ", D=" 1 ", E=" 1 ", F=" 0 ", G=" 1 ", H=" 1 ", I=" 0 ", J=" 0 ", K=" 1 ", C=" 1 ", XC=" 0 ", because previous status Q 1=" 0 ", XQ 1=" 1 ", Q2=" 1 ", XQ2=" 0 ", Q3=" 0 ", XQ3=" 1 ", so D1=" 1 ", D2=" 1 ", D3=" 0 ", circuit is output as QA=" 1 ", QB=" 1 ", QC=" 0 ", i.e. AB phase.
L7 point operating state: when clock pulse CL1=" 1 ", CL2=" 0 ", CN1=" 1 ", CN2=" 1 ", during DL=" 0 ", A=" 0 ", B=" 1 ", C1=" 1 ", D=" 1 ", E=" 1 ", F=" 0 ", G=" 1 ", H=" 1 ", I=" 0 ", J=" 0 ", K=" 1 ", C=" 1 ", XC=" 0 ", because previous status Q1=" 1 ", XQ1=" 0 ", Q2=" 1 ", XQ2=" 0 ", Q3=" 0 ", XQ3=" 1 ", so D 1=" 1 ", D2=" 0 ", D3=" 0 ", circuit is output as QA=" 1 ", QB=" 0 ", QC=" 0 ", i.e. A phase.
……
L12 point operating state: as clock pulse CL1=" 1 " or CL1=" 0 ", CL2=" 0 " or CL2=" 1 ", CN 1=" 1 ", CN2=" 1 ", during DL=" 1 ", A=" 0 " or " 0 ", B=" 1 ", C1=" 1 " or " 0 ", D=" 1 " or " 0 ", E=" 1 ", F=" 0 " or " 1 ", G=" 0 ", H=" 1 ", I equals " 1 " all the time, J equals " 0 " all the time, K equals " 0 " all the time, C equals " 0 " all the time, XC equals " 1 " all the time, no matter what previous status is, keep original state without exception, previous status is shown in waveform: QA=" 0 ", QB=" 1 ", QC=" 1 ", to keep this state, till DL=" 0 " always.
……
L13 point operating state: when clock pulse CL1=" 0 ", CL2=" 1 ", CN1=" 0 ", CN2=" 0 ", during DL=" 0 ", A=" 1 ", B=" 0 ", C1=" 0 ", D=" 0 ", E=" 0 ", F=" 1 ", G=" 1 ", H=" 0 ", I=" 1 ", J=" 1 ", K=" 1 ", C=" 1 ", XC=" 0 ", because previous status Q1=" 0 ", XQ1=" 1 ", Q2=" 0 ", XQ2=" 1 ", Q3=" 1 ", XQ3=" 0 ", so D 1=" 1 ", D2=" 0 ", D3=" 1 ", circuit is output as QA=" 1 ", QB=" 0 ", QC=" 1 ", i.e. AC phase.
L14 point operating state: when clock pulse CL1=" 0 ", CL2=" 1 ", CN1=" 0 ", CN2=" 0 ", during DL=" 0 ", A=" 1 ", B=" 0 ", C1=" 0 ", D=" 0 ", E=" 0 ", F=" 1 ", G=" 1 ", H=" 0 ", I=" 1 ", J=" 1 ", K=" 1 ", C=" 1 ", XC=" 0 ", because previous status Q 1=" 1 ", XQ 1=" 0 ", Q2=" 0 ", XQ2=" 1 ", Q3=" 1 ", XQ3=" 0 ", so D 1=" 1 ", D2=" 0 ", D3=" 0 ", circuit is output as QA=" 1 ", QB=" 0 ", QC=" 0 ", i.e. A phase.
……
Thus, connect " 0 " when clock allows end CN1, CN2, when retentive control end DL connects " 0 ", add the clock pulse of clock pulse input terminal CL1, CL2, output QA of the present utility model, QB, QC state be for just changeing, i.e. A-AB-B-B C-C-AC-A.Connect " 1 " when clock allows end CN1, CN2, when retentive control end DL connects " 0 ", add the clock pulse of clock pulse input terminal CL1, CL2, output QA of the present utility model, QB, QC state are counter-rotating, i.e. A-CA-C-BC-B-AB-A.Thereby reach the purpose that rotates and reverse of stepping motor three-phase six-beat.
When allowing end CN1, CN2, clock connects " 1 ", when retentive control end DL connects " 1 ", no matter clock pulse input terminal CL1, CL2 are " 1 " still is " 0 ", the C clock pulse input terminal signal of d type flip flop 1,2,3 is always " 0 ", XC clock pulse input terminal signal is always " 1 ", so no matter what original state is, keeps original state without exception, till DL is " 0 ", thus the maintenance function of realization the utility model stepping motor integrated circuit.
In addition, when the output signal of the Q output of first, second and third d type flip flop 1,2,3 is " 1 ", its output signal after the 3rd NAND gate 53, export " 0 " signal to the first d type flip flop 1 directly put 1 end XS, second d type flip flop directly put 0 end XR and 3d flip-flop 3 directly put 0 end XR.Operation principle according to d type flip flop, the Q output of first, second and third d type flip flop 1,2,3 directly is output as " 1 ", " 0 ", " 0 " successively, it is the A phase, just when the Q of first, second and third d type flip flop 1,2,3 end output signal is followed successively by " 1 ", " 1 ", " 1 ", first, second and third d type flip flop 1,2,3 is automatically reset to initial condition.And no matter the Q of d type flip flop 1,2,3 end output signal is other free positions, and its output signal after NAND gate is always " 1 ", has guaranteed that first, second and third d type flip flop 1,2,3 can operate as normal.Thereby the utility model can be realized automatically reset function.
And, operation principle according to inverter, the level of the XQ output of first, second and third d type flip flop 1,2,3 output still keeps original level through twice after anti-phase, but its output current has increased, thereby the driving force of the utility model stepping motor integrated circuit is increased greatly, even former output current is increased to more than the 5mA by 300 μ A.
Schmidt trigger IP in the utility model is mainly used in the waveform shaping to circuit; Be with inverter IP2, IOB, the OB tool inverting function of protection, be mainly used in the protection of circuit input, output end signal.
Packaging appearance of the present utility model as shown in Figure 4, its leading foot is 14 pin, adopts the DIP14 encapsulation.
Claims (3)
1, a kind of stepping motor integrated circuit comprises first, second and third d type flip flop (1), (2), (3), it is characterized in that:
Its first clock pulse input terminal C L 1 is through inverter IOB and an inverter (11) access first or the door (41) of band protection, first clock allows end CN1 through Schmidt trigger IP access first or door (41), second clock pulse input end CL2 is through inverter IOB and an inverter (11) access second or the door (42) of band protection, retentive control end DL inserts first NAND gate (51) through the inverter IP2 of band protection, second clock allows end CN2 to insert first NAND gate (51) through Schmidt trigger IP, the output access second or the door (42) of first NAND gate (51), first or the output of door (41) with second or the output of (42) insert second NAND gate (52), the output of this second NAND gate (52) inserts first, second and third d type flip flop (1), (2), (3) C clock pulse input terminal, the output of this second NAND gate (52) inserts first through inverter (11), second and third d type flip flop (1), (2), (3) XC clock pulse input terminal;
Its described first clock allows end CN 1 through Schmidt trigger IP access first and door (61), the 3rd with the door (63), the 5th with the door (65), first clock allows end CN1 through Schmidt trigger IP and inverter (11) access second and door (62), the 4th with the door (64), the 6th with the door (66), the XQ output access first and the door (61) of 3d flip-flop (3), the 4th with the door (64), the XQ output access second and the door (62) of second d type flip flop (2), the 5th with the door (65), the XQ output of first d type flip flop (1) insert the 3rd with the door (63), the 6th with the door (66), first with the output of door (61) with second and the output of (62) insert first NOR gate (71), the 3rd inserts second NOR gate (72) with the 4th with the output of (64) with the output of door (63), the 5th inserts three NOR gate (73), this first NOR gate (71) with the 6th with the output of (66) with the output of door (65), second NOR gate (72), the output of the 3rd NOR gate (73) inserts first d type flip flop (1) through inverter (11) respectively, second d type flip flop (2), the D input of 3d flip-flop (3).
2, stepping motor integrated circuit according to claim 1, it is characterized in that: the Q output of described first, second and third d type flip flop (1), (2), (3) inserts the 3rd NAND gate (53), the output of the 3rd NAND gate (53) insert first d type flip flop (1) directly put 1 end XS, second d type flip flop (2) directly put 0 end XR and 3d flip-flop (3) directly put 0 end XR.
3, stepping motor integrated circuit according to claim 1 and 2 is characterized in that: inverter OB place in circuit output QA, OB, QC that the XQ output of described first d type flip flop (1), second d type flip flop (2) and 3d flip-flop (3) is protected through two inverters (11), (13) and band respectively.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 03231282 CN2626131Y (en) | 2003-05-20 | 2003-05-20 | Integrated circuit for step motor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 03231282 CN2626131Y (en) | 2003-05-20 | 2003-05-20 | Integrated circuit for step motor |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN2626131Y true CN2626131Y (en) | 2004-07-14 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 03231282 Expired - Fee Related CN2626131Y (en) | 2003-05-20 | 2003-05-20 | Integrated circuit for step motor |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN2626131Y (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101860183A (en) * | 2010-06-03 | 2010-10-13 | 大连嘉禾工业控制技术有限公司 | Self-adaptive trigger circuit of three-phase electric dust-removing power supply |
| CN107370441A (en) * | 2017-07-24 | 2017-11-21 | 郝熠哲 | A kind of method of the logic circuit of the operation of control stepping motor three-phase six |
-
2003
- 2003-05-20 CN CN 03231282 patent/CN2626131Y/en not_active Expired - Fee Related
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101860183A (en) * | 2010-06-03 | 2010-10-13 | 大连嘉禾工业控制技术有限公司 | Self-adaptive trigger circuit of three-phase electric dust-removing power supply |
| CN107370441A (en) * | 2017-07-24 | 2017-11-21 | 郝熠哲 | A kind of method of the logic circuit of the operation of control stepping motor three-phase six |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| C17 | Cessation of patent right | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20040714 Termination date: 20110520 |