CN2616432Y - Driving recording instrument - Google Patents

Abstract

The utility model relates to an automobile driving recording instrument (an automobile black box), belonging to a field of automobile electronic application. The utility model is characterized in that the utility model comprises a socket of a data input port 1, a housing 2, a socket of the data output port 3, a microprocessor U1 for data acquisition and processing, a microprocessor U2 for data compression and storing, two latches U3 and U4, a dual port RAM U5, a data saving chip U6, two mirror image memory U7 and U8 and a bus transceiver U9. The data input port 1 is connected with the pins P10 to P17 of the chip U1P1 port, the P00 to P07 of the P0 port of the U1 are directly connected with the left data line D0 to D7 of U5 and the data line I/O0 to I/O7 of U6, and are connected with the D0 to D7 of U3.

Description

Drive recorder

Technical field: the utility model belongs to the vehicle electronics application, is specially running recording instrument (automobile black box).

Background technology: existing various drive recorders, be merely able to store individual event or several driving data, and several item numbers of this minority are according to the foundation that is not enough to as accident causation evaluation, auto vendor's follow-up of product quality and authentication and raising auto trade level of management.In addition, the data of will driving a vehicle are used for that accident causation is identified and during purposes such as follow-up of product quality, require the driving data must be accurately, failure-free, this has just proposed the extreme high reliability requirement to whole vehicle-running recording system.

Summary of the invention: the purpose of this utility model is a kind of driving recording instrument of design-calculated for the storing reproduction problem that solves various data in the vehicle driving process.The alarm message that it takes place in the operations of different periods and status information (as the speed of a motor vehicle, rotating speed, steering indicating light, braking, country beam, fog lamp, reversing, car door opening etc.) and the vehicle driving process in can the store car driving process (as index overruns such as the speed of a motor vehicle, rotating speed, water temperature, oil pressure, air pressure I, air pressure II, oil strainer, fuel filter, water level, storehouse temperature, Battery voltage, oil masses time warning).When needing to use the driving data, can resolve the running information that software is understood storage, reproduce the data in the vehicle driving process by special use.The driving data class of the utility model storage is complete, also have simultaneously the reliability height, simple in structure, with low cost, manipulate safe and reliable.The purpose of this utility model is achieved in that data-in port 1 links to each other with the P10～P17 pin of chip U1P1 mouth, P00～the P07 of the P0 mouth of U1 directly links to each other with left data line D0～D7 of U5 and data line I/O0～I/O7 of U6, P00～the P07 of P0 mouth also links to each other with D0～D7 of U3 simultaneously, output line Q0～Q7 by U3 links to each other respectively with left side A wire A0～A7 of U5 and A wire A0～A7 of U6 then, P20～the P23 of U1 chip P2 mouth directly links to each other with left side A wire A8～A10 of U5 and A wire A8～A10 of U6, the RD of U1 chip, WR, P23 and P24 respectively with the OEL of U5, RWL, CEL and BUSYL direct connection, the RD of U1 chip, WR, P26 and P27 respectively with the OE of U6, WE, RDY and CE direct connection, P00～the P07 of the P0 mouth of U2 directly links to each other with right data line DR0～DR7 of U5, P00～the P07 of P0 mouth also links to each other with D0～D7 of U4 simultaneously, output line Q0～Q7 by U4 links to each other with the right A wire AR0～AR7 of U5 then, P20～the P23 of U2 chip P2 mouth directly links to each other with the right A wire AR8～AR10 of U5, the RD of U2 chip, WR, P23 and P24 respectively with the OER of U5 chip, RWR, CER and BUSYR direct connection, the EA/VP pin of chip U1 and U2 connects high level, 1 and the X2 pin of chip U1 and U2 be external crystal oscillator CY1 and CY2 respectively, the R1OUT of chip U9 links to each other with the TXD pin with the RXD of chip U2 respectively with T1IN, RXDPC links to each other with data-out port socket 3 respectively with TXDPC, the SDA2 of chip U8 links to each other with P13 with the P12 of chip U2 with SCL2, and the SDA1 of chip U7 links to each other with P11 with the P10 of chip U2 with SCL1.The utility model advantage is: the utility model interface is followed the standard of national Automobile Electronic Industry, and data acquisition interface both can be connected with standard private bus on the automobile, can be connected with supporting with it data acquisition unit again.Can store 50 kinds of different running informations.But vehicle was exercised situation in the nearest 48-288 of the utility model continuous record hour, can carry out record to nearest 5 years accidents, and alert data can be preserved 10 years.Failure free time of the present utility model reached more than 10000 hours, fault from recovery time less than 1 second.The utility model is easy for operation, safe and reliable.

Description of drawings: Fig. 1 is the utility model panel construction principle schematic; Fig. 2 is the utility model quantitative data input and microcontroller circuit schematic diagram; Fig. 3 (a) is the utility model data output unit schematic circuit diagram; Fig. 3 (b) is the utility model mirroring memory U8 schematic circuit diagram; Fig. 3 (c) is the utility model mirroring memory U7 schematic circuit diagram.

The specific embodiment: data-in port 1 links to each other with the P10～P17 pin of chip U1P1 mouth, P00～the P07 of the P0 mouth of U1 directly links to each other with left data line D0～D7 of U5 and data line I/O0～I/O7 of U6, P00～the P07 of P0 mouth also links to each other with D0～D7 of U3 simultaneously, output line Q0～Q7 by U3 links to each other respectively with left side A wire A0～A7 of U5 and A wire A0～A7 of U6 then, P20～the P23 of U1 chip P2 mouth directly links to each other with left side A wire A8～A10 of U5 and A wire A8～A10 of U6, the RD of U1 chip, WR, P23 and P24 respectively with the OEL of U5, RWL, CEL and BUSYL direct connection, the RD of U1 chip, WR, P26 and P27 respectively with the OE of U6, WE, RDY and CE direct connection, P00～the P07 of the P0 mouth of U2 directly links to each other with right data line DR0～DR7 of U5, P00～the P07 of P0 mouth also links to each other with D0～D7 of U4 simultaneously, output line Q0～Q7 by U4 links to each other with the right A wire AR0～AR7 of U5 then, P20～the P23 of U2 chip P2 mouth directly links to each other with the right A wire AR8～AR10 of U5, the RD of U2 chip, WR, P23 and P24 respectively with the OER of U5 chip, RWR, CER and BUSYR direct connection, the EA/VP pin of chip U1 and U2 connects high level, the X1 of chip U1 and U2 and X2 pin be external crystal oscillator CY1 and CY2 respectively, the R1OUT of chip U9 but links to each other with the TXD pin with the RXD of microprocessor U2 respectively with T1IN, RXDPC links to each other with data-out port socket 3 respectively with TXDPC, the SDA2 of chip U8 links to each other with P13 with the P12 of microprocessor U2 with SCL2, and the SDA1 of chip U7 links to each other with P11 with the P10 of microprocessor U2 with SCL1.Working process of the present utility model: with chip U1 the drive a vehicle collection and the work of treatment of data.Use the drive a vehicle uplink work of compression, storage and data of data of chip U2.Chip U1 and U2 use the 89C58 microprocessor, and U3 and U4 are two latch, and its model is 74LS373.U5 is a slice dual port RAM, and its model is IDT132.U6 is a slice EEPROM, can preserve data when system's accident power down.The driving data link to each other with the P10～P17 pin of chip U1P1 mouth through 1 input of data-in port socket.The P0 mouth of U1 is data/address multiplex line, and when using as data line, the P00～P07 of P0 mouth directly links to each other with left data line D0～D7 of U5 and data line I/O0～I/O7 of U6; When using as A wire, the P00 of P0 mouth～P07 links to each other with D0～D7 of U3 earlier, and the output line Q0～Q7 by U3 links to each other respectively with left side A wire A0～A7 of U5 and A wire A0～A7 of U6 then.P20～the P23 of U1 chip P2 mouth directly links to each other with left side A wire A8～A10 of U5 and A wire A8～A10 of U6.The RD of U1 chip, WR, P23 and P24 respectively with OEL, RWL, CEL and the BUSYL direct connection of U5, carry out reading and writing, sheet choosing and the control of data access conflict arbitration.The RD of U1 chip, WR, P26 and P27 respectively with OE, WE, RDY and the CE direct connection of U6, carry out reading and writing, inquiry and sheet selected control system.The P0 mouth of U2 is data/address multiplex line, and when using as data line, the P00～P07 of P0 mouth directly links to each other with right data line DR0～DR7 of U5; When using as A wire, the P00 of P0 mouth～P07 links to each other with D0～D7 of U4 earlier, and the output line Q0～Q7 by U4 links to each other with the right A wire AR0～AR7 of U5 then.P20～the P23 of U2 chip P2 mouth directly links to each other with the right A wire AR8～AR10 of U5.The RD of U2 chip, WR, P23 and P24 respectively with OER, RWR, CER and the BUSYR direct connection of U5 chip, carry out reading and writing, sheet choosing and the control of data access conflict arbitration.Chip U1 and U2 do not need Add-In ROM, so the EA/VP pin connects high level.The X1 of chip U1 and U2 and X2 pin be external crystal oscillator CY1 and CY2 respectively, needed clock frequency when chip operation is provided.Chip U7 and U8 are serial i 2C nonvolatile memory FLASH, are used for the storage line car data.U9 is a bus transceiver, and its model is MAX232CPE, is used for communicating with computing machine.The R1OUT of chip U9 but links to each other with the TXD pin with the RXD of chip U2 respectively with T1IN, and RXDPC links to each other with data-out port respectively with TXDPC, is used for the driving data are reached PC by serial port RS232.The SDA2 of chip U8 links to each other with P13 with the P12 of micro controller system U2 with SCL2.The SDA1 of chip U7 links to each other with P11 with the P10 of micro controller system U2 with SCL1.U7 and U8 are a pair of mirroring memories.Treater U1 gathers the driving data and also carries out after the corresponding data handing, with data storage in dual port RAM U5 and EEPROMU6.Treater U2 will be stored in after data among the U5 compress, and timesharing is stored among U7 and the U8.Storage data content among U7 and the U8 is in full accord, is mainly used in the double copies of realizing the driving data.

Claims (1)

1, a kind of drive recorder, it comprises data-in port socket 1, housing 2, data-out port socket 3, data acquisition and processing (DAP) microprocessor U1, data compression and storage microprocessor U2, latch U3 and U4, dual port RAM U5, preserve data chip U6, mirroring memory U7 and U8, bus transceiver U9, it is characterized in that: data-in port 1 links to each other with the P10～P17 pin of chip U1P1 mouth, P00～the P07 of the P0 mouth of U1 directly links to each other with left data line D0～D7 of U5 and data line I/O0～I/O7 of U6, P00～the P07 of P0 mouth also links to each other with D0～D7 of U3 simultaneously, output line Q0～Q7 by U3 links to each other respectively with left side A wire A0～A7 of U5 and A wire A0～A7 of U6 then, P20～the P23 of U1 chip P2 mouth directly links to each other with left side A wire A8～A10 of U5 and A wire A8～A10 of U6, the RD of U1 chip, WR, P23 and P24 respectively with the OEL of U5, RWL, CEL and BUSYL direct connection, the RD of U1 chip, WR, P26 and P27 respectively with the OE of U6, WE, RDY and CE direct connection, P00～the P07 of the P0 mouth of U2 directly links to each other with right data line DR0～DR7 of U5, P00～the P07 of P0 mouth also links to each other with D0～D7 of U4 simultaneously, output line Q0～Q7 by U4 links to each other with the right A wire AR0～AR7 of U5 then, P20～the P23 of U2 chip P2 mouth directly links to each other with the right A wire AR8～AR10 of U5, the RD of U2 chip, WR, P23 and P24 respectively with the OER of U5 chip, RWR, CER and BUSYR direct connection, the EA/VP pin of chip U1 and U2 connects high level, the X1 of chip U1 and U2 and X2 pin be external crystal oscillator CY1 and CY2 respectively, the R1OUT of chip U9 links to each other with the TXD pin with the RXD of microprocessor U2 respectively with T1IN, RXDPC links to each other with data-out port socket 3 respectively with TXDPC, the SDA2 of chip U8 links to each other with P13 with the P12 of microprocessor U2 with SCL2, and the SDA1 of chip U7 links to each other with P11 with the P10 of microprocessor U2 with SCL1.

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