CN2615770Y - Electric circuit for testing read-only memory - Google Patents
Electric circuit for testing read-only memory Download PDFInfo
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- CN2615770Y CN2615770Y CN 03231629 CN03231629U CN2615770Y CN 2615770 Y CN2615770 Y CN 2615770Y CN 03231629 CN03231629 CN 03231629 CN 03231629 U CN03231629 U CN 03231629U CN 2615770 Y CN2615770 Y CN 2615770Y
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Abstract
The utility model relates to a circuit which is used to test read only memory. Control a signal port (2) via read only memory and read signals from read only memory via a control circuit (3). A data operational circuit (4) and an output circuit (5) of the read only memory test the read only memory (1) and estimate test result output data to test a curing COS data (chip operating system)in the read only memory (1). The safe use of the integrated circuit card is ensured.
Description
Technical field
The utility model relates to the integrated circuit card field, relates in particular to a kind of circuit of testing ROM (read-only memory).
Background technology
Various types of memory is widely used in integrated circuit (IC) card.Basic demand to storer is high precision, high capacity, low-power consumption.By the function branch, storer can be divided into random access memory (RAM) and ROM (read-only memory) (ROM).ROM (read-only memory) can be divided into two big classes again, masking film program ROM and programming ROM (Programmable Read-Only Memory).The ROM of masking film program, the fixed logic information of its storage is to be passed through by manufacturer, carves mask and decides.It is that structure is the simplest a kind of in the storer.Its data write the back and just can not change at any time with simple and rapidly method.Therefore, the data of its storage are changeless when operate as normal, can only read, and can not write, and are referred to as ROM (read-only memory).Usually, ROM is used as program storage.
Developed the operating system of using therein on the IC-card of band CPU, isolated with the technology of using relevant problem and IC-card in order to make, operating system be usually by should being used for dividing catalogue with constituent act, and with the visit of cryptoguard to them.Differentiate mutually in earnest, can increase and change the dedicated functions that each is used easily, realize one card for multiple uses veritably.
In the IC-card of band CPU, ROM is the carrier as chip operating system COS (Chip OperationSystem) program code.Therefore, whether the COS data of solidifying in the checking R OM correctly are very important.
Summary of the invention
Whether correct the utility model technical issues that need to address have provided a kind of circuit of testing ROM (read-only memory), be intended to separate the COS data of solidifying in must not checking R OM defective.
In order to solve the problems of the technologies described above, the utility model is achieved through the following technical solutions:
Circuit of the present utility model comprises: ROM (read-only memory), and ROM (read-only memory) control signal end is read the control circuit of ROM (read-only memory) signal, ROM data computing circuit, output circuit; Described ROM (read-only memory) control signal end is connected with the input end of the control circuit of reading the ROM (read-only memory) signal, the first input end of ROM data computing circuit, the first input end of output circuit; The described output terminal of reading the control circuit of ROM (read-only memory) signal outputs to the read control signal of ROM (read-only memory) the input end of described ROM (read-only memory); The output terminal of described ROM (read-only memory) outputs to the data of ROM (read-only memory) second input end of ROM data computing circuit; The output terminal of ROM data computing circuit outputs to the arithmetic operation number second input end of described output circuit; Output circuit is with the data output of test result.
Compared with prior art, the beneficial effects of the utility model are: whether correct by the COS data of solidifying in the checking R OM, guaranteed the safe handling of IC-card.
Description of drawings
Fig. 1 is the block scheme of the circuit of test ROM (read-only memory);
Fig. 2 is a block scheme of reading the control circuit of ROM (read-only memory) signal;
Fig. 3 is the block scheme of ROM data computing circuit;
Fig. 4 is the circuit diagram of ROM data computing circuit;
Fig. 5 is the block scheme of output circuit;
Fig. 6 is the workflow diagram of test ROM (read-only memory) method;
Fig. 7 is the operational flowchart in the ROM data computing circuit;
Fig. 8 is the sequential chart of test ROM (read-only memory).
Wherein: ROM (read-only memory) 1, ROM (read-only memory) control signal end 2 is read the control circuit 3 of ROM (read-only memory) signal, ROM data computing circuit 4, output circuit 5, address register 31, first MUX 32, first trigger 33, clock 34 is with computing, XOR circuit 41 condenses, shift operation circuit 42, XOR circuit 43, the second MUX 52, the second triggers 53.
Embodiment
Below in conjunction with accompanying drawing and embodiment the utility model is described in further detail:
RomTstEn is a control signal, and RomTstRd is the read control signal of ROM, and RomData is the data of reading from ROM, and SigAna is the arithmetic operation number of testing algorithm, and RomTstOut is the data outputs, SigAna[0] be several the 0th data of arithmetic operation.
By Fig. 1, Fig. 2, Fig. 3, Fig. 5 as seen: circuit of the present utility model comprises: ROM (read-only memory) 1, and ROM (read-only memory) control signal end 2 is read the control circuit 3 of ROM (read-only memory) signal, ROM data computing circuit 4, output circuit 5; Described ROM (read-only memory) control signal end 2 is connected with the input end of the control circuit 3 of reading the ROM (read-only memory) signal, the first input end of ROM data computing circuit 4, the first input end of output circuit 5; The described output terminal of reading the control circuit 3 of ROM (read-only memory) signal outputs to the read control signal of ROM (read-only memory) the input end of described ROM (read-only memory) 1; The output terminal of described ROM (read-only memory) 1 outputs to the data of ROM (read-only memory) second input end of ROM data computing circuit 4; The output terminal of ROM data computing circuit 4 outputs to the arithmetic operation number second input end of described output circuit 5; Output circuit 5 is with the data output of test result;
The described control circuit 3 of reading the ROM (read-only memory) signal comprises address register 31, the first MUX 32, the first triggers 33, clock 34; Described address register 31 is connected with first, second input end of first MUX 32 respectively with ROM (read-only memory) control signal end 2; The output terminal of described clock 34 and MUX 32 is connected with first, second input end of trigger 33 respectively, and the output terminal of described trigger 33 is connected with the input end of ROM (read-only memory) 1, with the read signal of CROM (control read only memory) 1;
Described ROM data computing circuit 4 comprises clock 34, with computing, the XOR circuit 41 that condenses, shift operation circuit 42, XOR circuit 43; Described and computing, the XOR circuit 41 that condenses are several the 16th circuit that formed by the XOR that condensed after the arithmetic operation number of a last clock period and computing seed number and the operation of arithmetic operation; Described shift operation circuit 42 be the 9th to the 15th by several the 10th circuit that form to the 16th bit shift of the arithmetic operation of a last clock period; Described XOR circuit 43 be the 1st to the 8th be the arithmetic operation of a last clock period several the 2nd to the 9th with current ROM in the data circuit that forms of XOR mutually; Described and computing, the XOR circuit 41 that condenses, shift operation circuit 42, XOR circuit 43 under the control of clock 34 and ROM (read-only memory) control signal end 2, output arithmetic operation number;
Described output circuit 5 comprises address register 31, the second MUX 52, the second triggers 53, clock 34; Described address register 31 is connected with second MUX, 52 input ends; Described second MUX, 52 output terminals are connected with the first input end of second trigger 53, described ROM (read-only memory) control signal end 2 is connected with second input end of second trigger 53, described clock 34 is connected with the 3rd input end of second trigger 53, with the control data output that arithmetic operation is several the 0th;
Described address register 31 is address registers of 15;
As seen from Figure 4: the logical operation circuit of forming by a plurality of components and parts, to realize logical operation.
By Fig. 6, Fig. 7 as seen: method of the present utility model realizes by following steps:
Become " 1 ' b1 " by ROM (read-only memory) control signal end by " 1 ' b0 ", to enter the step 41 of test pattern;
Automatically add 1 step 42 by the address register in the control circuit of reading the ROM (read-only memory) signal;
By reading the step 43 of data in the ROM (read-only memory);
By the calculation step in the ROM data computing circuit 44;
By the last position in the compare address register is " 1 ' b0 " or " 1 ' b1 ", to differentiate output arithmetic operation several 45 or to get back to step 42;
By the binary number of 16 of serial outputs, to differentiate the correct step 46 of data in the ROM (read-only memory).
Describedly count SigAna=SigAna[15 by the arithmetic operation in the calculation step 44 in the ROM data computing circuit] nSigAna[14:8] nSigAna[7:0] n is made up of three parts, realizes by following steps:
SigAna[15]n＝^(SigAnan1?&SigSeed)441
SigAna[14：8]n＝SigAna[15：9]n-1442
SigAna[7：0]n＝SigAna[8：1]n-1^RomData?443
Several the 16th SigAna[15 of described arithmetic operation] n was that the arithmetic operation of a last clock period is counted SigAnan-1 and computing seed number SigSeed and operation (sign of operation is “ ﹠amp; ") XOR that condenses afterwards (sign of operation is " ^ ") forms; The 9th to the 15th SigAna[14:8] n was several the 10th to the 16th SigAna[15:9 of arithmetic operation of a last clock period] the n-1 displacement forms; The 1st to the 8th SigAna[7:0] n was several the 2nd to the 9th SigAna[8:1 of arithmetic operation of a last clock period] data RomData among n-1 and the current ROM value that obtains of XOR (sign of operation is " ") mutually.The numerical value that wherein comprises the data represented present clock period of subscript n comprises the numerical value of a data represented last clock period of subscript n-1.
Described 16 binary arithmetic operations are counted SigAna when original state, are ' 16 ' b0 ';
Described computing seed number SigSeed is ' 16 ' b0110 1,000 0,000 0001 ';
As seen from Figure 8: at test period, RomTstEn keeps high level, RomTstOut sends and opens the beginning position and begin to export by turn SigAna at next cycle when measuring 3FFF, when output SigAna, RomTstRd transfers high level to, RomTstOut transfers high level automatically to after output is finished, and has so just finished the process of test data output.
Below principle of the present utility model is described as follows:
The utility model can be divided into three parts according to function: at first be the control circuit 3 of reading the ROM signal, major function is to make the read signal RomTstRd of ROM1 effective when self-test begins, and stops to continue to read ROM1 after all data participation computings of ROM1; Next is a ROM data computing circuit 4, and each data of ROM1 participate in the computing of self-test here according to certain algorithm, produce 16 check code at last; Be the output circuit 5 of operation result at last, major function is the check code result of 16 of serial outputs.Three parts are worked under the driving of clock, can be reliably and finish the test of all data among ROM1 fast.
The control circuit 3 of reading the ROM (read-only memory) signal comprises address register 31, is used for controlling the address of ROM1.After the value computing of an address finished, address register 31 added one automatically.Default 15 of address register 31 Duo one than the ROM1 address, therefore when the most significant digit of address register 31 (RomTestA[14]) during by 0 change 1, represents that the computing of all addresses finishes, and can export the result.When ROM1 tested, control signal RomTstEn put high level, and this moment, address register 31 began to increase progressively.
At the ROM test period, send a read control signal RomTstRd, data in illustrating during this period among the computing ROM1, this signal low level is effective, most significant digit RomTestA[14 when control signal RomTstEn=' 1 ' and address register 31]=read control signal RomTstRd bottom set level when two conditions in ' 0 ' satisfy simultaneously, other cycle is a high level.
RomTstOut is used to export calculated result, and it keeps high level usually, and a start bit is sent in test when finishing, and with 16 clock period output results, output finishes and transfers high level to then.This process is by control signal RomTstEn and address register 31 controls, RomTstEn is effective at whole ROM1 test period, low 14 of address register 31 is the address of calculating, when calculating last address of ROM1 " 3FFF " h, make RomTstOut jump the low start bit of sending, " 4000 " h outputs test result to these 16 clock period serials of " 400F " h in the address, becomes high level then.
When control signal RomTstEn became 1 ' b1 by 1 ' b0, the CPU card had entered the pattern of ROM data test, and the address wire of ROM and control signal transfer to by circuit of the present utility model to be provided.
After data are read, participate in computing.Comprise a computing seed number SigSeed in the algorithm, the computing seed number choose and algorithm itself can make the data among the ROM1 no matter what kind of mistake takes place, all can produce as much as possible and the correct different result of 16 bit check sign indicating numbers.The essence of algorithm is by increasing the amount of redundancy of data, producing check code.If whether check data is correct, only need to adopt identical checking algorithm, judge whether the check code that obtains is identical.
The capacity of ROM1 is 16K, but the check code that obtains at last has only 16, and containing all possibilities of makeing mistakes of ROM1 among 16 bit digital can't realize.But under 90% the situation, be to have only one or several data to make mistakes among the ROM1, and be not the data generation mistake of bulk.In this algorithm, this problem has been considered in just choosing of S1gSeed.SigSeed cooperates with algorithm, can contain the error in data of 90% ROM1 that may occur.Make wrong reflection to some extent in 16 check code as much as possible, reach the efficient of the ROM1 self-test of optimum.False Rate is an index of evaluation algorithms error correcting capability, if pursue the error correcting capability of algorithm merely, False Rate can reach lower numerical value, but the speed of self-test is reduced greatly; And if pursue the speed of computing merely, in the time of the speeding up of self-test, also may cause the likelihood ratio judged by accident higher.So efficient is only key.This algorithm balance has been considered reliability and speed, has than higher efficient.
After all data participated in computing and obtain 16 check code, arithmetic operation was counted data among the SigAna by RomTstOut serial output, has so far finished the test of a 16K ROM.
The Core Feature of ROM1 test is to detect the correctness of data among the ROM1, therefore contains an algorithm, the in addition logical operation of the data of each address, obtains one 16 number at last, is placed on arithmetic operation and counts among the SigAna.At original state operand SigAna is ' 0 ', after control signal RomTstEn=' 1 ' begins test, produce new SigAna value, constitute by 3 parts, SigAna[15] be that the XOR that condenses after the SigAna of last clock period generation and SigSeed and the operation is formed, SigAna[14:8] be the SigAna[15:9 that produced last clock period] displacement forms SigAna[7:0] be the SigAna[8:1 that produced a last clock period] with the current RomData value that obtains of XOR mutually.After finishing, calculating produces next SigAna value with next RomData again.Cycle calculations like this, each the number computing in ROM1 finishes, and obtains one 16 result.Therefore, utilize this method to detect and whether have misdata among the ROM1.
Claims (5)
1. circuit of testing ROM (read-only memory), comprise: ROM (read-only memory) (1) is characterized in that: also comprise ROM (read-only memory) control signal end (2), read the control circuit (3) of ROM (read-only memory) signal, ROM data computing circuit (4), output circuit (5); Described ROM (read-only memory) control signal end (2) is connected with the input end of the control circuit of reading the ROM (read-only memory) signal (3), the first input end of ROM data computing circuit (4), the first input end of output circuit (5); The described output terminal of reading the control circuit (3) of ROM (read-only memory) signal outputs to the read control signal of ROM (read-only memory) the input end of described ROM (read-only memory) (1); The output terminal of described ROM (read-only memory) (1) outputs to the data of ROM (read-only memory) second input end of ROM data computing circuit (4); The output terminal of ROM data computing circuit (4) outputs to the arithmetic operation number second input end of described output circuit (5); Output circuit (5) is with the data output of test result.
2. a kind of circuit of testing ROM (read-only memory) according to claim 1, it is characterized in that: the described control circuit (3) of reading the ROM (read-only memory) signal comprises address register (31), first MUX (32), first trigger (33), clock (34); Described address register (31) is connected with first, second input end of MUX (32) respectively with ROM (read-only memory) control signal end (2); The output terminal of described clock (34) and MUX (32) is connected with first, second input end of trigger (33) respectively, the output terminal of described trigger (33) is connected with the input end of ROM (read-only memory) (1), with the read signal of CROM (control read only memory) (1).
3. a kind of circuit of testing ROM (read-only memory) according to claim 1, it is characterized in that: described ROM data computing circuit (4) comprises clock (34), with computing, the XOR circuit (41) that condenses, shift operation circuit (42), XOR circuit (43); Described and computing, the XOR circuit (41) that condenses are several the 16th circuit that formed by the XOR that condensed after the arithmetic operation number of a last clock period and computing seed number and the operation of arithmetic operation; Described shift operation circuit (42) be the 9th to the 15th by several the 10th circuit that form to the 16th bit shift of the arithmetic operation of a last clock period; Described XOR circuit (43) be the 1st to the 8th be the arithmetic operation of a last clock period several the 2nd to the 9th with current ROM (read-only memory) (1) in the data circuit that forms of XOR mutually; Described and computing, the XOR circuit (41) that condenses, shift operation circuit (42), XOR circuit (43) are exported the arithmetic operation number under the control of clock (34) and ROM (read-only memory) control signal end (2).
4. a kind of circuit of testing ROM (read-only memory) according to claim 1 is characterized in that: described output circuit (5) comprises address register (31), second MUX (52), second trigger (53), clock (34); Described address register (31) is connected with second MUX (52) input end; Described second MUX (52) output terminal is connected with the first input end of second trigger (53), described ROM (read-only memory) control signal end (2) is connected with second input end of second trigger (53), described clock (34) is connected with the 3rd input end of second trigger (53), with the control data output that arithmetic operation is several the 0th.
5. a kind of circuit of testing ROM (read-only memory) according to claim 2 is characterized in that: described address register (31) is 15 a address register.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 03231629 CN2615770Y (en) | 2003-05-30 | 2003-05-30 | Electric circuit for testing read-only memory |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 03231629 CN2615770Y (en) | 2003-05-30 | 2003-05-30 | Electric circuit for testing read-only memory |
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| CN2615770Y true CN2615770Y (en) | 2004-05-12 |
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| CN 03231629 Expired - Fee Related CN2615770Y (en) | 2003-05-30 | 2003-05-30 | Electric circuit for testing read-only memory |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106484557A (en) * | 2015-08-31 | 2017-03-08 | 联芯科技有限公司 | Select to read the method and device of parameter |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106484557A (en) * | 2015-08-31 | 2017-03-08 | 联芯科技有限公司 | Select to read the method and device of parameter |
| CN106484557B (en) * | 2015-08-31 | 2019-06-18 | 联芯科技有限公司 | The method and device of parameter is read in selection |
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| CF01 | Termination of patent right due to non-payment of annual fee |