CN2615756Y - High-speed information safety processor - Google Patents
High-speed information safety processor Download PDFInfo
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- CN2615756Y CN2615756Y CN 02291708 CN02291708U CN2615756Y CN 2615756 Y CN2615756 Y CN 2615756Y CN 02291708 CN02291708 CN 02291708 CN 02291708 U CN02291708 U CN 02291708U CN 2615756 Y CN2615756 Y CN 2615756Y
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- speed information
- high speed
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- internal bus
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Abstract
A high speed information safety processor of the utility model comprises an embedded central processing unit, a soft password engine, an internal bus, a data transceiver, a percutaneous coronary intervention/personal computer memory card international association bus interface, a control path and a data path. The soft password engine comprises a reconfigurable cipher arithmetic logic unit, a standard password arithmetic logic unit, a random number generator which is connected to the internal bus, a packet exploder, a password control register, an input queuing and output queuing. The high speed information safety processor dose not need to get through extra conversion circuit and supports various network protocols. The user can realize the self-definition password arithmetic logic unit of the utility model in a software programming way. The utility model has the advantages that the application mode is flexible, the cryptographic algorithm has more particularity and the security is more easily to realize.
Description
Technical field
The utility model relates to a kind of high speed information safe processor.Relate to specifically and be used for the high speed information safe processing chip that router, ecommerce, digital broadcasting etc. need be carried out information the encrypt/decrypt field.
Background technology
Information security relates to the supreme interest and the safety of country, the interests of commercial organization, so various countries trend towards formulating oneself independently information security system.The domestic information security processor of having developed at present as the SSX04 chip, can carry out the real work of password acceleration computings such as RSA, but these safety chips is only supported one or more cryptographic algorithms usually, and are fairly simple.Remain in following defective:
Therefore 1.) do not have user's restructural algorithm component in the chip,, can not in time remedy by the change algorithm if when algorithm no longer has security.
2.) processing data packets is separated with Cipher Processing, makes that enciphered data needs repeatedly to transmit between each network processes parts, has influenced encryption rate.
Summary of the invention
The purpose of this utility model is to provide a kind of high speed information safe processor of user's restructural cryptographic algorithm.
High speed information safe processor of the present utility model, it is characterized in that it comprises: flush bonding processor CPU, soft cipher engine, internal bus, data collector, the PCI/PCMCIA bus interface, control path and data path, said soft cipher engine comprises restructural cryptarithm logical block, the standard cipher arithmetic logical unti, the randomizer that links to each other with internal bus, the packet delivery device, the cipher control register, input queue and output queue, the PCI/PCMCIA bus interface is used for being connected with the pci bus or the pcmcia bus of external computer system, data collector will distinguish from the control information and the data message of PCI/PCMCIA bus interface, the control path is passed through in the control information of its output, be transferred to flush bonding processor CPU through internal bus, the data message of output is transferred to the packet delivery device of soft cipher engine by data path, this packet delivery device and restructural cryptarithm logical block, the standard cipher arithmetic logical unti, input queue links to each other with output queue, cipher control register and restructural cryptarithm logical block, the standard cipher arithmetic logical unti, internal bus and packet delivery device link to each other.
Usually, on flush bonding processor CPU, be connected to CPU external address data bus, so that can articulate outside extended memory.For high speed information safe processor (chip) is carried out power managed, when chip when not having data to handle, forward it to sleep state, and, can on flush bonding processor CPU, connect power managed and debugging interface for ease of debugging utility; Also can after being used to store power down, the internal bus connection still need the electricity erasable memorizer of hold mode information and the chip number of identification chip identity information.
During use, high speed information safe processor of the present utility model is installed in the pci card, and is installed on the PCI slot of machine system.Its course of work is as follows:
CPU in the computer system sends control information to the high speed information safe processor via the PCI/PCMCIA bus interface, data collector receives the information that sends, judging this according to the target address space of information is to belong to control information, so control information by the control path, is transferred to flush bonding processor CPU through internal bus; Flush bonding processor CPU carries out analyzing and processing to control information, send a series of processing data packets and Cipher Processing parameter to cipher engine then, cipher engine is after having accepted parameter and control signal, finished initialization, subsequent it will wait for the data message that need carry out encrypt/decrypt; Computer system sends data message through the PCI/PCMCIA bus interface to the high speed information safe processor, data collector receives the information that sends, judging this according to the target address space of information is to belong to data message, so it is directly delivered to the input queue of the connection packet distributor in the cipher engine via data path; Cipher control register controlled packet delivery device, make data stream pass in and out restructural cryptarithm logical block or standard cipher arithmetic logical unti by the mode of anticipation, the packet delivery device takes out packet in input queue and the parameter in the cipher control register, and overanxious useless data, send into restructural cryptarithm logical block or standard cipher arithmetic logical unti, handle the data and the various parameter of input by restructural cryptarithm logical block or standard cipher arithmetic logical unti, and send the result back to the packet delivery device, the packet delivery device generates new packet with some parameters in crypto-operation result and the cipher control register, and deposits it in output queue; Data message in the output queue sends in the computer system by the PCI/PCMCIA bus interface in the mode of DMA (immediate data reads) via data path again and goes.If also have data to need encrypting and decrypting, then continue to repeat said process.
The utility model has the advantages that:
1. the soft cipher engine with restructural cryptarithm logical block and standard cipher arithmetic logical unti is set in the high speed information safe processor, by the soft cryptarithm logical block in the soft cipher engine, make the user can be according to the needs of oneself, mode with software programming realizes its self-defining cryptarithm logical block, application mode is just more flexible like this, and cryptographic algorithm can have singularity more, be convenient to maintain secrecy;
2. added the packet delivery device, made the utility model processor can directly support talk various network protocols, and do not need, be beneficial to the performance that improves total system by extra change-over circuit.
3. adopt the software protocol treatment technology, can expand the external command interpretive routine by CPU external address data bus, to handle new security protocol, this can improve the dirigibility of safe processor.
Description of drawings
Fig. 1 is a kind of concrete formation block diagram of high speed information safe processor;
Fig. 2 is that soft cipher engine constitutes block diagram.
Embodiment
With reference to Fig. 1, high speed information safe processor of the present utility model comprises: flush bonding processor CPU1, soft cipher engine 2, internal bus 3, data collector 4, PCI/PCMCIA bus interface 5, control path 6 and data path 7, PCI/PCMCIA bus interface 5 is used for being connected with the pci bus or the pcmcia bus of external computer system, data collector 4 links to each other with PCI/PCMCIA bus interface 5, to distinguish from the control information and the data message of PCI/PCMCIA bus interface 5 by it, the control information of data collector output is by control path 6, be transferred to flush bonding processor CPU through internal bus 3, the data message of output is transferred to soft cipher engine 2 by data path 7, in the illustrated example, flush bonding processor CPU is connected to CPU external address data bus 8, power managed 10 and debugging interface 11.The primary control program (PCP) storer that flush bonding processor CPU adopts built-in security protocol to handle is as the MCore that can adopt ARM, MIPS, motorola inc etc.On internal bus, also be connected with electricity erasable memorizer 9.
Said soft cipher engine 2, see shown in Figure 2, it comprises restructural cryptarithm logical block 12, standard cipher arithmetic logical unti 13, the randomizer 14 that links to each other with internal bus 3, packet delivery device 15, cipher control register 16, input queue 17 and output queue 18.Randomizer 14 can adopt real random number generator.Packet delivery device 15 links to each other with restructural cryptarithm logical block 12, standard cipher arithmetic logical unti 13, input queue 17 and output queue 18.Cipher control register 16 links to each other with restructural cryptarithm logical block 12, standard cipher arithmetic logical unti 13, internal bus 3 and packet delivery device 15.Here, internal bus is connected with chip number 19.
Claims (7)
1. high speed information safe processor, it is characterized in that it comprises: flush bonding processor CPU[1], soft cipher engine [2], internal bus [3], data collector [4], PCI/PCMCIA bus interface [5], control path [6] and data path [7], said soft cipher engine [2] comprising: restructural cryptarithm logical block [12], standard cipher arithmetic logical unti [13], the randomizer [14] that links to each other with internal bus [3], packet delivery device [15], cipher control register [16], input queue [17] and output queue [18], PCI/PCMCIA bus interface [5] is used for being connected with the pci bus or the pcmcia bus of external computer system, data collector [4] will distinguish from the control information and the data message of PCI/PCMCIA bus interface [5], the control information of its output is by control path [6], be transferred to flush bonding processor CPU[1 through internal bus [3]], the data message of output is transferred to the packet delivery device [15] of soft cipher engine [2] by data path [7], this packet delivery device [15] and restructural cryptarithm logical block [12], standard cipher arithmetic logical unti [13], input queue [17] links to each other with output queue [18], cipher control register [16] and restructural cryptarithm logical block [12], standard cipher arithmetic logical unti [13], internal bus [3] and packet delivery device [15] link to each other.
2. high speed information safe processor according to claim 1 is characterized in that said flush bonding processor CPU[1] the primary control program (PCP) storer handled of built-in security protocol.
3. high speed information safe processor according to claim 1 is characterized in that said flush bonding processor CPU[1] be connected to power managed [10].
4. high speed information safe processor according to claim 1 is characterized in that said flush bonding processor CPU[1] be connected to debugging interface [11].
5. high speed information safe processor according to claim 1 is characterized in that said flush bonding processor CPU[1] be connected to CPU external address data bus [8].
6. high speed information safe processor according to claim 1 is characterized in that said randomizer [14] is a real random number generator.
7. high speed information safe processor according to claim 1 is characterized in that said internal bus [3] is connected to electricity erasable memorizer [9] and chip number [19].
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 02291708 CN2615756Y (en) | 2002-12-12 | 2002-12-12 | High-speed information safety processor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 02291708 CN2615756Y (en) | 2002-12-12 | 2002-12-12 | High-speed information safety processor |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN2615756Y true CN2615756Y (en) | 2004-05-12 |
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ID=34238679
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 02291708 Expired - Lifetime CN2615756Y (en) | 2002-12-12 | 2002-12-12 | High-speed information safety processor |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN2615756Y (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112130981A (en) * | 2020-09-28 | 2020-12-25 | 天地伟业技术有限公司 | Method for improving service efficiency of internal hardware processing unit of SOC (System on chip) |
-
2002
- 2002-12-12 CN CN 02291708 patent/CN2615756Y/en not_active Expired - Lifetime
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112130981A (en) * | 2020-09-28 | 2020-12-25 | 天地伟业技术有限公司 | Method for improving service efficiency of internal hardware processing unit of SOC (System on chip) |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| AV01 | Patent right actively abandoned |
Effective date of abandoning: 20051228 |
|
| C25 | Abandonment of patent right or utility model to avoid double patenting |