CN2540667Y - Display screen for forcasting, stop of arrival of public bus - Google Patents
Display screen for forcasting, stop of arrival of public bus Download PDFInfo
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- CN2540667Y CN2540667Y CN 02214491 CN02214491U CN2540667Y CN 2540667 Y CN2540667 Y CN 2540667Y CN 02214491 CN02214491 CN 02214491 CN 02214491 U CN02214491 U CN 02214491U CN 2540667 Y CN2540667 Y CN 2540667Y
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Abstract
The utility model discloses a destination forecasting display screen for common transport operating vehicles. The utility model is characterized in that the information output end of a vehicle locater is connected with the information input end of a vehicle-carrying communication controller via a serial port, wherein the information output end of the vehicle-carrying communication controller is connected with a vehicle-carrying DS radio station, the information output end of the DS reception radio station is connected with the information input end of a data processing device, the information output end of the data processing device is connected with the information input end of an encoder via a serial port, the information output end of the encoder is connected with a paging launching pad, the information output end of the pager is connected with the information input end of a paging signal-receiving processor, and the information output end of the paging signal-receiving processor is connected with the input end of the display screen. The utility model is capable of displaying the current positions of the operating vehicles in the public-transport operating circuits on the display screen of each station in real time, is capable of realizing the scientific management of the public-transport operating and is favorable for people waiting for the buses to know the waiting time of the station.
Description
Affiliated technical field
The utility model relates to a kind of display screen, especially a kind of display screen that can show that the public transport operational vehicle arrives at a station and forecasts.
Background technology
At present, the urban public transport operational vehicle arrives at a station forecast mostly by the steward or be arranged on the arrive at a station forecast of website precursor on the vehicle, this forecasting mode of arriving at a station can only realize to personnel forecast by bus, for the task that can not realize then that each website marquis car personnel operational vehicle arrives at a station and forecasts.In addition, at present public traffic management department on each circuit just the current location situation at operating public transit vehicle can not grasp in real time, schedule job exist blindly must, can't monitor operation conditions, this is the unsurmountable defective that exists in the existing public transport operation system.
Summary of the invention
Task of the present utility model is to provide a kind of public transport operational vehicle that the current location of operating public transit vehicle in the circuit can be shown by the display screen that is arranged on each website forecast display screen that arrives at a station.
Task of the present utility model takes following technical scheme to realize.The utility model is by the vehicular communication unit of being made up of vehicle retainer, vehicle-carrying communication controller, vehicle-mounted data radio station that is arranged on the public transit vehicle; Pass to receive the vehicle location monitored base stations that radio station, data processor, scrambler, call transmitting station are formed by being arranged at number on the base station; The vehicle of being made up of the beeper, paging information receiving processor, the display screen that are arranged on each website of public transport forecast display device three parts of arriving at a station are organized.The information output that it is characterized in that vehicle retainer is connected by the information input terminal of serial port with the vehicle-carrying communication controller, and the information output of vehicle-carrying communication controller is connected with vehicle-mounted data radio station; Number passes the information output that receives the radio station and is connected with the information input terminal of data processor, and the signal output part of data processor is connected with the information input terminal of scrambler by serial port, and the information output of scrambler is connected with the call transmitting station; The signal output part of beeper is connected with the signal input part of notifying from a phone call signal receiving processor, and the information output of paging information receiving processor is connected with the information input terminal of display screen.
Owing to adopted technique scheme, vehicle retainer sends vehicle position information to the vehicle-carrying communication controller by serial port and handles the back and pass transmitting station by number and information is sent to number pass and receive the radio station, the vehicle position information that number biography reception radio station receives is given in the data processor and is handled, information after the processing is sent in the scrambler by serial port and is encoded, vehicle position information behind the coding is given the call transmitting station information is sent, beeper receives to send in the paging information receiving processor after the information and handles, information after the processing is sent in the display screen and is shown, thereby finishes task of the present utility model.
The beneficial effects of the utility model are, the one, and real-time on the display screen of each website, the showing in position that can each operational vehicle in the public transport operation circuit is current; The 2nd, public traffic management department can monitor the current location of operational vehicle in the public bus network; The 3rd, can realize the scientific management of public transport operation and help marquis's car personnel understanding the our station marquis car time.
Description of drawings
The embodiment given below with reference to accompanying drawing further specifies the utility model.
Accompanying drawing 1 has provided circuit structure block scheme of the present utility model;
Accompanying drawing 2 has provided the electrical block diagram of the utility model vehicular communication unit;
Accompanying drawing 3 has provided the arrive at a station electrical block diagram of forecast display device of the utility model vehicle;
In the accompanying drawings, 1 is that vehicle retainer, 2 for notify from a phone call transmitting station, 8 for beeper, 9 for paging information receiving processor, 10 is LED display for scrambler, 7 for number pass to receive radio station, 5 for data processor, 6 for vehicle-mounted data radio station, 4 for vehicle-carrying communication controller, 3.
In accompanying drawing 2, U1 is that model is that 8031 singlechip CPU, U2 are that model is that address latch, the U3 of 74LS573 is that model is that 62256 data-carrier store, U4 are that model is that level translator, the U7 of MAX232 is that model is that singlechip CPU, U8A and the U9A of 89C2051 is that model is that gate circuit, CY1 and the CY2 of 74LS04 is that crystal oscillator, CZ3 and CZ4 are that gang socket, A are that vehicle retainer, B are vehicle-mounted data radio station.
In accompanying drawing 3, U1 is that model is 8031 singlechip CPU, U2 is that model is the address latch of 74LS573, U3 is that model is 62256 data-carrier store, U4 is that model is the level translator of MAX232, and U6A is that model is the comparer of LM393, and CY1 is prosperous oscillation body device, the socket of CZ1 for being connected with the LED charactron, BP-R is the beeper interface.
With reference to the accompanying drawings 1, the signal output part that is arranged at the vehicle retainer 1 on the public transit vehicle is connected by the information input terminal of serial port with vehicle-carrying communication controller 2, and the information output of vehicle-carrying communication controller 2 is connected with vehicle-mounted data radio station 3; Number passes the information output that receives radio station 4 and is connected with the information input terminal of data processor 5, the information output of data processor 5 is connected by the information input terminal of serial port with scrambler 6, and the information output of scrambler 6 is connected with call transmitting station 7; The information output of beeper 8 is connected with the information input terminal of paging information receiving processor 9, and the information output of paging information receiving processor 9 is connected with the information input terminal of LED display 10.
With reference to the accompanying drawings 2, vehicle communication device of the present utility model mainly is made up of vehicle retainer A, vehicle-mounted data radio station B, gang socket CZ3 and CZ4, singlechip CPU U1, singlechip CPU U7, address latch U2, data-carrier store U3, level translator U4.CPU plays the center control action, has instruction fetch and analyzes execution command, gathers functions such as input data, output data.8 incoming lines of address latch U2 and signal wire C are connected to data bus and the ALE line of CPU U1 respectively, address latch U2 latchs the address information of CPU U1 output, it is output as the least-significant byte address bus, the data line of data-carrier store U3 is connected to the data bus of CPU U1, the least-significant byte of address wire is connected to the output terminal of address latch U2, high 7 and/the CS line is connected to the P2 mouth of CPU U1, the read-write line is connected to the read-write line of CPU U1 respectively, CPU U1 inside has the storer of 4K to be used for storing the instruction machine code of establishment in advance, the serial port input and output of CPU U1 are connected to T2 OUT and the T2IN of level translator U4, and the R1 OUT of level translator U4 and R1 IN are connected to the 3rd pin and the 2nd pin of socket CZ3 respectively.The 5th pin of socket CZ3, the 3rd pin and the 2nd pin are connected to the 5th pin, the 2nd pin and the 3rd pin of vehicle retainer respectively by line, the serial port input and output of CPU U7 are connected to T1 OUT and the T1 IN of level translator U4, and the R2 OUT of level translator U4 and R2 IN are connected to the 3rd pin and the 2nd pin of socket CZ4 respectively.The 5th pin of socket CZ4, the 3rd pin and the 2nd pin are connected to the 5th pin, the 2nd pin and the 3rd pin of vehicle-mounted data radio station respectively by line, and electrochemical capacitor C4 and C5 are connected to level translator C1 respectively
+C1
-C2
+C2
-One end, crystal oscillator CY1 two ends are connected to X1 and the X2 two ends of CPU U1 respectively, are connected to X1 and the X2 two ends of CPU U1 after capacitor C 1 and the C2 serial connection respectively, the common end grounding of capacitor C 1 and C2.Resistance R 3 is joined with capacitor C 3 and is then linked to each other with the RESET pin of CPU U7, another termination+5V power supply of capacitor C 3, the other end of resistance R 3 is connected to ground, crystal CY2 two ends are connected to X1 and the X2 two ends of CPU U7 respectively, be connected to X1 and the X2 two ends of CPU U7 after capacitor C 6 and the C7 serial connection respectively, the common end grounding of capacitor C 6 and C7.The EA/VP pin of one termination CPU U1 of resistance R 1, another termination+5V power supply of R1, one termination of capacitor C 8+5V power supply, the RESET pin of another termination CPU U1 also passes through resistance R 2 ground connection, and the P17 of CPU U1 is connected to the T0 pin of CPU U7, and the P17 of CPU U7 is connected to the INT0 pin of CPU U1, the input pin of U8A is connected to the P10 pin of CPU U7, the output pin of U8A is connected to the P10 pin of CPU U1, and the input pin of U9A is connected to the P11 pin of CPU U1, and the output pin of U9A is connected to the P11 pin of CPU U7.
With reference to the accompanying drawings 3, the paging information receiving processor is made up of oscillatory circuit, reset circuit, singlechip CPU U1, external data memory circuit, serial data input and output circuit, voltage contrasting amplified circuit, power-down data protection circuit, charactron interface circuit.
Oscillatory circuit and CPU U1 clock internal circuit constitute the clock mode of single-chip microcomputer together, and there is a high-gain inverting amplifier that is used to constitute oscillator CPU U1 inside, and pin X1 and X2 are respectively this amplifier input terminal and output terminal.Crystal CY1 two ends are connected to X1 and the X2 two ends of CPU respectively, and capacitor C1 and C2 serial connection back are with crystal CY1 and connect the common end grounding of capacitor C 1 and C2.External crystal CY1 and capacitor C 1 and C2 constitute antiresonant circuit, are connected in the backfeed loop of amplifier just self-sustained oscillation of internal oscillator at this moment.
Reset circuit is made up of electrochemical capacitor C8 and resistance R 2, the positive pole of electrochemical capacitor C8 is connected to positive source, the negative pole of electrochemical capacitor C8 is connected to the RESET pin of CPU U1, resistance R 2 one is connected to the RESET pin of CPU U1, the other end of resistance R 2 is connected to ground, switching on moment, in RC circuit charging process, positive pulse appears in the RESET foot of CPU U1, thereby single-chip microcomputer is resetted, the core of reset circuit is exactly that the above stable high level of 10MS appears in the RESET pin that must guarantee CPU U1, so just can realize resetting reliably.
The procedure stores circuit.There is 4K byte ROM/EPROM program storage CPU U1 inside, is used for storing the instruction machine code of establishment in advance.When/EA=1, low 4K address (0000H-0FFFFH) is pointed in the sheet, when/EA=0, low 4K address (0000H-0FFFFH) is pointed to outside the sheet, resistance R 1 one is connected to positive source, the other end is connected to the EA/VP pin of CPU U1, makes the EA/VP pin keep high level, and program leaves in the ROM/EPROM storer of CPUU1 inside.
The external data memory circuit.CPU plays the center control action, has instruction fetch and analyzes execution command, gathers functions such as input data, output data.The P0 mouth (P00-P07) of CPU U1 is the address/data bus of time-sharing multiplex, therefore must utilize address latch that address signal is separated from address/data bus when carrying out data read and storage.Address latch uses eight D-latchs of the ternary output of band, and address latch signal is provided by the ALE/P pin of CPU U1, data bus (P00-P07) and ALE line that 8 incoming lines (1D-8D) of address latch U2 and signal wire C are connected to CPU U1 respectively.Address latch U2 latchs the address information of CPU U1 output, and it is output as the least-significant byte address bus.The data line of data-carrier store U3 (DQ1-DQ8) is connected to the data bus (P00-P07) of CPU U1, the least-significant byte of address wire (A0-A7) is connected to the output (1Q-8Q) of address latch U2, high 7 (A8-A14) and/the CS line is connected to the P2 (P20-P27) mouthful of CPU U1, read-write line/OE of U3 and/WE be connected to respectively CPU U1 read-write line/RD and/WR, U2 /the OC pin is called data and squeezes into line, when/when OC is low level and the enable signal line C of the triple gate of U2 when being high level, triple gate is in conducting state, allow 1D-8D to output to 1Q-8Q, when/when OC is low level and the triple gate of U2 can make signal wire C be low level the time, triple gate disconnects, 1Q-8Q is in floating dummy status, when/the enable signal line C of the triple gate of U2 level why no matter when OC is high level, triple gate disconnects, and 1Q-8Q is in floating dummy status.The P0 mouth of CPU U1 is multiplexing address/data line of data-carrier store (RAM) U3, and the P2 mouth is used for data storer U3 (RAM) is carried out page addressing, and during to the RAM read/write, CPU U1 produces the RD/WR signal.
Serial data input and output circuit.There is a full duplex serial port that function is very strong the inside of CPU U1, serial port have two physically independently receive, transmission buffer SBUF, can send, receive data simultaneously.The RXD of CPU U1 is the Data Receiving pin, and TXD is that data send pin.The serial port output terminal of CPU U1 is connected to the T1 IN of level translator U4, and the R1 OUT of level translator U4 is connected to the 3rd pin of socket CZ1.Electrolytic condenser C4 and C5 positive pole are connected to the C1 of level translator U4 respectively
+C2
+End, electrochemical capacitor C4 and C5 negative electrode are connected to the C1 of level translator U4 respectively
-C2
-End.Integrated circuit U4 be one do not need+12V and-power supply of 12V power supply, RS-232 transceiver sheet contains a handle+12V and becomes-the charge pump voltage changer of 12V, in the sheet charge pump will+5 be transformed into produce the RS-232 output level required+10V ,-10V voltage.
Voltage contrasting amplified circuit.Resistance R 3 and R5 serial connection back one are connected to+the 5V power supply, the other end is connected to ground, common port is connected to the 3rd pin of the positive input terminal of voltage comparator U6A, resistance R 4 and R6 serial connection back one are connected to+the 5V power supply, the other end is connected to ground, and common port is connected to the 2nd pin of the negative input end of comparer U6A, and the 8th pin of comparer U6A connects+the 5V power supply, the 4th pin ground connection, the 3rd pin connects the output terminal of beeper.Because about the data signal levels 3V of beeper output, and the required electricity of the RXD of CPU U1 jade is 5V, therefore need voltage amplifier circuit.The data-signal of beeper output is delivered to the positive input terminal of U6A, compares the 1 pin output+5V voltage of big person U6A, otherwise output 0V voltage with negative input end voltage.
Claims (3)
1, the public transport operational vehicle forecast display screen that arrives at a station comprises the vehicular communication unit of being made up of vehicle retainer, vehicle-carrying communication controller, vehicle-mounted data radio station that is arranged on the public transit vehicle; Pass to receive the vehicle location monitored base stations that radio station, data processor, scrambler, call transmitting station are formed by being arranged at number on the base station; The vehicle of being made up of the beeper, paging information receiving processor, the display screen that are arranged on each website of public transport forecast display device three parts of arriving at a station are organized, the information output that it is characterized in that vehicle retainer is connected by the information input terminal of serial port with the vehicle-carrying communication controller, and the information output of vehicle-carrying communication controller is connected with vehicle-mounted data radio station; Number passes the information output that receives the radio station and is connected with the information input terminal of data processor, and the signal output part of data processor is connected with the information input terminal of scrambler by serial port, and the information output of scrambler is connected with the call transmitting station; The signal output part of beeper is connected with the signal input part of notifying from a phone call signal receiving processor, and the information output of paging information receiving processor is connected with the information input terminal of display screen.
2, the public transport operational vehicle according to claim 1 forecast display screen that arrives at a station, it is characterized in that described vehicle communication apparatus is by vehicle retainer A, vehicle-mounted data radio station B, gang socket CZ3 and CZ4, singlechip CPU U1, singlechip CPU U7, address latch U2, data-carrier store U3, level translator U4 forms, 8 incoming lines of address latch U2 and signal wire C are connected to data bus and the ALE line of CPU U1 respectively, the data line of data-carrier store U3 is connected to the data bus of CPU U1, the least-significant byte of address wire is connected to the output terminal of address latch U2, high 7 and/the CS line is connected to the P2 mouth of CPU U1, the read-write line is connected to the read-write line of CPU U1 respectively, the serial port input and output of CPUU1 are connected to T2 OUT and the T2 IN of level translator U4, and the R1 OUT of level translator U4 and R1 IN are connected to the 3rd pin and the 2nd pin of socket CZ3 respectively.The 5th pin of socket CZ3, the 3rd pin and the 2nd pin are connected to the 5th pin, the 2nd pin and the 3rd pin of vehicle retainer respectively by line, the serial port input and output of CPU U7 are connected to T1OUT and the T1 IN of level translator U4, the R2 OUT of level translator U4 and R2 IN are connected to the 3rd pin and the 2nd pin of socket CZ4 respectively, the 5th pin of socket CZ4, the 3rd pin and the 2nd pin are connected to the 5th pin, the 2nd pin and the 3rd pin of vehicle-mounted data radio station respectively by line, and electrochemical capacitor C4 and C5 are connected to level translator C1 respectively
+C1
-C2
+C2
-One end, crystal oscillator CY1 two ends are connected to X1 and the X2 two ends of CPU U1 respectively, be connected to X1 and the X2 two ends of CPU U1 after capacitor C 1 and the C2 serial connection respectively, the common end grounding of capacitor C 1 and C2, resistance R 3 is joined with capacitor C 3 and is then linked to each other with the RESET pin of CPU U7, another termination+5V power supply of capacitor C 3, the other end of resistance R 3 is connected to ground, crystal CY2 two ends are connected to X1 and the X2 two ends of CPU U7 respectively, be connected to X1 and the X2 two ends of CPU U7 after capacitor C 6 and the C7 serial connection respectively, the common end grounding of capacitor C 6 and C7, the EA/VP pin of a termination CPU U1 of resistance R 1, another termination+5V power supply of R1, one termination of capacitor C 8+5V power supply, the RESET pin of another termination CPU U1 also passes through resistance R 2 ground connection, and the P17 of CPUU1 is connected to the T0 pin of CPU U7, and the P17 of CPU U7 is connected to the INT0 pin of CPU U1, the input pin of U8A is connected to the P10 pin of CPU U7, the output pin of U8A is connected to the P10 pin of CPU U1, and the input pin of U9A is connected to the P11 pin of CPU U1, and the output pin of U9A is connected to the P11 pin of CPU U7.
3, the public transport operational vehicle according to claim 1 forecast display screen that arrives at a station; it is characterized in that described paging information receiving processor is made up of oscillatory circuit, reset circuit, singlechip CPU U1, external data memory circuit, serial data input and output circuit, voltage contrasting amplified circuit, power-down data protection circuit, charactron interface circuit, it is characterized in that:
A, oscillatory circuit are X1 and the X2 two ends that crystal CY1 two ends are connected to CPU respectively, and capacitor C1 and C2 serial connection back are with crystal CY1 and connect the common end grounding of capacitor C 1 and C2;
B, reset circuit are that the positive pole of electrochemical capacitor C8 is connected to positive source, and the negative pole of electrochemical capacitor C8 is connected to the RESET pin of CPU U1, and resistance R 2 one is connected to the RESET pin of CPU U1, and the other end of resistance R 2 is connected to ground;
C, external data memory circuit are the data bus (P00-P07) that the data line (DQ1-DQ8) of data-carrier store U3 is connected to CPU U1, the least-significant byte of address wire (A0-A7) is connected to the output (1Q-8Q) of address latch U2, high 7 (A8-A14) and/the CS line is connected to the P2 (P20-P27) mouthful of CPU U1, read-write line/OE of U3 and/WE be connected to respectively CPU U1 read-write line/RD and/WR;
D, serial data input and output circuit are the T1 IN that the serial port output terminal of CPU U1 is connected to level translator U4, and the R1 OUT of level translator U4 is connected to the 3rd pin of socket CZ1, and electrolytic condenser C4 and C5 positive pole are connected to the C1 of level translator U4 respectively
+C2
+End, electrochemical capacitor C4 and C5 negative electrode are connected to the C1 of level translator U4 respectively
-C2
-End;
E, voltage contrasting amplified circuit are that resistance R 3 and R5 serial connection back one are connected to+the 5V power supply, the other end is connected to ground, common port is connected to the 3rd pin of the positive input terminal of voltage comparator U6A, resistance R 4 and R6 serial connection back one are connected to+the 5V power supply, the other end is connected to ground, and common port is connected to the 2nd pin of the negative input end of comparer U6A, and the 8th pin of comparer U6A connects+the 5V power supply, the 4th pin ground connection, the 3rd pin connects the output terminal of beeper.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 02214491 CN2540667Y (en) | 2002-05-16 | 2002-05-16 | Display screen for forcasting, stop of arrival of public bus |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 02214491 CN2540667Y (en) | 2002-05-16 | 2002-05-16 | Display screen for forcasting, stop of arrival of public bus |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN2540667Y true CN2540667Y (en) | 2003-03-19 |
Family
ID=33693810
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 02214491 Expired - Fee Related CN2540667Y (en) | 2002-05-16 | 2002-05-16 | Display screen for forcasting, stop of arrival of public bus |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN2540667Y (en) |
-
2002
- 2002-05-16 CN CN 02214491 patent/CN2540667Y/en not_active Expired - Fee Related
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| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| C19 | Lapse of patent right due to non-payment of the annual fee | ||
| CF01 | Termination of patent right due to non-payment of annual fee |