CN2528080Y - Chip group and controller for supporting information signal interruption - Google Patents
Chip group and controller for supporting information signal interruption Download PDFInfo
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- CN2528080Y CN2528080Y CN 01259679 CN01259679U CN2528080Y CN 2528080 Y CN2528080 Y CN 2528080Y CN 01259679 CN01259679 CN 01259679 CN 01259679 U CN01259679 U CN 01259679U CN 2528080 Y CN2528080 Y CN 2528080Y
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Abstract
The utility model provides a chip set and a controller that support information signal type interruption. The control chip set comprises a dynamic random access and storage controller, a host interface and an interruption controller. The information signal type interruption controller comprises an information signal type interruption detector, an information signal type interruption calculator, an information signal type interruption generator and an interruption controller. The utility model is characterized in that the preserved interruption address ranged is arranged in the system memory address range. Therefore, data waiting for treatment and system designated information will be arranged in sequence when being written into a buffer together, so that the problem caused by delaying when the data and the information are written into the buffer is solved naturally, and the data and the information have no relationship with the stratum of PCI bus at all. Because the system memory can be used to store a plurality of system designated information, a plurality of different interruption requests in different peripheral devices can be treated in the same interruption service program.
Description
Technical field
The utility model relates to the compatibility interface device that a kind of peripheral hardware connects (peripheral componentinterconnection is called for short PCI) bus, particularly relevant for hardware unit compatible mutually with interruption processing method on a kind of pci bus.
Background technology
At present in the personal computer motherboard with pci bus as connecting the main bus of peripheral hardware adapter.On pci bus, have only primary controller (master) or main bridge (bridge) can initiate exchanges data (transaction), and the PCI compatible apparatus of initiating transaction such as reading or write is called as initiator (initiator), its corresponding trading object just is called destination apparatus (target), data between these PCI compatible apparatus transmit mainly by cycle frame (cycle frame, be called for short FRAME) signal, data address bus (address/data bus, be called for short AD) signal, order/byte starts (command/byte enable, be called for short CBE[3:0]) signal, ready (the initiator ready of initiator, be called for short IRDY) signal, ready (the target ready of destination apparatus, be called for short TRDY) signal, and stop interface control signal such as (stop, be called for short STOP) signal and control.
The FRAME signal is sent by initiator, in order to the indication accessing operation beginning and the duration, when the FRAME signal is sent, expression begins to carry out by the exchanges data of pci bus, when maintaining low level, the FRAME signal represents that then exchanges data continues to carry out, at this moment, at first can be during address cycle, send effective address (validaddress) in the AD of address data bus signal, simultaneously can be at CBE[3:0] line sends effective bus line command (satisfying the PCI specification), in order to destination apparatus is pointed out the desired exchanges data form of initiator, wherein CBE (3:0) line is encoded into 16 kinds of different bus line commands with 4, and it has specific definition in the PCI specification.After effective address, address data bus AD just sends the data that will transmit, and is called cycle data this period, and the bus line command of while after CBE (0:3) line is sent coding is whereby to transmit data.IRDY signal and TRDY signal are used, and can carry out data in order to indicate initiating means and destination apparatus to be ready for respectively and transmit.For example: reading action when carrying out, IRDY signal indication initiator is ready to receive data, and when carrying out write operation, TRDY signal indication destination apparatus is ready to receive data.As for the STOP signal, destination apparatus comes the requirement initiator to stop present exchanges data with it.When the FRAME signal stops to send, just represent that stateful transaction transmits for the finishing touch data, or finished data and transmitted.
The interface control signal as control during except above-mentioned exchanges data, pci bus has also defined four look-at-me: INTA, INTB, INTC and INTD, when the peripheral hardware on any one pci bus needs driver handles, can arouse attention by these look-at-mes.But, not only one certainly of peripheral hardware on the pci bus, at this time look-at-me is exactly a Limited resources, so sharing look-at-me becomes unavoidable, because when central broken hair was given birth to, interrupt service routine must be checked the state of peripheral hardware, be which peripheral hardware initiates to interrupt with differentiation, as further control being given the foundation of correct peripheral hardware driver, thereby also cause the burden on the software.
Fig. 1 shows known a kind of being applied on the personal computer motherboard, and the framework synoptic diagram of pci bus compatible system please refer to Fig. 1.General known personal computer motherboard 1 includes: control chip group 100, dynamic RAM 110, central processing unit 120, pci bus I 130, peripheral hardware 150 etc., wherein control chip group 100 comprises south bridge (South Bridge) chip 102 and north bridge (North Bridge) chip 104.Many known senior mainboards also include: PCI-PCI bridge 140, pci bus II 160 and be positioned at peripheral hardware 170 of second stratum etc.
When any one peripheral hardware 150 needs its interrupt service routine to handle, can be on pci bus I130, the beginning internal memory writes transaction, hope is passed through control chip group 100 with pending data, write dynamic RAM 110, while peripheral hardware 150 also sends one of four look-at-mes on the pci bus, to cause the attention of system.At this moment, control chip group 100 must be in due course, and sends look-at-me INTR to central processing unit 120, so that central processing unit is handled pending data, and central processing unit 120 also must be in due course and handles pending data.As everyone knows, because the consideration on the usefulness, the pci bus system is a multitask system that allows many primary controllers, when having begun internal memory, control chip group 100 writes transaction, do not represent the complete dynamic RAM 110 that writes of data, may still there be the impact damper in the control chip group 100 in pending data, really do not write dynamic RAM 110 as yet, and may have the complex data of being sent by different peripheral in the impact damper of control chip group 100.If central processing unit 120 has just begun the processing of pending data before pending data really do not write dynamic RAM 110 as yet, apparently, will cause the mistake of deal with data, this is the situation that definitely can not take place.
Known a kind of solution to the problems described above is in control chip group 100, control produces the opportunity of look-at-me INTR to central processing unit 120, main way is when pending data are not write out as yet fully, do not allow the generation of look-at-me INTR, owing to may have the complex data that belong to different peripheral in the write buffer, and control chip group 100 can't judge which data are pending data, have to work as when all data are not write out as yet fully in the write buffer, just not allow the generation of look-at-me INTR.Therefore, such way will cause and postpone to produce look-at-me INTR, and influence performance.As everyone knows, when the degree of depth of impact damper heals when dark, the time of the write buffer delay (write-buffer latency) that may cause is longer, especially in the present control chip group 100, South Bridge chip 102 is responsible for control pci bus 130, north bridge chips 104 is responsible for control dynamic RAM 110, it will be more serious that this write buffer postpones, be still more when peripheral hardware 170 needs Interrupt Process, by the compatible framework of pci bus of multistage laminar, write buffer postpones to be difficult to more estimate.
Known another kind of way is the opportunity that control central processing unit 120 is handled pending data.Because when making Interrupt Process, central processing unit 120 generally must be checked the state of peripheral hardware, with as the foundation of differentiating Interrupt Process etc., so this way mainly is after must waiting until that pending data integrity writes out, central processing unit 120 could be checked the state of peripheral hardware, reads the purpose that delay (CPU read delay) reaches control by central processing unit.But this kind practice is except the shortcoming that above-mentioned write buffer delay is arranged, also because the read cycle of general central processing unit does not have multitask pipeline (pipeline) function, so have a strong impact on the usefulness of system more.
In the specification of pci bus 2.2, provide a kind of and select the interrupt mode of (option) to be called information signal formula interruption (Message Signaled Interrupt is called for short MSI).It is exactly that peripheral hardware arrives system-specific address (system specified address) through writing system appointed information (system specifed message) that so-called information signal formula is interrupted, just be used as the system-specific address that internal memory writes transaction with one in the pci bus two character group (double word), and system's appointed information write this system-specific address, reach the purpose that produces interrupt request, these system's specified message and addresses, when the pci bus system in the device configuration when (during deviceconfiguration), institute's initialization (initialize) appointment.But, the system that present being seen support information signal formula is interrupted, all use same address for system-specific address, reduced system in same interrupt service routine, handle the elasticity of most different information of peripheral hardware, and on behalf of name, remaining elasticity only plant the reason that may cause interruption in system's appointed information of utilizing 16.And, present being seen system, and the problem of unresolved above-mentioned write buffer delay, also may cause some other situations, for example: because write buffer postpones the oversize old system's appointed information of system's appointed information covering new in the system-specific address that causes.
Summary of the invention
The utility model chipset and controller that the information signal formula is interrupted that provide support, can not be subject to the number of interrupting the pin position, make control chip group behind the complete writing system internal memory of pending data, and then send certain look-at-me to central processing unit, solved the problem that the write buffer delay is caused, the utility model is applicable to the pci bus of multistage laminar, and can be in same interrupt service routine, handle a plurality of different interrupt request of different peripheral, can comprise the elasticity of interrupting occurrence cause in addition in system's appointed information in addition.
The utility model provides a kind of information signal formula interruptable controller, can be applicable to computer system, this computer system comprises control chip group at least, pci bus and Installed System Memory, this control chip group is coupled to pci bus and Installed System Memory, and this control chip group includes dynamic RAM Controller, host interface and interruptable controller, this information signal formula interruptable controller comprises: the information signal formula is interrupted detector, be coupled to pci bus and dynamic RAM Controller, in order to monitor that the internal memory on the pci bus writes transaction, when the address that internal memory writes transaction falls within when keeping the interrupt address scope, system's appointed information behind dynamic RAM Controller writing system internal memory, is sent information signal formula interruption acknowledge signal again; The information signal formula is interrupted counter, be coupled to the information signal formula and interrupt detector and host interface, in order to receive and to count above-mentioned information signal formula interruption acknowledge signal, interrupt count value to form, and will interrupt count value according to host interface and become and send the interruption count value, and send and send the interruption count value; And the information signal formula is interrupted generator, be coupled to the information signal formula and interrupt counter and interruptable controller, in order to according to above-mentioned interruption count value, produce information signal formula interrupt request singal to interruptable controller, make interruptable controller produce interrupt request singal.The very important point, reservation interrupt address scope of the present utility model is positioned at the address realm of Installed System Memory.
A kind of information signal formula interruptable controller according to preferred embodiment of the present utility model, wherein control chip group also is coupled to central processing unit, and information signal formula interruption generator also is coupled to host interface, after central processing unit was handled system's appointed information, central processing unit passes through host interface, send break in service end signal to information signal formula and interrupt generator, and central processing unit is sent to read and interrupted count value to information signal formula interruption counter also by host interface.Above-mentioned central processing unit can pass through host interface earlier, obtains and sends the interruption count value.Above-mentioned information signal formula is interrupted detector and is write the interrupting information of transaction according to internal memory, produces the actual address that writes, and passes through dynamic RAM Controller again, internal memory is write actual the writing in the address of system's appointed information writing system internal memory of transaction.
The chipset that the utility model provides a kind of support information signal formula to interrupt, this chipset is coupled to pci bus, central processing unit and Installed System Memory, chipset of the present utility model comprises: dynamic RAM Controller is coupled to Installed System Memory, in order to control and access system internal memory; Host interface is coupled to central processing unit, in order to as the control interface between chipset and central processing unit; Interruptable controller is coupled to central processing unit, in order to produce interrupt request singal to central processing unit, activates interrupt service routine further to make central processing unit; And information signal formula interruptable controller, be coupled to pci bus, dynamic RAM Controller, host interface and interruptable controller, in order to monitor that the internal memory on the pci bus writes transaction, when the address that internal memory writes transaction is positioned at when keeping the interrupt address scope, with system's appointed information in dynamic RAM Controller writing system internal memory, send information signal formula interrupt request singal again, make interruptable controller produce interrupt request singal.The very important point, reservation interrupt address scope of the present utility model is positioned at the address realm of Installed System Memory.
The utility model is owing to produce the address realm that the address is positioned at Installed System Memory that writes that the internal memory of information signal formula interruption writes transaction, just system's appointed information can really be written in the Installed System Memory, so a plurality of interrupting informations of utilisation system memory storage, so can be in same break in service circulation, handle most different information of different peripheral, can comprise the elasticity of interrupting occurrence cause in addition in the information data in addition.And for chipset, system's appointed information and pending data arrangement in order in write buffer have in the lump solved the problem that the write buffer delay is caused naturally, and irrelevant fully with the stratum of pci bus.
Description of drawings
Fig. 1 shows known a kind of being applied on the personal computer motherboard, the framework synoptic diagram of pci bus system.
Fig. 2 shows according to the control chip group of a kind of support information signal formula interruption of the utility model preferred embodiment and the block schematic diagram of the controller in the control chip group.
Fig. 3 A, Fig. 3 B, Fig. 3 C show the schematic flow sheet of the disposal route of interrupting according to a kind of support information signal formula of the utility model preferred embodiment.The drawing reference numeral explanation:
100,200 control chip group
102 South Bridge chips
104 north bridge chips
110 dynamic RAM
120 central processing units, 130 pci bus I
140 PCI-PCI bridges, 150 peripheral hardwares
160 pci bus II
The peripheral hardware of 170 second stratum
210 information signal formula interruptable controllers
220 information signal formulas are interrupted detector
230 information signal formulas are interrupted counter
240 information signal formulas are interrupted generator
250 dynamic RAM Controllers
260 host interface, 270 interruptable controllers
280 PCI peripheral hardwares, 290 pci buss
Embodiment
Fig. 2 shows according to the control chip group of a kind of support information signal formula interruption of the utility model preferred embodiment and the block schematic diagram of the controller in the control chip group, please refer to Fig. 2.The control chip group 200 of the utility model preferred embodiment is connected to pci bus 290, central processing unit 120 and Installed System Memory (being generally dynamic RAM 110) to I haven't seen you for ages, and chipset of the present utility model comprises at least: information signal formula interruptable controller (being called for short the MSI controller) 210, dynamic RAM Controller (DRAMC) 250, host interface 260 and interruptable controller 270.
Above-mentioned dynamic RAM Controller 250 is coupled to Installed System Memory, is used for controlling and access system internal memory (dynamic RAM 110).Above-mentioned host interface 260 is coupled to central processing unit 120, is mainly used to the control interface as 120 of control chip group 200 and central processing units.Be coupled to central processing unit 120 as for interruptable controller 270, be used for producing interrupt request INTR signal, start interrupt service routine further to make central processing unit 120 to central processing unit 120.
The MSI controller 210 of the utility model original creation comprises: the information signal formula is interrupted detector (being called for short the MSI detector) 220, the information signal formula interrupts counter (being called for short the MSI counter) 230 and the information signal formula is interrupted generator (being called for short the MSI generator) 240.Wherein, MSI detector 220 is coupled to pci bus 290 and dynamic RAM Controller 250, and host interface 260 is connected to MSI counter 230 and MSI generator 240, and MSI generator 240 also is connected to interruptable controller 270.MSI controller 210 of the present utility model monitors that all internal memories write transaction on the pci bus 290, when any one PCI peripheral hardware 280 interrupts causing the attention of system with the information signal formula, can send interrupting information, this interrupting information comprises system-specific address and system's appointed information of two character group, and specified system memory address will be positioned at the reservation interrupt address scope that system is scheduled in the interrupting information, at this moment, MSI controller 210 will monitor this situation, and can be in dynamic RAM Controller 250 writing system internal memories with system's appointed information, and then send an information signal formula interrupt request singal MSI-IRQ, make interruptable controller 270 produce interrupt request singal INTR.
The very important point reservation interrupt address of the present utility model scope is positioned at the address realm of Installed System Memory in the utility model.Present embodiment is allocated the MSI controller that different particular addresss is given each peripheral hardware in advance.So MSI controller 210 can be with in the real writing system internal memory of system's appointed information, before PCI peripheral hardware 280 will send internal memory that the information signal formula interrupts and writes transaction, can be earlier pending data be write the mode of transaction with internal memory, require in the writing system internal memory.This is for control chip group 200, pending data and system specify in the lump and arrange in order in write buffer, so MSI controller 210 can be gone ahead of the rest pending data earlier in the successful writing system internal memory, just immediately the one-writing system appointed information to Installed System Memory, after successfully being written to Installed System Memory, and then send information signal formula interrupt request singal MSI_IRQ to system's appointed information.Therefore, solved the problem that the write buffer delay is caused naturally.As be familiar with this operator and can know easily, such solution is owing to utilize the most basic internal memory to write transaction, so count up to completely without the pass with the stratum of pci bus.
A kind of MSI controller 210 provided by the utility model is placed in the control chip group 200 of mainboard, can save costs such as packing, but is not must be placed in the control chip group 200.MSI detector 220 in the MSI controller 210 of the present utility model is coupled to pci bus 290 and dynamic RAM Controller 250, mainly in order to monitor that the internal memory on the pci bus 290 writes transaction, when system memory address specified in the interruption information is positioned at reservation interrupt address scope, MSI detector 220 writes the transaction interrupting information according to internal memory, produces the actual address that writes earlier.In the present embodiment, earlier internal memory is write the 7th to the 31st of system-specific address of transaction, the combination internal memory writes the 0th to the 4th of system's appointed information of transaction, and add two unitss 0 at the lowest order place, be expressed as: memory_address={MSI_address[31:7], MSI_data[4:0], 00} then, MSI detector 220 is by dynamic RAM Controller 250, system's appointed information that internal memory is write transaction writes the actual of dynamic RAM 110 and writes among the memory_addres of address, that is to say, with pending data and system's appointed information behind dynamic RAM Controller 250 writing system internal memories, MSI detector 220 is sent information signal formula interruption acknowledge MSI_ACK signal again, to notify MSI counter pending data 230 this moment and system's appointed information writing system internal memory really.
MSI counter 230 in the MSI controller 210 is coupled to MSI detector 220 and host interface 260, in order to receive and to calculate above-mentioned information signal formula interruption acknowledge signal MSI_ACK, and the count value of sending MSI_ACK is referred to as to interrupt count value MSI_ACK_count to MSI generator 240.MSI generator 240 is couple to MSI counter 230 and interruptable controller 270, it receives above-mentioned interruption count value MSI_ACK_count, and according to this interruption count value, produce information signal formula interrupt request singal MSI_IRQ, further make interruptable controller 270 produce interrupt request singal INTR.In the present embodiment, when MSI_ACK_count＞0, MSI generator 240 will produce information signal formula interrupt request singal MSI_IRQ.After interruptable controller 270 was received information signal formula interrupt request singal MSI_IRQ, the interrupt request singal INTR that can really send hardware activated interrupt service routine to central processing unit 120 further to make central processing unit 120.As be familiar with this operator when knowing, link up by host interface 260 between above-mentioned MSI generator 240 and the central processing unit 120, but also can directly connect.
Begin at an interrupt service routine, central processing unit 120 is earlier by host interface 260, obtain a number M SI_sent of the interrupting information of writing system internal memory altogether at present, that is to say, obtain the number of the information signal formula interruption that has write the dynamic access internal memory at present, MSI counter 230 can be set MSI_sent for the number of the MSI_ACK_count of this moment.Central processing unit 120 is according to MSI_sent, possible system's appointed information in the reservation interrupt address scope in the scanning system internal memory, and then processing keeps the interior all system's appointed information of interrupt address scope, and calculate the number of system's appointed information of having handled, become to read and interrupt count value MSI_read.Be noted that, system's appointed information of having handled in the Installed System Memory must be disposed, to avoid this system's appointed information processed once more, when removing the internal memory of this part, must read the pattern operation that corrigendum again writes (locked read-modified-write) with locking earlier, will write fashionable making a mistake simultaneously to avoid new system's appointed information.At last before this interrupt service routine finishes, if MSI_read is less than MSI_sent, after MSI_read is modified as MSI_sent, central processing unit 120 is by host interface 260, send break in service end signal MSI_EOI to MSI generator 240, and central processing unit 120 is sent to read and is interrupted count value MSI_read to MSI counter 230 also by host interface 260.MSI counter 230 deducts up-to-date interruption count value MSI_ACK_count to read and interrupts count value MSI_read and deposit back among the interruption count value MSI_ACK_count again, if interrupt count value this moment still greater than 0 o'clock, MSI generator 240 will produce information signal formula interrupt request singal MSI_IRQ again.
Because native system is a multiple task operating system basically, each unit can send requirement separately, for example different pci bus peripheral hardwares 280 may be simultaneously, continue or not timing is sent the information signal formula and interrupted, so during interrupt service routine of central processing unit 120 beginnings, may have a plurality of systems appointed information to deposit in the Installed System Memory, and the system's appointed information that deposits Installed System Memory in interrupt service routine is carried out in may constantly increase.Utilize the above-mentioned framework of the utility model, can store a plurality of systems appointed information at Installed System Memory, so can in same interrupt service routine, handle a plurality of different system appointed information of different peripheral simultaneously, can comprise the elasticity of interrupting occurrence cause in addition in system's appointed information in addition.
In sum, can put out the disposal route that a kind of support information signal formula of the present utility model is interrupted in order, please refer to Fig. 3 A, Fig. 3 B, Fig. 3 C, Fig. 3 A, Fig. 3 B, Fig. 3 C show the schematic flow sheet of the disposal route that a kind of support information signal formula is interrupted.Disposal route of the present utility model can be applicable in the control chip group of mainboard, this chipset is coupled to pci bus, Installed System Memory and central processing unit, this processing method comprises the following steps: at first execution in step 310, monitor that the internal memory on the pci bus writes transaction, according to the specification that the information signal formula is interrupted, the interrupting information that this internal memory writes transaction is system-specific address and system's appointed information of two character group; Then in step 315, judge when system memory address specified in the interruption information falls within the reservation interrupt address scope of Installed System Memory, just carry out interrupt handling routine (step 320 is following).Above-mentioned interrupt handling routine comprises the following steps: at first execution in step 320, write the interrupting information of transaction according to internal memory, in system's appointed information writing system internal memory, that is to say, write the interrupting information of transaction earlier according to internal memory, produce the actual address that writes, again internal memory is write actual the writing in the address of system's appointed information writing system internal memory of transaction.Execution in step 325 then, behind system's appointed information success writing system internal memory, increase the value of interrupting count value; Then execution in step 330 is interrupted count value according to this, produces the hardware interrupts request to central processing unit; Being exactly that central processing unit is actual at last removes to handle interrupt service routine.
Please refer to Fig. 3 B, the disposal route that a kind of support information signal formula of foundation preferred embodiment of the present utility model is interrupted, wherein in the interrupt handling routine, the processing of relevant central processing unit aspect, comprise the following steps: at first execution in step 340, read the interruption count value, and save as and send the interruption count value; Then execution in step 345 is just interrupted count value, all system's appointed information of the reservation interrupt address scope of scanning system internal memory according to this; Execution in step 350 then, handle all system's appointed information that keep in the interrupt address scope, and calculate the number of system's appointed information of having handled, become and read the interruption count value; In step 351, judge to have sent and whether interrupt count value greater than reading the interruption count value; To interrupt count value bigger if sent, then in step 353, will read and interrupt count value and be modified to and send the interruption count value; And last execution in step 355, send to read and interrupt count value and break in service end signal, with notice MSI controller, make it will interrupt count value and deduct and read the interruption count value interruption count value of restoring.
Please refer to Fig. 3 C, in the utility model the foregoing description, the subsequent processing steps of relevant MSI controller aspect, comprise the following steps: at first in step 360, send the interruption count value, then in step 365, wait receives reading of coming from the central processing unit aspect and interrupts count value and break in service end signal, execution in step 370 then, up-to-date interruption count value deducted to read interrupt count value and deposit back again in the interruption count value, if judge this moment when interrupting count value still greater than 0 (step 375), with regard to execution in step 380, produce information signal formula interrupt request singal again, begin most, continue to monitor that the internal memory on the pci bus writes transaction otherwise get back to.
Be familiar with this operator when knowing, above-mentioned steps 351 has read the step of interrupting count value with the correction that step 353 is reached, and can omit.Replace, utilize in step 370, deduct the greater among MSI_read and the MSI_send, also can reach the purpose of correction interrupting count value.
Though the utility model with a preferred embodiment openly as above; right its is not in order to limit the utility model; anyly be familiar with this operator; in not breaking away from spirit and scope of the present utility model; when being used for a variety of modifications and variations, therefore protection domain of the present utility model is as the criterion when looking the accompanying Claim book person of defining.
Claims (13)
1. information signal formula interruptable controller, can be applicable to a system, this system comprises a chipset, a pci bus and an Installed System Memory, this chipset is coupled to this pci bus and this Installed System Memory, this chipset comprises a dynamic RAM Controller, a host interface and an interruptable controller, it is characterized in that: this information signal formula interruptable controller comprises:
One information signal formula is interrupted detector, be coupled to this pci bus and this dynamic RAM Controller, in order to monitor that the internal memory on this pci bus writes transaction, when the address that this internal memory writes transaction is positioned at one when keeping the interrupt address scope, one system's appointed information is write this Installed System Memory through this dynamic RAM Controller, send an information signal formula interruption acknowledge signal again;
One information signal formula is interrupted counter, be coupled to this information signal formula and interrupt detector and this host interface, form an interruption calculated value in order to receive and to count this information signal formula interruption acknowledge signal, and should interrupt count value according to this host interface and become one and sent the interruption count value, and send and send the interruption count value;
One information signal formula is interrupted generator, be coupled to this information signal formula and interrupt counter and this interruptable controller, in order to interrupt count value according to this, produce an information signal formula interrupt request singal to this interruptable controller, make this interruptable controller produce an interrupt request singal;
Wherein this reservation interrupt address scope is positioned at the address realm of this Installed System Memory.
2. information signal formula interruptable controller as claimed in claim 1, it is characterized in that: wherein this chipset also is coupled to a central processing unit, and this information signal formula interruption generator also is coupled to this host interface, after this central processing unit was handled this system's appointed information, this central processing unit is sent a break in service end signal to this information signal formula interruption generator and and has been read the interruption count value to this information signal formula interruption counter by this host interface.
3. information signal formula interruptable controller as claimed in claim 1, it is characterized in that: wherein this chipset also is coupled to a central processing unit, and this central processing unit is obtained and is sent the interruption count value by this host interface.
4. information signal formula interruptable controller as claimed in claim 1, it is characterized in that: wherein this information signal formula is interrupted detector writes transaction according to this internal memory a interrupting information, produce an actual address that writes, again by this dynamic RAM Controller, this system's appointed information that this internal memory is write transaction writes this actual writing in the address of this Installed System Memory.
5. information signal formula interruptable controller as claimed in claim 1 is characterized in that: wherein this internal memory writes a system-specific address and this system's appointed information that this interrupting information of transaction is a pair of character group.
6. the chipset that interrupts of a support information signal formula, this chipset is coupled to a pci bus, a central processing unit and an Installed System Memory, it is characterized in that: this chipset comprises:
One dynamic RAM Controller is coupled to this Installed System Memory in order to control and this Installed System Memory of access;
One host interface is coupled to this central processing unit, in order to as the control interface between this chipset and this central processing unit;
One interruptable controller is coupled to this host interface, in order to produce an interrupt request singal to this central processing unit, makes this central processing unit activate an interrupt service routine;
One information signal formula interruptable controller, be coupled to this pci bus, this dynamic RAM Controller, this host interface and this interruptable controller, in order to monitor that the internal memory on this pci bus writes transaction, when the address that this internal memory writes transaction is positioned at one when keeping the interrupt address scope, with system's appointed information in this dynamic RAM Controller writes this Installed System Memory, send an information signal formula interrupt request singal again, make this interruptable controller produce this interrupt request singal;
Wherein this reservation interrupt address scope is positioned at the address realm of this Installed System Memory.
7. chipset as claimed in claim 6 is characterized in that: this information signal formula interruptable controller comprises:
One information signal formula is interrupted detector, be coupled to this pci bus and this dynamic RAM Controller, in order to monitor that this internal memory writes transaction, when this internal memory writes that specified address is positioned at this reservation interrupt address scope in the interrupting information of transaction, this system's appointed information after this dynamic RAM Controller writes this Installed System Memory, is sent an information signal formula interruption acknowledge signal again;
One information signal formula is interrupted counter, be coupled to this information signal formula and interrupt detector and this host interface, form an interruption count value in order to receive and to count this information signal formula interruption acknowledge signal, and should interrupt count value according to this host interface and become one and sent the interruption count value, and send and send the interruption count value;
One information signal formula is interrupted generator, be coupled to this information signal formula and interrupt counter and this interruptable controller, in order to interrupt count value according to this, produce this information signal formula interrupt request singal to this interruptable controller, make this interruptable controller produce this interrupt request singal.
8. chipset as claimed in claim 7, it is characterized in that: wherein this information signal formula interruption generator also is coupled to this host interface, after this central processing unit was handled this system's appointed information, this central processing unit is sent a break in service end signal to this information signal formula interruption generator and and has been read the interruption count value to this information signal formula interruption counter by this host interface.
9. chipset as claimed in claim 7 is characterized in that: this central processing unit is obtained this and has been sent the interruption count value by this host interface.
10. chipset as claimed in claim 7, it is characterized in that: this information signal formula is interrupted detector writes transaction according to this internal memory this interrupting information, produce an actual address that writes, again by this dynamic RAM Controller, this system's appointed information that this internal memory is write transaction writes this actual writing in the address of this Installed System Memory.
11. chipset as claimed in claim 7, it is characterized in that: this central processing unit reads this earlier and has sent the interruption count value, sent the interruption count value according to this again, scan this reservation interrupt address scope of this Installed System Memory, then handle the number of all these system's appointed information in this reservation interrupt address scope, and become one and read the interruption count value, send this at last and read the interruption count value.
12. chipset as claimed in claim 11 is characterized in that: judge to read when this central processing unit and interrupt count value and interrupt count value and equal to send the interruption count value less than sending when interrupting count value, allow to read.
13. chipset as claimed in claim 11 is characterized in that: this information signal formula is interrupted counter to be allowed this interruptions count value equal this interruptions count value to deduct this and read the interruption count value and this has sent the maximum of interruption count value.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 01259679 CN2528080Y (en) | 2001-09-28 | 2001-09-28 | Chip group and controller for supporting information signal interruption |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 01259679 CN2528080Y (en) | 2001-09-28 | 2001-09-28 | Chip group and controller for supporting information signal interruption |
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100382061C (en) * | 2004-01-14 | 2008-04-16 | 国际商业机器公司 | Method and apparatus for counting interrupts by type |
| CN100416530C (en) * | 2003-08-09 | 2008-09-03 | 得州仪器公司 | System for signaling serialized interrupts using message signaled interrupts |
| CN100430868C (en) * | 2005-12-26 | 2008-11-05 | 威盛电子股份有限公司 | Data buffer system and rending method of data buffer device |
| CN101000796B (en) * | 2006-01-12 | 2010-06-09 | 旺玖科技股份有限公司 | Control module and method of double data speed synchronous dynamic RAM |
| CN111880611A (en) * | 2020-06-19 | 2020-11-03 | 深圳宏芯宇电子股份有限公司 | Server for fast transaction and fast transaction data processing method |
-
2001
- 2001-09-28 CN CN 01259679 patent/CN2528080Y/en not_active Expired - Lifetime
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100416530C (en) * | 2003-08-09 | 2008-09-03 | 得州仪器公司 | System for signaling serialized interrupts using message signaled interrupts |
| CN100382061C (en) * | 2004-01-14 | 2008-04-16 | 国际商业机器公司 | Method and apparatus for counting interrupts by type |
| CN100430868C (en) * | 2005-12-26 | 2008-11-05 | 威盛电子股份有限公司 | Data buffer system and rending method of data buffer device |
| CN101000796B (en) * | 2006-01-12 | 2010-06-09 | 旺玖科技股份有限公司 | Control module and method of double data speed synchronous dynamic RAM |
| CN111880611A (en) * | 2020-06-19 | 2020-11-03 | 深圳宏芯宇电子股份有限公司 | Server for fast transaction and fast transaction data processing method |
| CN111880611B (en) * | 2020-06-19 | 2022-06-28 | 深圳宏芯宇电子股份有限公司 | Server for quick transaction and quick transaction data processing method |
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