CN2520528Y

CN2520528Y - Bridging system of access of shared system resource

Info

Publication number: CN2520528Y
Application number: CN 01264317
Authority: CN
Inventors: 林振荣
Original assignee: Via Technologies Inc
Current assignee: Via Technologies Inc
Priority date: 2001-09-27
Filing date: 2001-09-27
Publication date: 2002-11-13
Anticipated expiration: 2011-09-27

Abstract

The utility model provides a bridge connection system, which accesses sharing system resources. The utility model comprises a plurality of master control units that can send out a plurality of writing and reading exchanges. A first data bus is coupled with the master control units. A bridge is coupled with the first data bus to transmit the writing and reading exchanges. A second data bus is coupled with the bridge. A chipset is coupled with the second date bus and the sharing system resources, which is used to choose the writing and reading exchanges sent out by the special master control units to access the sharing system resources.

Description

The bridge system of access shared system resource

Technical field

The utility model relates to a kind of bridge system, and particularly relevant a kind of multinomial master control set is by the bridge system of high-speed bus access shared system resource.

Background technology

Known multinomial master control (Master) device is if desire the system resource (for example Installed System Memory) that access one is shared, and its practice is by a conventional bus, as pci bus, and the system resource of coming access to share.Fig. 1 shows the synoptic diagram of known a kind of multinomial master control set access system memory device.Please refer to Fig. 1, central processing unit 10 is couple to pci bus 14 through chipset (chipset) 12, provides 32 (bit), the access speed of 33MHz.And pci bus 14 couples the master control set 16 (external unit of pci bus compatibility) of a plurality of pci bus compatibilities again.Each master control set all can be sent request signal, and (moderator in the chipset 12 (arbiter) then can be sent approval signal, and (grant GNT) gives master control set, agrees to use pci bus 14 for request, REQ) request use pci bus 14.The master control set of obtaining pci bus 14 controls then can come access system internal memory 11 through chipset 12.In addition, this system provides 64 (bit) by AGP (Accelerated Graphics Port is called for short AGP) bus 18, the access speed of 66MHz is come access figure OverDrive Processor ODP 13, in order to provide display device required image information apace.

Yet in general servo-drive system, owing to do not need the function of image information access speed fast and acceleration, so the image information that provides display device required is provided with the interface of pci bus compatibility display device.So the framework of AGP bus is in servo-drive system and fail to be used more fully, if and can be under existing framework, on the AGP bus, provide faster transmission speed to the master control set of pci bus, not only can utilize the resource of system fully, effectively the performance of elevator system.

And, known chipset is handled the access request that pci bus sends with first come first served basis, and the transmission of data mainly is to be right after same bus trade after request is sent in the cycle, so the latent period waste of time that pending data such as can cause to be ready for.In addition, this mode can't satisfy the characteristic that some access transmission has high priority memory access power.Existing high-speed bus, as the AGP bus, the method that adopts access request and access data to separate, and use pipeline (pipeline) internal memory to write and read operation with degree of depth, so that two-forty and efficient data transmission to be provided.Because its access request has the attribute of high low priority, allows control chip group be able to some access work of priority processing.In addition, such high-speed bus also arrange in pairs or groups removing (Flush) with intercept (Fence) signal, guaranteed the execution sequence of some access work.But having the system of a plurality of master control sets,, come access shared system resource, how to guarantee the correctness of access sequence, just become a problem that is worth research by this kind high-speed bus.

Summary of the invention

The utility model proposes a kind of bridge system of access shared system resource, comprising: it can send a plurality of master control sets and a plurality ofly write transaction and read transaction; First bus is coupled to master control set; Bridge is coupled to first bus and reads transaction and write transaction in order to transmission; Second bus is coupled to bridge; And chipset is coupled to second bus and shared system resource, comes access shared system resource in order to select specific master control set sent read transaction and write transaction.

Description of drawings

Fig. 1 shows the system schematic of known multinomial aggressive device access one shared memory device;

Fig. 2 illustrates a kind of system schematic by AGP bus access shared drive of the utility model preferred embodiment;

Fig. 3 shows the transaction ordering synoptic diagram according to the control chip group internal queues of the utility model preferred embodiment.The drawing reference numeral explanation:

10,110 central processing units

11,120 Installed System Memories

12,200 chipsets

13 figure OverDrive Processor ODPs

The 14PCI bus

16 master control sets

18,220 AGP buses

200 chipsets

230 bridges

240PCI bus I

245PCI bus II

260 first master control sets

270 second master control sets

280 the 3rd master control sets

310 read formation

312 first devices read formation

314 second devices read formation

316 the 3rd devices read formation

320 write formation

322 first devices write formation

324 second devices write formation

326 the 3rd devices write formation

Embodiment

Fig. 2 illustrates a kind of system schematic by AGP bus access shared drive of the utility model preferred embodiment.Chipset 200 is coupled to central processing unit 110 and Installed System Memory 120.And the access speed of 33MHz by the pci bus I 240 that chipset 200 has, is provided 32 (bit).And, the utility model couples a pci bus to AGP bridge 230 on AGP bus 220, make on the pci bus II245 first, second, also can come Installed System Memory 120 is done data trade with the 3rd master control set 260,270,280 through AGP bus 220 and chipset 200, certainly present embodiment only provides three master control sets to illustrate that as example the utility model does not limit the number of master control set.

And, because the AGP bus provides 64 (bit), the access speed of 66MHz, thus can provide the speed master control set of pci bus compatibility faster at pci bus II245, therefore, the overall performance of elevator system effectively.

When any one master control set will begin an access transaction, at first its pci bus II that couples 245 is sent request signal, and after obtaining agreement, this access transaction is through bridge 230 intermediaries, again by AGP bus 220, what be placed in control chip group 200 writes or reads ordering in the waiting list (Waiting Queue).This is because Installed System Memory is shared by a plurality of master control sets, regardless of what master control sets being arranged or by the access request which master control set sent, all must arriving in the waiting list at last and wait, with the shared system internal memory 120 of access.

Because pci bus II245 has a plurality of external units (master control set) 260.And in order to want the memory device of access system, access that these external units (master control set) 260 are sent transaction all can be placed within the waiting list in the chipset 200.And how to determine the precedence of these transaction, and make memory device can therefore not produce the mistake of data access, the example of a solution below will be provided.

In sort method, the transaction of the external unit that each is different is all given its master control set encoded radio (Master ID) and is belonged to which external unit (master control set) and initiate in order to distinguish this transaction.And each transaction for example writes transaction or reads transaction again according to its attribute (Attribute), gives a transaction encoded radio (Transaction ID).

Its arranged mode then according to current transaction attribute with and the transaction attribute of last pen decide (following all being represented as with R read transaction, and W is represented as and writes transaction).And the first stroke transaction encoded radio begins by 0, and when current transaction was R for the last transaction of R, the encoded radio of then concluding the business added 1.When current transaction was W for the last transaction of R, the encoded radio of then concluding the business added 0.When current transaction was R for the last transaction of W, the encoded radio of then concluding the business added 1.When current transaction was W for the last transaction of W, the encoded radio of then concluding the business added 0.

For instance, when three master control sets are arranged on the pci bus II, its access of sending transaction is delivered to chipset through bridge and is R2-R1-R2-R3-W1-W2-R1-W1-R1-R3-W2-W2-R2-W3-W3-R3 (numeral behind the letter is then represented particular outer equipment, just the master control set encoded radio) in regular turn.Therefore, the first stroke transaction R initiates (the master control set encoded radio is 2) by second external unit and its transaction encoded radio is made as 0, second transaction R representative adds 1 by first external unit initiation (the master control set encoded radio is 1) and this transaction encoded radio becomes 1, the 3rd transaction R initiates (the master control set encoded radio is 2) and this transaction encoded radio by second external unit and adds 1 and become 2, the 4th transaction R initiates (the master control set encoded radio is 3) and this transaction encoded radio by the 3rd external unit and adds 1 and become 3, the 5th transaction W adds 1 by first external unit initiation (the master control set encoded radio is 1) and this transaction encoded radio becomes 4, the 6th transaction W initiates (the master control set encoded radio is 2) and this transaction encoded radio by second external unit and adds 0 and become 4, the 7th transaction R adds 0 by first external unit initiation (the master control set encoded radio is 1) and this transaction encoded radio becomes 4, the rest may be inferred, and the transaction encoded radio that can obtain All Activity at last is 0-1-2-3-4-4-4-5-5-6-7-7-7-8-8-8 in regular turn.

Fig. 3 illustrates the synoptic diagram that writes waiting list and read waiting list according to the chipset inside of the foregoing description.Transaction by the AGP bus is sent can place reading formation 310 and writing formation 320 in the chipset respectively according to its attribute.And except address and data (not illustrating) that exchange needs, reading formation 310 and writing master control set encoded radio and the transaction encoded radio that formation 320 must store every transaction again in chipset.Then, chipset can deposit different master control sets respectively in according to the content that the master control set encoded radio will read formation 310 and write formation 320 and reads formation and write formation.According to present embodiment, first master control set reads formation 312 and writes formation 322 that to store the master control set encoded radio respectively be 1 read transaction and write transaction.In like manner, second master control set reads formation 314 and writes formation 324 that to store the master control set encoded radio respectively be 2 read transaction and write transaction, and the 3rd master control set reads formation 316 and write formation 326 that to store the master control set encoded radio respectively be 3 read transaction and write transaction.

Therefore, the transaction that each master control set sent can be distinguished as shown in the figure, then, can carry out the transaction of specific master control set and Installed System Memory according to the priority order of master control set in regular turn.

The trading order of specific master control set and Installed System Memory then decides according to the transaction encoded radio, for instance, first master control set read have in the formation 312 the transaction encoded radio be 1,4, with 5 the transaction of reading, first master control set writes that the transaction encoded radio is arranged in the formation 322 is 4, with 5 the transaction that writes.When first master control set begins to conclude the business with Installed System Memory, begin by the transaction of transaction encoded radio minimum, the encoded radio of therefore concluding the business is that 1 R concludes the business with Installed System Memory earlier.And the transaction encoded radio in first device reads formation 312 and writes formation 322 is carried out the transaction of W earlier when identical, and therefore, first master control set is R-W-R-W-R to the performed trading order of Installed System Memory in regular turn.Therefore, the transaction of being initiated by first master control set can't be read formation and writes formation and cause the entanglement of transaction order because of being respectively placed on, and causes the mistake of data.

In like manner, second master control set is R-R-W-W-W-R to the performed trading order of Installed System Memory in regular turn.The 3rd master control set is R-R-W-W-R to the performed trading order of Installed System Memory in regular turn.

Because each master control set all has other right of priority, so chipset can be carried out transaction according to the right of priority of master control set, trading order can't be therefore and entanglement, the reading and writing data that leads to errors.

Therefore, present embodiment is by AGP bus 220 at a high speed, and the transfer rate that multinomial master control set (260,270 and 280) can be higher and the utmost point be the shared memory device 110 of access efficiently.In addition, the utility model can arrange in pairs or groups removing (Flush) that AGP bus 220 supported with intercept (Fence) request, and utilize the characteristic of transaction encoded radio, guarantee the order that some access transaction is done.When receiving the removing request, the transaction request of all low priorities is finished earlier, continue this again and remove the following transaction request of request; After receiving the request of obstruct, do not allow this obstruct request transaction request afterwards, intercept the execution earlier of request transaction request before prior to this.

As be familiar with this operator and can know, master control set is couple to pci bus in the present embodiment, but the utility model and the non-limiting pci bus that is used in, the utility model does not even necessarily need this bus, and directly with bridge on the plurality of active devices bridge joint, as long as the mechanism of a plurality of master control set runnings can be provided.

Though the utility model with a preferred embodiment openly as above; so be not in order to limit the utility model; anyly be familiar with this operator; in not breaking away from spirit and scope of the present utility model; can be used for a variety of modifications and variations, therefore protection domain of the present utility model when with claim the person of being defined be as the criterion.

Claims

1. the bridge system of an access shared system resource is characterized in that: comprising:

At least one master control set, this at least one master control set can send and a plurality ofly write transaction and a plurality ofly read transaction;

One first bus is coupled to this at least one master control set;

One bridge is coupled to this first bus, in order to transmit those read the transaction and those write transaction;

One second bus is coupled to this bridge;

One chipset is coupled to this second bus and this shared system resource, in order to select this at least one master control set wherein one sent those read transaction and those and write transaction and come this shared system resource of access.

2. bridge system as claimed in claim 1 is characterized in that: this first bus is a pci bus.

3. bridge system as claimed in claim 1 is characterized in that: this second bus is an AGP bus.

4. bridge system as claimed in claim 1 is characterized in that: this chipset one bus is a pci bus.

5. bridge system as claimed in claim 1 is characterized in that: each read the transaction and each write transaction all have one the transaction encoded radio.

6. bridge system as claimed in claim 5 is characterized in that: each reads transaction and each writes transaction, all has the master control set encoded radio of corresponding at least one master control set.

7. bridge system as claimed in claim 5 is characterized in that: wherein this chipset comprises:

One reads formation, in order to store those those master control set encoded radios that read transaction and those transaction encoded radios;

One writes formation, in order to store those those master control set encoded radios that write transaction and those transaction encoded radios;

A plurality of master control sets read formation, and each this master control set reads formation and stores and to have pairing those of those identical master control set encoded radios and read those transaction encoded radios of transaction;

A plurality of master control sets write formation, and each this master control set writes formation and stores and to have pairing those of those identical master control set encoded radios and write those transaction encoded radios of transaction.