CN2502461Y - Line collector based on two-line two-state communication bus system - Google Patents
Line collector based on two-line two-state communication bus system Download PDFInfo
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Abstract
The utility model relates to a line collector based on two-line two-state communication bus system, which comprises a plurality of level switching circuits with communication bus joint, a logic controller with multi inputs and outputs, and an anti-bus-shaking circuit corresponding to each level switching circuit. When all the communication bus joints of all the level switching circuits are in the recessive position, and the logic controller makes the communication bus joints of the other level switching circuits in recessive position. If the communication joint for a certain level switching circuit is in the dominant position, the logic controller makes the communication bus joints of the other level switching circuits in dominant position. The anti-bus-shaking circuit is to prevent bus from producing shaking when the output state of the logic controller changes. The utility model adopts the non-intelligent hardware structure to realize the function of the intelligent line collector software in the prior art, which avoids the system paralysis phenomenon caused by the failure of the running procedure for the existed intelligent line collector. The utility model is mainly used for the communication bus system.
Description
Technical field
The utility model relates to a kind of hub, particularly based on the hub of two line binary states communication bus systems.
Background technology
Development along with network and automation industry, share in order to realize field apparatus interconnection and data resource, formed multiple standard for Fieldbus, as foundation bus (FF), CAN (Control AreaNetwork) bus, LONworks bus, ControlNet bus standard etc., these buses are widely used in fields such as Industry Control, intelligent building and home automation at present.
In the bus, the binary states bus communication uses comparatively general at the scene.So-called binary states bus communication is meant to have two kinds of complementary logics on the bus: dominance position and recessive position, and when having only the dominance position to send, the state on the bus is the dominance position; When having only recessive position to send, the state on the bus is recessive position; When the dominance position sent simultaneously with recessive position, the state on the bus was the dominance position.The dominance position represents that with logical zero recessive position is represented with logical one.Such bus exists certain restriction in transmission range and node number.With the CAN bus is example, and its direct transmission range is 40m (1Mbps)～10km (5kbps) farthest, and the node number mostly is 110 most.Because the direct transmission range of communication exists certain restriction, the communication distance lengthening just need be passed through repeater if want; If in a larger system, automatic building control system for example, the control website remote and that disperse that wants to be separated by is linked on the system bus jointly, at this moment just be a long felt need for hub, the website of respectively controlling that disperses can be divided into bus network of several network segments compositions by hub.But present repeater and hub are smart machines, stable and the reliability of the reliability of system communication and real-time and repeater or hubware is closely related, in case the program generation problem of repeater or hub, will influence whole system can't operate as normal, so this is a quite crucial problem of system communication.
The utility model content
At the deficiency that exists in the background technology, the utility model provides a kind of hub based on two line binary states communication bus systems, hub of the present utility model adopts non intelligent hardware to realize the function of existing hub, to improve the reliability and stability of its work.
The utility model comprises a plurality of level shifting circuits, and described level shifting circuit has a communication bus interface, an input and an output; Its design feature is: also comprise having the logic controller that multichannel input and multichannel are exported, and corresponding to a plurality of anti-bus oscillating circuit of each level shifting circuit; The output of each level shifting circuit is connected with one tunnel input of described logic controller, one tunnel output of logic controller is connected with the input of the input of a level shifting circuit and corresponding anti-bus oscillating circuit respectively, and the output of each anti-bus oscillating circuit is imported with a road of described logic controller and is connected;
The network segment of only working as the communication bus interface connection of all level shifting circuits is recessive position, and the output of described logic controller is high level entirely; When if the communication bus interface of a certain level shifting circuit is the dominance position, it is the dominance position that described logic controller makes the communication bus interface state of all the other level shifting circuits.
When the output of described logic controller becomes high level by low level, described anti-bus oscillating circuit is exported high level in the certain hour section, in this time period, output is that the output signal of low level level shifting circuit is blocked by described logic controller, produces concussion to prevent external communication bus.
According to technique scheme, described logic controller is made up of a plurality of OR-gates and a plurality of AND gate, and an input of each OR-gate is as one tunnel input of logic controller, and each is exported as a road of logic controller with the output of door; The output of the corresponding anti-bus oscillating circuit with it of the output of level shifting circuit is connected with the input of same OR-gate.
According to technique scheme, described logic controller is a programmable logic chip.
According to technique scheme, described anti-bus oscillating circuit is the single-shot trigger circuit that monostable flipflop is formed; When the triggering input of monostable flipflop occurred by low level to the rising edge of a pulse of high level, the steady Power Generation Road of described singlet was exported high level in the certain hour section.
According to technique scheme, described level shifting circuit comprises the signal chip for driving that is used for the CAN bus, the photoelectrical coupler that is connected with the signal chip for driving.
According to technique scheme; the output of a described photoelectrical coupler is connected with protective circuit; described protective circuit is made of monostable flipflop, and when the communication interface of level shifting circuit was the dominance position for a long time, described protective circuit was blocked the signal of level shifting circuit output.
According to technique scheme, the utility model also comprises Extended Capabilities Port, and described Extended Capabilities Port is electrically connected with described logic controller; By described expansion mouth a plurality of described hubs based on two line binary states communication bus systems are merged and form hub with more communication bus interfaces
The utility model adopts non intelligent hardware configuration to realize the function of the intelligent HUB software of prior art, improve the stability and the reliability of hub work significantly, avoided existing intelligent HUB to cause the phenomenon of systemic breakdown because of working procedure breaks down.The utility model inside is finished by hardware circuit the logical transition of communication between the different segment, so no matter in the same network segment, or the communication of each node in system between the different segment all is real-time.Therefore, utilize the utility model to connect a plurality of network segments, can with the communication data of any one node or the network segment real-time be reflected to other each node or network segment.The utility model also can improve the transmission range of communication, reasonably optimizing communication system structure.
Description of drawings
Fig. 1 is a structured flowchart of the present utility model;
Fig. 2 is the utility model hub circuit schematic diagram with 3 communication bus interfaces;
Fig. 3 constitutes the utility model hub circuit schematic diagram of logic controller for adopting logical circuit;
Fig. 4 is the utility model hub circuit schematic diagram with two communication bus interfaces;
Fig. 5 is the utility model hub circuit schematic diagram with Extended Capabilities Port;
Fig. 6 is the level shifting circuit schematic diagram that is used for the CAN bus;
Fig. 7 is the level shifting circuit schematic diagram that is used for the CAN bus and has protective circuit:
The CAN bus communication system of Fig. 8 for forming with the utility model hub with 3 communication bus interfaces;
The CAN bus communication system of Fig. 9 for having the utility model hub composition of expansion mouth with two;
Embodiment:
With reference to figure 1: hub 4 comprises a plurality of level shifting circuits 2, with level shifting circuit 2 corresponding a plurality of anti-bus oscillating circuits 2, and logic controller 5.Level shifting circuit 2 has a communication bus interface 1, an input and an output, and communication bus interface 1 is used to connect network segment bus.Level shifting circuit 2 converts network segment bus signals to input that hub 4 carries out the required CMOS level of logical operation and delivers to logic controller 5 by output; Perhaps the CMOS level signal that logic controller 5 is exported converts to and is adapted to the required signal of network segment bus.The signal that logic controller 5 initiatively sends according to a certain network segment (dominance position or recessive position) is controlled the state of all the other network segments, and the signal of all network segments is consistent, and promptly is all dominance position or recessive position.
As shown in Figure 2: hub 4 has 3 level shifting circuit 2-1,2-2,2-3, by its communication bus interface 1-1,1-2,1-3 can external 3 network segments.Logic controller 5 is by OR-gate U5A, U5B, U5C, AND gate U1A, U1B, U1C, and resistance R 9, R10, R11 form.Logic controller 5 comes the input of all the other level shifting circuits is controlled according to a certain level shifting circuit master's output.For example: all communication bus interfaces of initial state are recessive position, when the network segment 1 that is connected with communication bus interface 1-1 sends the dominance position, the output M1-RX of level shifting circuit 2-1 is a low level, through or door still be low level behind the U5A, the output of AND gate U1B, U1C also is low level, input M2-TX, the M3-TX of level shifting circuit 2-2,2-3 is low level, the dominance position will appear by the network segment bus that is connected with communication bus interface 1-2,1-3 after the level conversion, and promptly identical with the network segment 1 state; When the dominance position appears in the network segment 2 or the network segment 3, in like manner, logic controller 5 will make all the other network segments identical with the network segment 2 or the network segment 3 states.
In the network system communication process, the state of network segment bus always constantly changes between dominance position and recessive position, and in the moment that network segment bus changes the bus reforming phenomena may take place.As: initial condition is that the network segment 1 initiatively sends the dominance position, and the state of the network segment 2, the 3 reflection network segments 1 is the dominance position; This moment, the network segment 1 will initiatively send the recessiveness position, and the state on the network segment 2,3 should become recessive position state immediately in theory, but in fact because life period delay on the circuit just becomes recessive state so the state on the network segment 2,3 can postpone certain hour.In delay time, still keep original dominance condition on the network segment 2,3, therefore, this state will be reflected to other network segment under the control of controller 5, just the network segment 1, at this moment the dominance condition that occurs on the network segment 1 bus is false dominance, and the network segment is initiatively sending recessive state 1 this moment, and this will cause producing on the bus reforming phenomena.But this phenomenon can not take place by initiatively sending recessive position at a certain network segment in the process that initiatively sends the dominance position.
Anti-bus oscillating circuit 3 constitutes single-shot trigger circuit by monostable flipflop, inverter, OR-gate, resistance and electric capacity; only when a certain network segment by initiatively sending the dominance position when initiatively sending the variation of recessive position, the corresponding anti-bus oscillating circuit of all the other network segments shields.As: initial condition is that the network segment 1 initiatively sends the dominance position, and the state of the network segment 2, the 3 reflection network segments 1 is the dominance position, and input M2-TX, the M3-TX of level shifting circuit 2-2,2-3 is low level; This moment, the network segment 1 active sent recessive position, under the control of controller 5, input M2-TX, the M3-TX of level shifting circuit 2-2,2-3 become high level, a rising edge of a pulse appears in the input of anti-bus oscillating circuit 3-2,3-3 simultaneously, this rising edge will make high level pulse that pulsewidth is constant RC of monostable flipflop U4B, U4C output, respectively through or door U3B, U5B and U3D, U5C after export high level, low level signal with its output M2-RX, M3-RX in delay time blocks, and avoids it to be reflected to the network segment 1.
With reference to as Fig. 3: the controller 5 in the structure shown in Figure 2 is replaced by programmable logic chip 5-1, and its model is GAL16V8D, and by programming, programmable logic chip 5-1 realizes the logical operation function of logic controller 5 shown in Figure 2, and its operation principle is identical.
Being illustrated in figure 4 as has increased an Extended Capabilities Port 6 on the basis of Fig. 3, can be connected with the same port of another hub by Extended Capabilities Port 6, thereby two hubs are merged hub that can connect the double network segment of composition.The input RX of Extended Capabilities Port, output TX are connected with the output of controller 5-1.
As shown in Figure 5: hub of the present utility model is to remove a level shifting circuit on structure shown in Figure 3, can only external two network segments, what this structure realized is exactly the function of repeater, can be used as simple prolongation bus transfer apart from the time use.
Fig. 6 is the level shifting circuit that is applicable to the CAN bus, and wherein CAN Bus Interface Chip U6A model is 82C250, also can use the CAN Bus Interface Chip of other model.
Structure shown in Figure 7 is for having increased photoelectrical coupler and protective circuit on the basis of Fig. 6.Optocoupler U7A, U7B isolate transmission in order to carry out photoelectricity between the bus with hub and long Distance Transmission, to avoid that the interference on a certain network segment bus is passed to other network segment by hub.Among the figure by monostable flipflop U8A and resistance R 14; the protective circuit that capacitor C 4 is formed is to influence the protective circuit that other network segment can not operate as normal when breaking down for the bus that prevents this network segment; break down and always present dominance condition as the bus of this network segment; protective circuit can produce a low level by 4 pin of monostable flipflop U8A by recessive state when dominance condition changes; this low level can be kept a period of time (time of delay is by resistance R 14 and capacitor C 4 decisions); during this period of time; state on the bus can freely pass through OR-gate U6; if but exceed during this period of time; still keep dominance condition on the bus; 4 pin of monostable flipflop U8A can become high level; dominance condition on the bus can't pass through OR-gate U6 like this, also just can not pass to other network segment.Therefore, when one of them network segment broke down, other network segment still can operate as normal.The circuit of forming by diode D1, D2 and voltage-stabiliser tube Z1 among the figure, and be to produce too high voltage and damage CAN Bus Interface Chip U6A when bus breaks down in order to prevent by the circuit that diode D3, D4 and voltage-stabiliser tube Z2 form.
As shown in Figure 8, utilize hub bus communication system can be divided into the more network segment, the node that can concentrate be connected in the same network segment like this, and the node division that will disperse is to the different network segments, for the configuration of system provides the more scheme of optimization.And because the communication failure of one of them network segment can not influence other network segment, this has just reduced the harm that communication failure brings whole system greatly, has improved the reliability of system.
Be illustrated in figure 9 as the expansion using method of the utility model hub.The Extended Capabilities Port of two CAN hubs is connected, two CAN hubs can be merged and form the CAN hub 8 that can connect the double amount network segment.
The communication bus interface of the utility model hub is not limited in 3, can have a plurality ofly as required, and its operation principle is identical with method.
Claims (7)
1, a kind of hub based on two line binary states communication bus systems comprises a plurality of level shifting circuits, and described level shifting circuit has a communication bus interface, an input and an output; It is characterized in that also comprising to have the logic controller that multichannel input and multichannel are exported, and corresponding to a plurality of anti-bus oscillating circuit of each level shifting circuit; The output of each level shifting circuit is connected with one tunnel input of described logic controller, one tunnel output of logic controller is connected with the input of the input of a level shifting circuit and corresponding anti-bus oscillating circuit respectively, and the output of each anti-bus oscillating circuit is imported with a road of described logic controller and is connected;
The network segment of only working as the communication bus interface connection of all level shifting circuits is recessive position, and the output of described logic controller is high level entirely; When if the communication bus interface of a certain level shifting circuit is the dominance position, it is the dominance position that described logic controller makes the communication bus interface state of all the other level shifting circuits.
When the output of described logic controller becomes high level by low level, described anti-bus oscillating circuit is exported high level in the certain hour section, in this time period, output is that the output signal of low level level shifting circuit is blocked by described logic controller, produces concussion to prevent external communication bus.
2, the hub based on two line binary states communication bus systems according to claim 1, it is characterized in that described logic controller is made up of a plurality of OR-gates and a plurality of AND gate, one input of each OR-gate is as one tunnel input of logic controller, and each is exported as a road of logic controller with the output of door; The output of the corresponding anti-bus oscillating circuit with it of the output of level shifting circuit is connected with the input of same OR-gate.
3, the hub based on two line binary states communication bus systems according to claim 1 is characterized in that described logic controller is a programmable logic chip.
4, the hub based on two line binary states communication bus systems according to claim 1 is characterized in that described anti-bus oscillating circuit is the single-shot trigger circuit that monostable flipflop is formed; When the triggering input of monostable flipflop occurred by low level to the rising edge of a pulse of high level, the steady Power Generation Road of described singlet was exported high level in the certain hour section.
5, the hub based on two line binary states communication bus systems according to claim 1 is characterized in that described level shifting circuit comprises the signal chip for driving that is used for the CAN bus, the photoelectrical coupler that is connected with the signal chip for driving.
6, the hub based on two line binary states communication bus systems according to claim 5; the output that it is characterized in that a described photoelectrical coupler is connected with protective circuit; described protective circuit is made of monostable flipflop; when the communication interface of level shifting circuit was the dominance position for a long time, described protective circuit was blocked the signal of level shifting circuit output.
7, according to claim 1,2,3,4,5 or 6 described hubs based on two line binary states communication bus systems, it is characterized in that also comprising Extended Capabilities Port, described Extended Capabilities Port is electrically connected with described logic controller; By described expansion mouth a plurality of described hubs based on two line binary states communication bus systems are merged and form hub with more communication bus interfaces.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 01270231 CN2502461Y (en) | 2001-11-05 | 2001-11-05 | Line collector based on two-line two-state communication bus system |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 01270231 CN2502461Y (en) | 2001-11-05 | 2001-11-05 | Line collector based on two-line two-state communication bus system |
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| Publication Number | Publication Date |
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| CN2502461Y true CN2502461Y (en) | 2002-07-24 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN 01270231 Expired - Fee Related CN2502461Y (en) | 2001-11-05 | 2001-11-05 | Line collector based on two-line two-state communication bus system |
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- 2001-11-05 CN CN 01270231 patent/CN2502461Y/en not_active Expired - Fee Related
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Owner name: 2907, TOWER A, QINGHUATONGFANGKEJI PLAZA, BEIJING Free format text: FORMER NAME OR ADDRESS: 2670 MAILBOX, BEIJING CITY 100084 |
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