CN2492885Y - Arithmetic logic unit with frame memory - Google Patents

Arithmetic logic unit with frame memory Download PDF

Info

Publication number
CN2492885Y
CN2492885Y CN 01255558 CN01255558U CN2492885Y CN 2492885 Y CN2492885 Y CN 2492885Y CN 01255558 CN01255558 CN 01255558 CN 01255558 U CN01255558 U CN 01255558U CN 2492885 Y CN2492885 Y CN 2492885Y
Authority
CN
China
Prior art keywords
frame memory
signal
data
input
arithmetic logic
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
CN 01255558
Other languages
Chinese (zh)
Inventor
牟轩沁
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Keda'en Science & Technology Co Ltd Shenzhen
Original Assignee
Keda'en Science & Technology Co Ltd Shenzhen
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Keda'en Science & Technology Co Ltd Shenzhen filed Critical Keda'en Science & Technology Co Ltd Shenzhen
Priority to CN 01255558 priority Critical patent/CN2492885Y/en
Application granted granted Critical
Publication of CN2492885Y publication Critical patent/CN2492885Y/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Images

Landscapes

  • Image Processing (AREA)

Abstract

The utility model discloses an arithmetic logic unit with a frame memory. The image data input and output ends of the arithmetic logic unit are respectively connected with the input and output signals via a trigger. The frame memory is an image memory that automatically organizes data in a frame structure, the address signal end of the frame memory is connected with a counter, which automatically generates a frame memory address according to an imported video synchronization clock signal, the data output end of the frame memory is connected with the template data input end of the arithmetic logic unit via a drive, and an input signal connected with the data input end of the frame memory via the drive provides data input to the data input end. The arithmetic logic unit can realize different arithmetic logic operations by the method of programming, and a signal selection operation mode is selected by an operation mode, thus realizing an arithmetic logic operation of the frame memory data and the input data automatically according to the imported video synchronization clock signal.

Description

The ALU of band frame memory
Technical field:
The utility model patent relates to a kind of ALU with frame memory.
Background technology:
ALU (Arithmetic Logic Unit, be called for short ALU) is a kind of common computing circuit unit, be used for by circuit realize the input data logical operation (with or, non-) and arithmetical operation (add, subtract, multiplication and division) and the result exported.At present, existing ALU only can carry out computing to simple unstructured data, and for structural data, as view data, general ALU can not differentiate structured messages such as " OK ", " field ", " frame " of its data, and ALU is not with storage unit.
Structural datas such as view data are called frame memory (Frame Store) by the tissue storage of its structured data.In the process that structured data is handled in real time, the computing of jumbo structural data is all undertaken by its structure synchronizing information.In the practical application, in real-time video image processing system, need therefore need before computing, image and template data be stored in the frame memory, when computing, carry out computing by the audio video synchronization clock signal with view data frame by frame for unit carries out computing.If adopt general ALU, need additional peripheral circuitry to carry out synchro control, need extra sequential, both caused the system architecture complexity thus, influence the real-time of system's operation again.
Summary of the invention:
The purpose of this utility model is exactly in order to overcome the above problems, and a kind of ALU that view data is handled in real time that is used for is provided, and supports the structuring data by " frame " computing.
The utility model realizes that the scheme of above-mentioned purpose is: a kind of ALU with frame memory, comprise arithmetical unit, and the view data input of described arithmetical unit, output terminal link to each other with output signal with input signal by trigger respectively; It is characterized in that: also comprise frame memory, described frame memory be one with data by the self-organzing video memory of frame structure, its address signal end links to each other with counter, counter is according to the automatic delta frame storage address of audio video synchronization clock signal of input, its data output end links to each other with the template data input end of arithmetical unit by driver, its data input pin is that input signal is attached thereto by driver, for it provides the data input.
Adopt the beneficial effect of above scheme: because ALU inside has jumbo frame memory, under the clock synchronization of synchronous signals such as " OK ", " field ", " frame ", can from frame memory, read the back automatically and carry out arithmetic logical operation being stored in image template data in the frame memory with the real time video image data of input, and export operation result in real time, also can be according to the template data in the content update frame memory of input data.Like this, it is the arithmetic unit that is particularly suitable for the real time video image disposal system, has overcome common ALU and can't realize the shortcoming of carrying out computing by structured messages such as " frames " automatically.
Description of drawings:
Fig. 1 is the utility model functional schematic.
Fig. 2 is the utility model structural representation.
Fig. 3 is the physical circuit synoptic diagram of the utility model embodiment.
Fig. 4 is the application synoptic diagram of the utility model in digital subtraction angiography system.
Embodiment:
Be illustrated in figure 1 as functional schematic of the present utility model.The symbol implication is as follows among the figure:
IN: realtime image data input signal, its sequential are the audio video synchronization clock
OUT: image operation is output signal as a result, and its sequential is the audio video synchronization clock
R/W: frame memory useful signal
Mode: the compute mode control signal, according to the difference of Mode signal, the control arithmetical unit is carried out different arithmetic operations
SEL: signal is selected in output, and when Mode was pass-through state, selecting frame memory was data template straight-through (OUT=M) or input signal straight-through (OUT=L=IN)
CLK: the pixel clock signal in the audio video synchronization clock signal
HS: the line synchronizing signal in the audio video synchronization clock signal
FS: the field sync signal in the audio video synchronization clock signal
HB: the horizontal blanking signal in the audio video synchronization clock signal
VB: the field blanking signal in the audio video synchronization clock signal
Pdata: the address offset amount of frame memory read-write
The Load:Pdata preset signal
Above signal all is input signal except that the OUT signal for ALU.
The function of this ALU is: there is the DRAM frame memory this unit, can store the above view data of a frame.Under the clock synchronization of audio video synchronization clock signals such as CLK, HS, FS, HB, VB, the image data stream of input can carry out computing with the view data in the frame memory in real time, the pattern of computing is according to control signals such as Mode, SEL and decide, according to the control of R/W, whether the decision operation result reads and writes frame memory simultaneously.In addition, the addressing initial offset of frame memory can be passed through Pdata, Load signal sets, can realize the row, column side-play amount by " frame " computing.
Circuit structure diagram as shown in Figure 2, wherein D.FF is a d type flip flop, Buffer is a driver, DRAM is a frame memory, Counter is a counter.
As seen from the figure, this ALU comprises arithmetical unit, frame memory.Described arithmetical unit is a kind of programmable algorithms unit, and its view data input, output terminal link to each other with output signal OUT with input signal IN by trigger respectively; Described frame memory be one with data by the self-organzing video memory of frame structure, its address signal end links to each other with counter Counter, counter is according to the automatic delta frame storage address of audio video synchronization clock signal, its data output end links to each other with the template data input end of arithmetical unit by driver Buffer, and its data output offers arithmetical unit as template data after driving.Its data input pin is that input signal IN is attached thereto by driver Buffer, for it provides the data input.Counter is used for the address signal according to the triggering for generating DRAM frame memory of audio video synchronization clock signal, and the initial value of counter can pass through a d type flip flop setting by Pdata and Load signal.
The operational pattern of arithmetical unit is provided by Mode, can finish different arithmetic operations according to Mode state difference.
Fig. 3 is the physical circuit synoptic diagram of the utility model embodiment.
Fig. 4 is the application synoptic diagram that the utility model is used for having the image processing system that subtracts the shadow function in real time.This application is the X-ray machine digital image system of simplifying, and can realize having an X-rayed last frame and keep, subtracts in real time the shadow function.
In application examples, the ALU module is the ALU of band frame memory of the present utility model; Operational amplifier A MP adjusts incoming video signal, and the separation of the line synchronizing signal of going forward side by side produces audio video synchronization clock signals such as HS, VS, HB, VB, CLK; Analog-digital conversion a/d is with the video image digitizing, as the input signal of ALU module; Digital-to-analog conversion D/A converts the digital signal of ALU output to simulating signal, and is synchronously synthetic simultaneously, forms video output; The pattern control module can be provided with the system works pattern by man-machine interaction mode, and produces required Mode, R/W, SEL, Pdata, Load, the control signal of ALU for line signal and audio video synchronization clock signal according to X-ray machine.
Realize the working method of function:
1, the last frame of perspective keeps (R/W is effective)
In the perspective process (X-ray machine is effective to the line signal), SEL is invalid, output OUT=IN when depositing fluoroscopy images in frame memory in real time; After the perspective process finishes (it is invalid that X-ray machine transfers to for the line signal), SEL is effective, and Mode=is straight-through, and the view data in the frame memory is kept output.
2, subtract shadow (R/W is effective) in real time
The frisket image: system directly deposits the frisket image in frame memory in the process of gathering the frisket image.Straight-through, the SEL=0 of Mode=this moment, then Out=In deposits image in frame memory when selecting input signal straight-through.
Be full of picture: system acquisition is full of picture, and subtracts movie queen's output with the frisket image, and this moment, Mode=subtracted shadow, SEL=1, and then Out=ABS (L-M) subtracts the shadow image and do not refresh, and keeps the frisket image in the frame memory.

Claims (2)

1, a kind of ALU with frame memory comprises arithmetical unit, and the view data input of described arithmetical unit, output terminal link to each other with output signal (OUT) with input signal (IN) by trigger respectively; It is characterized in that: also comprise frame memory, described frame memory be one with data by the self-organzing video memory of frame structure, its address signal end links to each other with counter (Counter), counter is according to the automatic delta frame storage address of audio video synchronization clock signal of input, its data output end links to each other with the template data input end of arithmetical unit by driver (Buffer), its data input pin is that input signal IN is attached thereto by driver (Buffer), for it provides the data input.
2, the ALU of band frame memory as claimed in claim 1 is characterized in that: this ALU can be realized different arithmetic logical operations by the mode of programming, and selects signal (Mode) to select compute mode by compute mode.
CN 01255558 2001-09-07 2001-09-07 Arithmetic logic unit with frame memory Expired - Fee Related CN2492885Y (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN 01255558 CN2492885Y (en) 2001-09-07 2001-09-07 Arithmetic logic unit with frame memory

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN 01255558 CN2492885Y (en) 2001-09-07 2001-09-07 Arithmetic logic unit with frame memory

Publications (1)

Publication Number Publication Date
CN2492885Y true CN2492885Y (en) 2002-05-22

Family

ID=33664674

Family Applications (1)

Application Number Title Priority Date Filing Date
CN 01255558 Expired - Fee Related CN2492885Y (en) 2001-09-07 2001-09-07 Arithmetic logic unit with frame memory

Country Status (1)

Country Link
CN (1) CN2492885Y (en)

Similar Documents

Publication Publication Date Title
US6034733A (en) Timing and control for deinterlacing and enhancement of non-deterministically arriving interlaced video data
US4602275A (en) Television memory system
US5444483A (en) Digital electronic camera apparatus for recording still video images and motion video images
US7817193B2 (en) Image pickup apparatus and image pickup method to display or record images picked up at high rate in real time
KR20070041507A (en) Method and system for displaying a sequence of image frames
CN100474890C (en) Image display device
JPH0681304B2 (en) Method converter
JP3513165B2 (en) Image processing device
CN1036626C (en) Electronic zoom system using image buffer
US20040183945A1 (en) Image processor with frame-rate conversion
CN2492885Y (en) Arithmetic logic unit with frame memory
JPH0817008B2 (en) Video signal time axis correction device
JP2002209838A (en) Endoscopic imaging device
EP0725534B1 (en) Image processing method and apparatus
JPH0562867B2 (en)
CN1055187C (en) Video program production parameter extracting method and system
JPH06292152A (en) Video signal converter
JP2785262B2 (en) Title image generator
JP2007020112A (en) Image signal processing apparatus, image signal processing method and imaging device
CN1021397C (en) Method for expansion of digital signal
JPH03286271A (en) Picture display device
JP2622622B2 (en) Scan line number conversion control method
JP3853519B2 (en) Image recording device
JP2001057654A (en) High sensitivity image pickup device
JP2918049B2 (en) Storage method for picture-in-picture

Legal Events

Date Code Title Description
C14 Grant of patent or utility model
GR01 Patent grant
C19 Lapse of patent right due to non-payment of the annual fee
CF01 Termination of patent right due to non-payment of annual fee