CN2457822Y - Adaptor for conversing line-by-line video frequency to interlacing standard video frequency signal - Google Patents

Adaptor for conversing line-by-line video frequency to interlacing standard video frequency signal Download PDF

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Publication number
CN2457822Y
CN2457822Y CN 01202530 CN01202530U CN2457822Y CN 2457822 Y CN2457822 Y CN 2457822Y CN 01202530 CN01202530 CN 01202530 CN 01202530 U CN01202530 U CN 01202530U CN 2457822 Y CN2457822 Y CN 2457822Y
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China
Prior art keywords
terminal
signal
utility
model
controller
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Expired - Fee Related
Application number
CN 01202530
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Chinese (zh)
Inventor
张学明
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Changchun Institute of Optics Fine Mechanics and Physics of CAS
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Changchun Institute of Optics Fine Mechanics and Physics of CAS
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Priority to CN 01202530 priority Critical patent/CN2457822Y/en
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Publication of CN2457822Y publication Critical patent/CN2457822Y/en
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Abstract

The utility model relates to a signal converting adapter, which is used for converting the signals displayed by successive monitors applied in some occasions into signals which can be received by standard interlaced televisions, and the video signals can be recorded by a tape video recording and reproducing machine. The utility model comprises a casing, a power supply, an analogue-to-digital converter, a clock, a memory, a digital-to-analogue converter, a sync separator, a controller, an adder and a time series generator. The utility model solves the problem that successive video signals do not match with interlaced standard video signals. The utility model widens the range of application of resolution, horizontal frequency and vertical frequency, and converts successive video signals into interlaced standard video signals, so that the successive video signals match with the interlaced standard video signals, which enables the utility model to be suitable for magnetic tape recorders. The utility model provides a signal converting adapter for converting successive video into interlaced standard video.

Description

Progressive is to interlacing video standard signal conversion adapter
The utility model belongs to TV technology, relate to the interlacing TV acceptable signal that a kind of conversion of signals that the monitor line by line of some applications is shown becomes standard, and the adapter that can utilize the tape recorder and reproducer recording image to change from progressive to the interlacing video standard signal.
From the present world and home products, the product of similar type has, the new computer of releasing of Taiwan circle intelligence Science and Technology Co., Ltd. is to the TV transducer, it can become TV acceptable signal with the conversion of signals of computer output, and can utilize the tape recorder and reproducer recording image, its limitation is only supported the pattern of IBM PC, as following table:
Resolution 640 × 480 640 × 480 640 × 480 640 × 480 800 × 600 800 × 600 800 × 600 800 × 600 1024 × 768
Horizontal frequency (KHz) 31.5 37.9 37.5 43.3 35.2 37.9 48 47.2 48.4
Vertical frequency (Hz) 60 72 75 85 56 60 72 75 60
The purpose of this utility model is to solve above-mentioned resolution, horizontal frequency, the narrow problem of vertical frequency range of application, provides a kind of and has the progressive of certain range of application to interlacing video standard signal conversion adapter.
Detailed content of the present utility model: it comprises A/D converter, clock, memory, D/A, sync separator, controller, adder, timing sequencer, casing and power supply, is installed with A/D converter, clock, memory, D/A, sync separator, controller, adder and timing sequencer in casing.Progressive signal end a receives the input end of analog signal A1 of A/D converter and the video inputs A2 of sync separator respectively; Data/address bus B1~B8 the terminal of A/D converter is received the data/address bus C1~4C8 terminal of memory; Data/address bus D1~D8 the terminal of memory is received the data/address bus E1~E8 terminal of D/A; The F1 of sync separator, F2 lead-out terminal are received controller G1, G2 input terminal, the control terminal G3 of controller is connected with A/D converter control terminal A3, control terminal G4, the G5 of controller, G6, G7 are connected with input terminal B9, B10, B11, the B12 of memory, and the control terminal G8 of controller is connected with the input terminal E9 of D/A; D/A video signal output terminal H1 is connected on the input terminal H2 of adder, and the output timing signal terminal I1,12 of timing sequencer is connected on the input terminal H2 of adder, and the lead-out terminal b of adder is connected with extraneous monitor; The signal output terminal J1 of clock is connected on the controller input terminal J2, and the signal output terminal K1 of clock is connected with the clock signal input terminal K2 of timing sequencer.
The principle of adapter is to use parallel A/D converter, use clock sampling, convert the progressive video signal of simulation to digital signal, store in the memory RAM, through controller control, to store data in the memory RAM into for the first time with television line 1,3,5, order, for the second time with television line 2,4,6, order output to parallel D/A, the conversion of signals of numeral is become the vision signal output of simulation, and this signal is capable, field sync signal of superposition and blanking signal again, is exactly final interlacing standard television signal.
Among the figure, progressive signal end a divides the two-way input, one the tunnel enters the high speed A device becomes digital signal with analog signal conversion, and store in the memory, sync separator is sent on another road, separate the trip field sync signal, directly deliver in the controller, the digital signal of memory output is delivered to the high speed D/A, convert digital signal to analog signal, deliver to adder, the clock generating clock signal, the sequential of whole system and control are controlled by controller, timing sequencer produces the television line of standard, field sync signal and blanking signal are finally by adder output b outputting standard TV signal.
The utility model makes the progressive signal pattern of the utility model support be owing to adopt the structure of separating component overlap joint:
Resolution: 512 * 512
Horizontal frequency: 27KHZz~31.25KHz
Vertical frequency: 50Hz
The monochrome television signal of outputting standard:
Resolution: 512 * 512
Horizontal frequency: 15625Hz
Number of fields per second: 50
Number of pictures per second: 25 to compare its range of application from the above listed parameter and the adapter of prior art different, can not replace between mutually.Since in the market video tape recorder can only record standard interlaced television signal, and it is civilian, industry, the employed monitor of a lot of occasions belongs to progressive video signal in the military affairs, used is monitor line by line, therefore the utility model has solved the problem that progressive video signal and interlacing video standard signal can not mate, the utility model has been widened resolution, horizontal frequency, the vertical frequency range of application, and progressive video signal and interlacing video standard signal coupling then are suitable for magnetic tape recorder use, a kind of signal conversion adaptor from progressive to the interlacing normal video is provided.
Description of drawings:
Fig. 1 is a principle schematic of the present utility model
Fig. 2 is a scheme of installation of the present utility model
Embodiment of the present utility model is as depicted in figs. 1 and 2: be A/D converter 1, clock 2, memory 3, D/A 4, sync separator 5, controller 6, adder 7, timing sequencer 8, power supply 9, casing 10 among Fig. 1.
A/D converter 1 adopts eight parallel-by-bit A/D converters at a high speed; Clock 2 adopts the sampling of high frequency 16MHz crystal clock, converts the progressive video signal of simulating to eight digital signal, stores in the memory 3, and memory 3 adopts the IDT7007 memories; D/A 4 adopts eight parallel-by-bit D/As at a high speed; It is LM1881 that sync separator 5 adopts; Controller 6 adopts and separates integrated circuit; Adder 7 adopts the AD811 video amplifier, timing sequencer 8 to adopt 27C512 EPROM to make timing sequencer, and power supply 9 can be selected direct current 5V external power supply for use.Casing 10 can adopt aluminium to make.

Claims (1)

1, progressive is to interlacing video standard signal conversion adapter, it comprises casing and power supply, it is characterized in that also comprising: be installed with A/D converter, clock, memory, D/A, sync separator, controller, adder and timing sequencer in casing.Progressive signal end a receives the input end of analog signal A1 of A/D converter and the video inputs A2 of sync separator respectively; Data/address bus B1~B8 the terminal of A/D converter is received the data/address bus C1~C8 terminal of memory; Data/address bus D1~D8 the terminal of memory is received the data/address bus E1~E8 terminal of D/A; The F1 of sync separator, F2 lead-out terminal are received controller G1, G2 input terminal, the control terminal G3 of controller is connected with A/D converter control terminal A3, control terminal G4, the G5 of controller, G6, G7 are connected with input terminal B9, B10, B11, the B12 of memory, and the control terminal G8 of controller is connected with the input terminal E9 of D/A; D/A video signal output terminal H1 is connected on the input terminal H2 of adder, and on the input terminal H2 that the output timing signal terminal I1 of timing sequencer, I2 are connected to adder, the lead-out terminal b of adder is connected with extraneous monitor; The signal output terminal J1 of clock is connected on the controller input terminal J2, and the signal output terminal K1 of clock is connected with the clock signal input terminal K2 of timing sequencer.
CN 01202530 2001-01-04 2001-01-04 Adaptor for conversing line-by-line video frequency to interlacing standard video frequency signal Expired - Fee Related CN2457822Y (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN 01202530 CN2457822Y (en) 2001-01-04 2001-01-04 Adaptor for conversing line-by-line video frequency to interlacing standard video frequency signal

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN 01202530 CN2457822Y (en) 2001-01-04 2001-01-04 Adaptor for conversing line-by-line video frequency to interlacing standard video frequency signal

Publications (1)

Publication Number Publication Date
CN2457822Y true CN2457822Y (en) 2001-10-31

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Application Number Title Priority Date Filing Date
CN 01202530 Expired - Fee Related CN2457822Y (en) 2001-01-04 2001-01-04 Adaptor for conversing line-by-line video frequency to interlacing standard video frequency signal

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN100342731C (en) * 2002-05-10 2007-10-10 汤姆森特许公司 Deinterlacing of mixed progressive and non-progressive sequences
CN100344157C (en) * 2004-05-31 2007-10-17 松下电工株式会社 Scan converter

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN100342731C (en) * 2002-05-10 2007-10-10 汤姆森特许公司 Deinterlacing of mixed progressive and non-progressive sequences
CN100344157C (en) * 2004-05-31 2007-10-17 松下电工株式会社 Scan converter

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C19 Lapse of patent right due to non-payment of the annual fee
CF01 Termination of patent right due to non-payment of annual fee