CN2294886Y

CN2294886Y - Digital windshield-wiper controller

Info

Publication number: CN2294886Y
Application number: CN 97212988
Authority: CN
Inventors: 张运动
Original assignee: Individual
Current assignee: Individual
Priority date: 1997-04-04
Filing date: 1997-04-04
Publication date: 1998-10-21
Anticipated expiration: 2007-04-04

Abstract

The utility model discloses a digital windshield-wiper controller. The controller solves the problem of the present windshield-wiper device that the working frequency and the working intermittence of the windshield-wiper can not be set according to requirement. The utility model is characterized in that a reference pulse source circuit, a frequency division timing circuit, an inner windshield-wiper and outer windshield-wiper resetting sensing circuit, a windshield-wiper resetting timing circuit and a frequency and intermittence setting circuit are additionally arranged at a control circuit; thus, the windshield-wiper can have two working modes which are continuous work and intermittent work, and the working frequency of each intermittent work and the intermittent time of each intermittence can be easily set; thereby, a driver can pay full attention to driving, and the driving safety can be improved.

Description

Digital rain brush controller

The utility model relates to a kind of rain brush controller, particularly relates to a kind of rain brush controller of Fundamental Digital Circuit.

Wiper system is the indispensable devices of various motor-driven transport facilitys.The vehicle need chaufeur can in time find the various situations in the place ahead in the process of travelling, so that take corresponding emergency measure.Wiper system can keep the unimpeded of the place ahead sight line and help driving safety.Wiper system on the present various vehicle all is to control Wiper motor by a switch basically, and the master cock of closing rear windscreen wiper motor just drives the rain brush crank motion and carries out work.Though this Wiper system is simple, has some problems: 1, needs hand switch every now and then, especially in the process of running at high speed, the people is taken sb's mind off sth in the process of moving, brought certain hidden danger to driving safety; 2, rain brush needs at therefore each reciprocal number of times and intermittence by the big or small degree ceaselessly manually control of chaufeur according to the sleet of outside in case work just has only state of continuous working, and is extremely not convenient; When 3, manually stopping rain brush, often can not make rain brush turn back to initial orientation, be parked in sometimes on the position that influences sight line, be unfavorable for the chaufeur normal operation.

At above-mentioned the deficiencies in the prior art, the purpose of this utility model provides a kind of digital rain brush controller, this rain brush controller not only has continuously-running duty, and the number of times of rain brush work and every back and forth time between several times intermittently can also be set easily.

In order to achieve the above object, the technical solution of the utility model is: a kind of digital rain brush controller, comprise DC regulated power supply and Wiper motor driving circuit, it is characterized in that it also comprises number of times initialization circuit, intermittently initialization circuit, rain brush return sensing circuit, rain brush return counting circuit, basic pulse source circuit, frequency division timekeeping circuit, number of times decoding scheme and decoding scheme intermittently; Above-mentioned number of times initialization circuit and intermittently initialization circuit be formed by connecting by binary pair and unidirectional static shift register (SSR) IC2, IC1 respectively, the mouth of binary pair links to each other with the clock end CP of unidirectional static shift register (SSR), n the parallel output terminal of wherein unidirectional static shift register (SSR) IC2, IC1 respectively with corresponding linking to each other of n input end of joint denial gate f2, the f1 of n input end, the mouth of described joint denial gate links to each other with the data input pin D of above-mentioned unidirectional static shift register (SSR) IC2, IC1 respectively; The clock end of unidirectional static shift register (SSR) IC3 in the mouth of above-mentioned rain brush return sensing circuit and the rain brush return counting circuit links to each other, (n-1) individual parallel output terminal of this unidirectional static shift register (SSR) links to each other with n-1 the input end of (n-1) input end joint denial gate f3, and the mouth of this joint denial gate links to each other with the data input pin D of above-mentioned unidirectional static shift register (SSR) IC3; Above-mentioned number of times decoding scheme is by (n-1) individual double input end and door b1, b2 ... a bn-1 and a n-1 input end or a door h link to each other and form; Above-mentioned intermittence, decoding scheme was by (n-1) individual double input end and door (a1, an a2 ... corresponding linking to each other of an-1 and (n-1) input end joint denial gate g forms; Two input ends of each in the above-mentioned number of times decoding scheme and door respectively with rain brush return counting circuit and number of times initialization circuit in one of them corresponding linking to each other in the mouth of IC3, IC2 of unidirectional static shift register (SSR); In the above-mentioned intermittence decoding scheme each and two input ends of door respectively with the intermittence initialization circuit in unidirectional static shift register (SSR) IC1 and above-mentioned frequency division timekeeping circuit in (n-1) individual mouth of counting machine IC11 in one of them corresponding linking to each other; Above-mentioned number of times decoding scheme or door h output and intermittently the joint denial gate g of decoding scheme export and link to each other with two input ends door d with one two input end respectively, link to each other with one of them input end of one three input end or door e with door C with a double input end respectively with the mouth of door d, link to each other with the mouth of said reference pulse source circuit with another input end of door c, link to each other with input end of clock in the frequency division timekeeping circuit with the mouth of door c, two input ends in addition of above-mentioned or door e are set with above-mentioned number of times respectively and the joint denial gate f1 in the initialization circuit intermittently, the mouth of f2 links to each other; Mouth above-mentioned or door e links to each other with above-mentioned Wiper motor driving circuit by a see-saw circuit; Above-mentioned number of times set and intermittently unidirectional static shift register (SSR) IC2, the IC1 in the initialization circuit be the energising zero clearing, unidirectional static shift register (SSR) IC3 in the above-mentioned rain brush return counting circuit and frequency division timekeeping circuit IC7, IC8, IC9, IC10, IC11 are the charged zero clearing of motor.

Described basic pulse source circuit is for " NEC555 " integrated circuit (IC6) serving as the main 100HZ square-wave generator that constitutes.

Described frequency division timekeeping circuit be by 4 " CD4017B " type decade counter IC7, IC8, IC9, IC10 be concatenated into 2000 advance 1 counting circuit after its output link to each other with the clock end CP of " CD4017B " IC 1 again, formation be the frequency division timekeeping circuit of mouth with carry mouth Q3, Q6, Q9.

Described rain brush return sensing circuit is to serve as main to constitute with " NEC555 " IC 4, wherein link to each other with the end of an open type travel switch XK behind " 6,2 " bipod short circuit of " NEC555 " circuit, the other end of the trip switch is by one " RC " parallel line ground connection, so that make rain brush whenever back and forth press the one stroke switch, " 3 " pin of above-mentioned " NEC555 " circuit is just exported a high impulse.

Described rain brush return is sensed as a Hall switch, " 1,3 " two ends of Hall switch link to each other with the positive pole and the ground wire of power supply respectively, and its " 2 " pin links to each other by the clock end CP of the unidirectional static shift register (SSR) IC3 in a not gate Y and the rain brush return counter circuit.

Described number of times set and intermittently the binary pair in the initialization circuit be rest-set flip-flop, " putting 0 end " R of binary pair respectively links to each other with positive source Vcc by a resistance with " putting 1 end " S, in addition, " put 0 end " by setting the open contact ground connection of button K1, K2, " put 1 end " by setting the normally closed contact ground connection of button K1, K2, the mouth of binary pair is the Q end.

Rain brush return sensing circuit in one also can be arranged in this controller circuitry, and the output of described two rain brush return sensing circuits can link to each other by the clock end CP of the unidirectional static shift register (SSR) IC3 in a double input end or door J and the rain brush return counting circuit.

Described joint denial gate f2 can be 5 mouths, and its 5th mouth can link to each other with the mouth Q0 of unidirectional static shift register (SSR) IC1 in the intermittence initialization circuit.

From technique scheme as can be seen, the utlity model has following advantage: 1,, used integrated circuit in the circuit more, thereby had that circuit is simple, the advantage of reliable operation because controller line has adopted Digital Electronic Technique; 2, design number of times setting, intermittently initialization circuit and decoding scheme thereof in the controller, chaufeur can be set the service condition of rain brush easily according to the abominable degree of weather, made its automatic work, be convenient to concentrate one's energy to ensure driving safety; 3, the rain brush return sensing circuit in the controller not only can be sent out an impulse singla to each return of rain brush, and rain brush after reaching set point number, reciprocal time is parked near the rain brush return sensor immediately, be the section start of rain brush, thereby avoid stopping on the position that influences sight line.

The utility model is further explained and explanation below in conjunction with drawings and Examples:

Fig. 1 is the electronic circuit schematic diagram of embodiment 1 of the present utility model;

Fig. 2 is the electronic circuit schematic diagram of embodiment 2 of the present utility model;

Fig. 3 is the input and the output pulse waveform figure of " CD4017B " integrated package of adopting in the utility model;

Fig. 4 is the input and the output pulse waveform figure of " CD4015B " integrated package of adopting in the utility model.

Embodiment 1, and as shown in Figure 1, among the figure, the number of times initialization circuit is formed by connecting by " RS " binary pair and the unidirectional static shift register (SSR) IC2 of " CD4015B " type.Wherein, " R " of " RS " binary pair end respectively links to each other with positive source Vcc by a resistance with " S " end, and " R " end links to each other with power ground with a pair of normally closed interlock with a pair of normally open contact that " S " holds again each number of pass times to set button K1." Q " mouth of " RS " binary pair links to each other with the input end of clock CP of " CD4015B " ic chip 2.The parallel output terminal of " CD4015B " type ic chip 2 is " Q0, Q1, Q2, Q3 ", these 4 parallel output terminal correspondences are connected into 4 input ends of 4 input end joint denial gate f2, the mouth of joint denial gate f2 links to each other with the data input pin " D " of ic chip 2, and the clear terminal " Cr " of " CD4015B " type ic chip 2 links to each other, links to each other with power ground by resistance with positive source Vcc by electric capacity.

The initialization circuit at intermittence of embodiment 1 is formed by connecting with unidirectional static shift register (SSR) IC1 of " CD4015B " type and joint denial gate f1 by same " RS " binary pair, and connection mode each other is identical with the number of times initialization circuit.

The rain brush return sensing circuit of embodiment 1 is by formations such as " NEC555 " type ic chip 4, travel switch XK and electric capacity.Wherein " 4,8 " bipod power connection positive pole of ic chip 4 passes through resistance power connection positive pole behind " 2,6 " bipod short circuit, pin " 1 " ground connection, and pin " 5 " passes through capacity earth.In addition, pin " 2,6 " short circuit point also links to each other with the end of an open type travel switch XK, and the other end of travel switch XK is through RC parallel line ground connection.When this connection mode can make rain brush whenever make a round trip to press the travel switch XK that is placed in reference position, just can make " 2,6 " bipod of ic chip 4 once instantaneous " 0 " current potential occur, thereby make its " 3 " pin output forward " 1 " pulse.

The rain brush return counting circuit of embodiment 1 is made up of unidirectional static shift register (SSR) IC3 of " CD4015B " type and 3 input end joint denial gate f3,3 input ends of 3 parallel output terminals " Q0, Q1, Q2 " AND OR NOT gate f3 of register IC3 are corresponding to link to each other, and the mouth of joint denial gate f3 links to each other with the data input pin " D " of register IC3.The input end of clock of register IC3 " CP " links to each other with the mouth pin " 3 " of ic chip 4 in the above-mentioned rain brush return sensing circuit.

The frequency division timekeeping circuit of embodiment 1 conspires to create thousand system circuit successively by 3 " CD4017B " type decade counter IC7-IC9, and then link to each other with " CD4017B " type decade counter IC10, the BS Binary Scale mouth " Q2 " of this decimal scale " CD4017B " type counting machine IC10 links to each other with the clock end " CP " of the 5th " CD4017B " type decade counter IC11 again, constitute complete frequency division timekeeping circuit, the Q3 pin of counting machine IC5, Q6 pin, Q9 pin are as three parallel output pins of frequency division timekeeping circuit.

The number of times decoding scheme of embodiment 1 be forms by 3 two input ends and door b1, a b2, b3 and 1 three input end or door h with or, 3 with one of them input end of door successively with the number of times initialization circuit in unidirectional static shift register (SSR) IC2 back 3 mouth Q1, Q2, Q3 is corresponding links to each other, link to each other with 3 parallel output terminal Q0, Q1, the Q2 of register IC3 successively with door b1, b2, b3 another input end separately.

The decoding scheme at intermittence of embodiment 1 is by 3 two input ends and door a1, a2, a3 and 1 three AND OR NOT gate that input end joint denial gate g forms, with among door a1, a2, the a3 each with one of them input end of door successively with the intermittence initialization circuit in back 3 mouths " Q1, Q2, Q3 " corresponding linking to each other of unidirectional static shift register (SSR) IC1, link to each other with 3 parallel output terminals " Q3, Q6, Q9 " of ic chip 11 in the frequency division timekeeping circuit successively with door a1, a2, a3 another mouth separately.

Above-mentioned number of times decoding scheme and the intermittently mouth and a double input end and two corresponding linking to each other of input end door d of decoding scheme link to each other with one of them input end of door c and one of them input end of one three input end or an e with two input ends respectively with the mouth of door d.Link to each other with the mouth of basic pulse source circuit with another input end of door c, link to each other with the input end of clock cp of decade counter IC7 in the mouth of door c and the frequency division timekeeping circuit.The said reference pulse source circuit is to be the 100HZ square-wave pulse generation circuit of main formation by " NEC555 " IC circuit 6.Corresponding linking to each other of mouth above-mentioned or door two other input end AND OR NOT gate f2 of e and joint denial gate f1.The mouth of joint denial gate e drives intermediate relay ZJ of a switch triode T control by see-saw circuit, Wiper motor M1 be connected on the direct supply after a pair of open contact ZJ-1 of intermediate relay ZJ connects.

Above-mentioned number of times is set and is intermittently linked to each other with positive source Vcc by an electric capacity behind clear terminal " Cr " short circuit of unidirectional static shift register (SSR) IC2, the IC1 in the initialization circuit, is connected into the zero clearing pattern of switching on.The clear terminal Cr of unidirectional static shift register (SSR) IC3 in the above-mentioned rain brush return counting circuit links to each other with the output terminals A of see-saw circuit by electric capacity, and links to each other with ground wire by resistance.The clear terminal " Cr " of " CD4017B " type ic chip 7-IC11 in the above-mentioned frequency division timekeeping circuit in addition, links to each other with the output terminals A of above-mentioned see-saw circuit by a resistance behind the clear terminal short circuit of each integrated package separately by a resistance eutral grounding.

In the number of times initialization circuit of embodiment 1, whenever press and once set button K1, just make cooresponding mouth output " 1 " current potential in " Q0, Q1, Q2, Q3 " mouth of ic chip 2, so circulation occurs, and waveform as shown in Figure 4.As a same reason, the setting button K2 that presses repeatedly in the initialization circuit at intermittence can make 4 mouths circulations of ic chip 1 " 1 " current potentials occur equally.Rain brush controller shown in the embodiment 1 is after energized, and joint denial gate f1, f2 all export " 1 " current potential, or door e output " 1 ", see-saw circuit output " 0 ", and motor does not change, and rain brush is not worked.After pressing setting button K1, K2 respectively, all output " 1 " of " Q0 " end of ic chip 2, IC1, joint denial gate f1, f2 all export " 0 ", and this just makes or wherein two input ends of door e are imported for " 0 ".In addition, 3 mouths of all the other of ic chip 2 " Q1, Q2, Q3 " are still " 0 ", the mouth of the ic chip 3 in the rain brush return counting circuit " Q0, Q1, Q2 " is " 0 " output, this just makes the output with door b1, a b2, b3 be " 0 " entirely, thereby or the output of door h also be " 0 ".At this moment, by the same token, 3 mouths of all the other of ic chip 1 " Q1, Q2, Q3 " also are " 0 ", thereby joint denial gate g is output as " 1 ".So just make with door d and be output as " 1 " * " 0 "=" 0 ".Therefore, or the 3rd input end of door e also become " 0 ", and see-saw circuit is output as " 1 ", and see-saw circuit just driving switch aerotron T makes the intermediate relay ZJ adhesive, and then drives Wiper motor, makes rain brush enter continuous duty.Under continuous duty, though constantly pressing travel switch XK, rain brush make rain brush return sensing circuit IC4 export the high potential pulse repeatedly, thereby make mouth " Q0, Q1, the Q2 " circulation of the ic chip 3 in the rain brush return counting circuit " 1 " current potential occur, but because all the other 3 cooresponding mouths " Q1, Q2, Q3 " of the ic chip 2 in the number of times initialization circuit are always " 0 " current potential, thereby also be always zero with the output of door b1, b2, b3, make or the output of door h also is always zero, this makes the output with door d also be always " 0 ".Be output as under the situation of " 0 " with door d, though the pulse that basic pulse source circuit IC6 ceaselessly sends 100HZ, but send pulse can for all the time the frequency division timekeeping circuit with door C, this makes that 3 mouths " Q3, Q6, Q9 " of ic chip 11 are always " 0 " in the frequency division timekeeping circuit, and the output of joint denial gate g also is always " 1 ".

Embodiment 1 shown in Fig. 1 also can be as required to setting at the work number of times and the intermittence of rain brush.For example, when after the energized to set button K1, when K2 all presses twice, " Q1 " mouth of ic chip 2, IC1 is " 1 " current potential, this moment, joint denial gate f1, f2 were output as " 0 ", be output as " 0 " with door d, or a door e were output as " 0 ".Wiper motor is started working, when rain brush presses one stroke switch XK, " Q0 " of ic chip 3 just exports " 1 ", just export " 1 " with door b1, or door h also exports " 1 ", because of joint denial gate 9 is still exported original " 1 " current potential, thereby just export " 1 " with door d, like this or the door e just export " 1 ", Wiper motor just quits work, enter intermittently state, simultaneously just can export to the frequency division timekeeping circuit to the 100HZ pulse in basic pulse source with door C, " Q2 " of ic chip 10 end was just exported " a 1 " current potential in per 20 seconds in the frequency division timekeeping circuit, made " Q3; Q6; Q9 " three mouths of ic chip 11 successively can be at 60 seconds like this, 120 seconds, " 1 " current potential appears in the time of 180 seconds successively.Be connected in because of " Q1 " end of " Q3 " of ic chip 11 end and ic chip 1 is corresponding and two input ends of an a1 on, when rain brush intermittently enters 60 seconds, just export " 1 " current potential with door a1, joint denial gate g just exports " 0 " current potential, with door d output " 0 " current potential, or door e output " 0 " current potential, motor is just reworked, travel switch resets at once, or door h output change " 0 ", the 100HZ pulse output with door C meanwhile just can stop ic chip 3, IC7-IC11 also is cleared simultaneously, " Q0 " output of ic chip 3 becomes " 0 ", and joint denial gate g heavily becomes output " 1 " current potential.At this moment rain brush finishes intermittence of 60 seconds and restarts work, and when rain brush working in reciprocating mode once once more during return or just output " 1 " current potential again of door h, Wiper motor just outage again quits work, and enters 60 seconds intermittence.Only otherwise carry out setting once more, to setting button K1, K2 rain brush will under the control of rain brush controller, carry out " ... the periodical duty that brush is moving once---intermittently 60 seconds---brush is moving once---intermittently 60 seconds ... ".

By to setting the setting of button K1, K2, embodiment 1 also can realize brushing 1 time, 2 times, 3 times and 9 kinds of work in combination modes at 60 seconds, 120 seconds, 180 seconds intermittence.

Enforcement 2 is for example shown in Figure 2, this embodiment and embodiment 1 at first have 2 differences, the first, the joint denial gate f2 in the number of times initialization circuit becomes 5 input ends by 4 input ends, and the mouth " Q0 " of the ic chip 1 in its input end that has more and the initialization circuit intermittently links to each other; The second, joint denial gate 9 becomes 4 input ends by three input ends, and its input end that has more links to each other with the mouth " Q0 " of ic chip 1, and above-mentioned 2 differences make embodiment 2 and once set button K2 controller and just can enter continuous duty as long as press.

Secondly, increased an interior rain brush circuit among the embodiment 2.Inside and outside rain brush return sensor circuit changes by HST0102-1A type Hall switch H1, H2 and constitutes, and this point is also different with embodiment 1.Negative pole " 3 " ground connection of the Hall switch of inside and outside rain brush sensing circuit, its positive pole " 1 " links to each other with positive source Vcc with two double-throw contacts of double-throw change-over swith ZK respectively, that its output " 2 " is connected into a double input end through a cooresponding not gate Y1, Y2 separately or door J, or the mouth of door J is connected into the input end of clock " CP " of the ic chip 3 of rain brush return counting circuit.In addition, the a pair of open contact of intermediate relay ZJ is connected with the common point of double-throw change-over swith ZK, another of change-over swith ZK links to each other with inside and outside Wiper motor respectively to interlock double-throw contact, and the common point of this double-throw change-over swith links to each other with positive source Vcc by the ZJ normally open contact ZJ-1 of intermediate relay again.Embodiment 2 is identical with other circuit formation and the line of embodiment 1, does not give unnecessary details down.

Claims

1, a kind of digital rain brush controller, comprise DC regulated power supply and Wiper motor driving circuit, it is characterized in that it also comprises number of times initialization circuit, intermittently initialization circuit, rain brush return sensing circuit, rain brush return counting circuit, basic pulse source circuit, frequency division timekeeping circuit, number of times decoding scheme and decoding scheme intermittently; Above-mentioned number of times initialization circuit and intermittently initialization circuit be formed by connecting by binary pair and unidirectional static shift register (SSR) (IC2, IC1) respectively, the mouth of binary pair links to each other with the clock end of unidirectional static shift register (SSR) (CP), n parallel output terminal of wherein unidirectional static shift register (SSR) (IC2, IC1) respectively with corresponding linking to each other of n input end of the joint denial gate (f2, f2) of n input end, the mouth of described joint denial gate links to each other with the data input pin (D) of above-mentioned unidirectional static shift register (SSR) (IC2, IC1) respectively; The clock end (CP) of the unidirectional static shift register (SSR) (IC3) in the mouth of above-mentioned rain brush return sensing circuit and the rain brush return counting circuit links to each other, (n-1) individual parallel output terminal of this unidirectional static shift register (SSR) links to each other with (n-1) individual input end of (n-1) input end joint denial gate (f3), and the mouth of this joint denial gate links to each other with the data input pin (D) of above-mentioned unidirectional static shift register (SSR) (IC3); Above-mentioned number of times decoding scheme is by (n-1) individual double input end and door (b1, b2 ... bn-1) with one (n-1) input end or door link to each other and form; Above-mentioned intermittence, decoding scheme was by (n-1) individual double input end and door (a1, an a2 ... an-1) form with corresponding linking to each other of one (n-1) input end joint denial gate (g); Two input ends of each in the above-mentioned number of times decoding scheme and door respectively with rain brush return counting circuit and number of times initialization circuit in one of them corresponding linking to each other in the mouth of unidirectional static shift register (SSR) (IC3, IC2); In the above-mentioned intermittence decoding scheme each and two input ends of door respectively with the intermittence initialization circuit in unidirectional static shift register (SSR) (IC1) and above-mentioned frequency division timekeeping circuit in (n-1) individual mouth of counting machine (IC11) in one of them corresponding linking to each other; Above-mentioned number of times decoding scheme or door (h) output and intermittently the joint denial gate (g) of decoding scheme export and link to each other with two input ends door (d) with one two input end respectively, link to each other with an input end of door (c) and one of them input end of one three input end or (e) with a dual input respectively with the mouth of door (d), link to each other with the mouth of said reference pulse source circuit with another input end of door (c), link to each other with input end of clock in the frequency division timekeeping circuit with the mouth of door (c), two input ends in addition of above-mentioned or door (e) are set with above-mentioned number of times respectively and the joint denial gate (eight in the initialization circuit intermittently, f2) mouth links to each other; Mouth above-mentioned or door (e) links to each other with above-mentioned Wiper motor driving circuit by a see-saw circuit; Above-mentioned number of times set and intermittently the unidirectional static shift register (SSR) (IC2, IC1) in the initialization circuit be the energising zero clearing, unidirectional static shift register (SSR) (IC3) in the above-mentioned rain brush return counting circuit and frequency division timekeeping circuit (IC7-IC11) are the charged zero clearing of motor.

2, rain brush controller according to claim 1 is characterized in that described basic pulse source circuit is for " NEC555 " integrated circuit (IC6) serving as the main 100HZ square-wave generator that constitutes.

3, rain brush controller according to claim 1, it is characterized in that described frequency division timekeeping circuit be by 4 " CD4017B " type decade counters (IC7, IC8, IC9, IC10) be concatenated into 2000 advance 1 counting circuit after its output link to each other with the clock end (CP) of " CD4017B " integrated circuit (IC11) again, formation be the frequency division timekeeping circuit of mouth with carry mouth (Q3, Q6, Q9).

4, rain brush controller according to claim 1, it is characterized in that described rain brush return sensing circuit serves as main formation with " NEC555 " integrated circuit (IC4), wherein link to each other with the end of an open type travel switch XK behind " 6,2 " bipod short circuit of " NEC555 " circuit, the other end of the trip switch is by one " RC " parallel line ground connection, so that make rain brush whenever back and forth press the one stroke switch, " 3 " pin of above-mentioned " NEC555 " circuit is just exported a high impulse.

5, rain brush controller according to claim 1, it is characterized in that described rain brush return is sensed as a Hall switch, Hall switch " 1,3 " two ends link to each other with the positive pole and the ground wire of power supply respectively, and its " 2 " pin links to each other with unidirectional static shift register (SSR) (IC3) clock end (CP) in the rain brush return counter circuit by a not gate.

6, rain brush controller according to claim 1, it is characterized in that described number of times is set and intermittently the binary pair in the initialization circuit be rest-set flip-flop, " putting 0 end " of binary pair (R) (S) respectively links to each other with positive source (Vcc) by a resistance with " putting 1 end ", in addition, " put 0 end " by setting the open contact ground connection of button (K1, K2), " put 1 end " by setting the normally closed contact ground connection of button (K1, K2), the mouth of binary pair is (Q) end.

7, according to claim 1,2,3,4,5 or 6 described rain brush controllers, it is characterized in that also can having in this controller circuitry rain brush return sensing circuit in, the output of described two rain brush return sensing circuits can link to each other by the clock end (CP) of the unidirectional static shift register (SSR) (IC3) in a double input end or door (J) and the rain brush return counting circuit.

8, rain brush controller according to claim 7 is characterized in that described joint denial gate (f2) can be 5 mouths, and its 5th mouth can link to each other with the mouth (Q0) of unidirectional static shift register (SSR) (IC1) in the intermittence initialization circuit.