CN221575334U

CN221575334U - High-voltage translation circuit suitable for DC-DC driving and with wide working voltage range

Info

Publication number: CN221575334U
Application number: CN202322459421.8U
Authority: CN
Inventors: 何迟; 李高林; 刘程嗣; 徐礼祥; 李健
Original assignee: Xinbei Electronic Technology Nanjing Co ltd
Current assignee: Xinbei Electronic Technology Nanjing Co ltd
Priority date: 2023-09-11
Filing date: 2023-09-11
Publication date: 2024-08-20
Anticipated expiration: 2033-09-11

Abstract

The utility model provides a high-voltage level shifting circuit with a wide working voltage range, which is suitable for DC-DC driving, and comprises a first power supply VCC, a switch node VX, a second power supply VBOOT and a logic input end IN, wherein the logic input end IN is used for receiving a logic input signal with a high level being the first power supply VCC and inputting a level signal to the circuit; the logic output terminal OUT is used for providing a logic output signal with a high level being the second power supply VBOOT, and two capacitors C1 and C2. The level shift circuit can be used for level shift of signals between different power rails, can solve the problem that the high-voltage level shifter cannot normally transmit signals at low power voltage or has long signal delay time, can ensure quick and reliable overturning of the high-voltage level shifter, and can have good balance between overturning speed and static power consumption.

Description

High-voltage translation circuit suitable for DC-DC driving and with wide working voltage range

Technical Field

The utility model relates to the technical field of integrated circuits, in particular to a high-voltage translation circuit with a wide working voltage range suitable for DC-DC driving.

Background

In the prior art, in order to meet the application requirements of the high-voltage DC-DC converter, some wafer factories develop a process suitable for designing a high-voltage power supply chip, and the process has the characteristics of a thin/thick gate oxide layer and higher rated voltage, so that the problem that a high-voltage level shifter cannot normally transmit signals at a low power supply voltage or has long signal delay time is solved.

PVT (process, voltage, temperature) performance is a critical factor that affects the ease of mass production of integrated circuits. P refers to process variations in the chip fabrication process, and the NMOS or PMOS drive capability (sometimes also understood as current magnitude or carrier mobility) varies from one transistor/wafer/lot to another, and the performance of all logic gates varies within 5 process corners (ss, ff, sf, fs, tt). V refers to the supply voltage of the chip, generally the larger the voltage, the larger the transistor current, and the faster the chip speed. T is the working temperature of the chip, the influence of the temperature on the performance of the chip is complex, and the higher the temperature is, the more vibration of the silicon lattice is considered to be aggravated, the carrier mobility is reduced, the saturation current of the transistor is reduced, and the chip is slowed down. However, this theory is only applicable to non-advanced processes, in which the threshold voltage VT and the power supply voltage of the transistor are low, so that the influence of VT on the logic gate delay is more important, and VT increases with the decrease of temperature, so that when the temperature decreases to a certain extent, the influence of VT on the logic gate delay becomes non-negligible, so that the logic gate delay increases with the decrease of temperature, which is called temperature inversion.

Chinese patent CN103856208 a describes a system for a level shifter, as shown in fig. 1, common gate NMOS devices M5 and M6 are used together with a low voltage control block 232 to increase the pull-down driver strength and mitigate the contention of the level shifter 230. By implementing the low voltage control block 232 using a low voltage device, a higher signal strength per unit area can be obtained as compared to using a high voltage device. The low voltage control block 232 is connected to nodes a and B coupled to the sources of common gate transistors M5 and M6, respectively. An inverter 206 coupled to the drain of PMOS transistor M2 buffers the output of level shifter 230 as output signal Dout. Inverter 206 is referenced to high voltage power supply VDDH. The cross-coupled NMOS devices M9 and M10 accelerate the voltage switching at nodes a and B via positive feedback in a similar manner as PMOS transistors M1 and M2. The common gate devices M5 and M6 isolate the high voltage domain of the PMOS transistors M1 and M2 from the low voltage control block 232, thereby protecting the low voltage devices in the low voltage control block 232 from breakdown and/or damage. The common-gate devices M5 and M6 may also be implemented using low-voltage devices, with VDDH being low enough so that the common-gate devices M5 and M6 may operate safely. Such a condition exists when VDDH is less than twice VDDL. Common gate devices M5 and M6 are shown with their gates biased with respect to the low voltage supply VDDL, but in practice other suitable bias voltages may be used. However, this scheme is only suitable for switching between two power supplies (VDDL to VDDH), and is not suitable for level shifting of the DC-DC high-side power transistor driving signal.

Chinese patent document CN102904565B describes a level shift circuit for DC-DC driven ultra-low quiescent current, as shown in fig. 2, comprising: a first power supply VCC having an input voltage ranging from 0V to 6V; the switch node voltage VX is a floating ground potential and is connected with the common end of the high-voltage side and the low-voltage side of the DC-DC converter, and the input voltage range of the switch node voltage VX is 0V to 30V; the second power supply VBOOT is a bootstrap high-voltage power supply of the DC-DC converter, and the input voltage range of the second power supply VBOOT is 5V to 35V; the second power supply VBOOT is a voltage formed by superposing a fixed voltage (for example, 5V) on the basis of the switching node voltage VX of the DC-DC converter, wherein the VBOOT changes along with the change of the switching node voltage VX, and the difference between the VBOOT and the switching node voltage VX is always constant in the full output range. A logic input terminal IN for receiving a logic input signal having a high level of a first power VCC and a low level of 0V; and inputting a level signal to the circuit; the logic output terminal OUT is configured to provide a logic output signal having a high level of the second power supply VBOOT and a low level of the third power supply VX. In this scenario, where M5 and M6 are high voltage PMOS, VBOOT-LX (shown in FIG. 2) may not be flipped or the flip delay is excessive when the voltage at point A is low, because point A may be pulled high to VBOOT by M7 when LEVEL SHIFTER is in the high state at point A and point B is low. And point B is pulled low to lx+vgs by M6. When the input signal is from high to low, and a is to be pulled down by M5, VGS 5=vboot-LX, where M7 is in the on state and VGS7 is VBOOT-LX-VGS. However, M7 is a low-voltage tube, vth is small, M5 is high voltage PDEMOS, vth is large, and as point a is pulled down, the pull-down capability of M5 is weaker, and under the condition of extreme PVT, point a may not be pulled down enough to ensure the inversion of the later stage. Therefore, this scheme is suitable for level conversion from the low voltage power supply VCC to VBOOT and the switching node LX, but suffers from the problems of weak driving capability at low voltage (VBOOT-LX) and slow conversion rate.

Disclosure of utility model

In view of the technical problems existing in the prior art, the utility model aims to provide a high-voltage level shifting circuit which can be used for level shifting of signals between different power rails, can solve the problem that a high-voltage level shifter cannot normally transmit signals at low power voltage or has long signal delay time, can ensure quick and reliable overturning of the high-voltage level shifter, and can have good balance between overturning speed and static power consumption and is suitable for a wide working voltage range of DC-DC driving.

Specifically, according to a first aspect of the present utility model, there is provided a high-voltage level shift circuit suitable for a wide operating voltage range of a DC-DC drive, the level shift circuit comprising:

A first power supply VCC is provided,

The switch node VX is connected with a common end of a high-voltage side and a low-voltage side of the DC-DC converter;

the second power supply VBOOT is a bootstrap type high-voltage power supply of the DC-DC converter; the second power supply VBOOT is a voltage formed by superimposing a fixed voltage on the basis of the switching node VX of the DC-DC converter, VBOOT varies with the variation of the switching node VX,

A logic input terminal IN for receiving a logic input signal of a first power supply VCC at a high level; and inputting a level signal to the circuit;

A logic output terminal OUT for providing a logic output signal with a high level being the second power supply VBOOT;

The upper polar plate of the two capacitors C1 and C2 is connected to VCC through the switching transistors M5 and M6 respectively, and the lower polar plate is directly connected to the grids of the transistors M3 and M4 respectively, so that the grids of the transistors M3 and M4 are quickly pulled up at the switching moment, and the transistors M1 and M2 are opened for strong pull-down in a short time.

The transistors MA and MB are selected from high-voltage NMOS, so that the transistors M1 and M2 are protected, the voltage breakdown problem is avoided, and the high-voltage isolation function is realized. The transistors M13 and M14 are low-voltage large-size PMOS, the lower the voltage of the points A and B is, the stronger the pull-up capability of the transistors M13 and M14 is, and the size of the PMOS is required to ensure that the voltage of the points A and B is not lower than VBOOT-5V at the moment of level shift and turnover.

The core point of the circuit operation is that the pull-down capability of the transistor M1 or M2 is enhanced at the moment of the input signal turning by utilizing the capacitor bootstrap characteristic, the circuit nodes A and B under low voltage are ensured, the output is smoothly turned over, and the turning speed can be increased.

When the input signal IN is 0, the right branch of the converter IN the horizontal direction is observed, the gates of the transistors M8 and M10 become inverse signals of IN, and at this time, M8 and M10 are turned on, and M6, the source of which is connected to the first power VCC, is turned off. The upper and lower plates of capacitor C2 are discharged to 0 through transistors M8 and M10, respectively.

When the input signal IN is shifted 1 from 0, the right branch is observed, and at this time, the transistors M8 and M10 are turned from on to off, and the transistor M6 is turned from off to on, and the first power supply VCC rapidly charges the upper plate of the capacitor C2 through the transistor M6. Because of the charge-retaining property of the capacitor, the lower electrode plate of C2 also can be pulled up quickly, so that the pull-down capability of M2 is increased quickly in a short time, and the discharge of the point B (the drain electrode of M14 is shown in the figure) is ensured. Looking at the left branch, transistors M7 and M9 change from off to on, capacitor C1 discharges primarily through M7 and M9, while the gate voltage of M3 has discharged rapidly to approximately Vth before the transition, at which time the current through M1 and M3 approaches 0, while M11 turns off the weak pull-down of the I1 current source.

Transistor M2 now has a strong pull-down current I2 and is mirrored through transistor M14 to transistor M16. The transistor M1 current approaches 0 and mirrors through transistor M13 to transistor M15 (to ensure LEVEL SHIFT fast flip, the larger the difference in current between the two legs is, the better one leg current approaches 0, the other leg current can be designed to be several hundred uA or even several mA levels in a short time), and the transistors M15, M19 and M21 currents all approach 0. The currents of transistors M1 and M2 are mirrored, eventually forming a comparison between the currents of transistors M21 and M16, and generating a high-low signal of the output voltage.

Since the MOS between VBOOT-LX is a low voltage PMOS, the operating voltage of the current level shift circuit (between VBOOT-LX) can be particularly low (about 1 VGS).

In the present utility model, the switching transistors M11, M12 and the current sources I1, I2 are additionally structured, and one and only one of M11 and M12 is in the on state in order to secure a certain state in the steady state.

Taking the state IN which the input signal IN is high as an example,

The left branch, at this time M1 is disconnected, M11 is disconnected, point A has no pull-down current,

The right branch circuit, after a period of time after the instant of turning over, the voltage of the lower polar plate of C2 is discharged through M4 until M4 is disconnected, at this time, M2 is also in a disconnected state, M12 is conducted, and point B has a weak pull-down of I2. If this I2 weak pull-down is cancelled, both A and B will be pulled high to VBOOT-Vth, the output state cannot be determined, so weak pull-down of I1 and I2 is necessary.

According to the utility model, the bootstrap characteristic of the capacitor is utilized, and the pull-down capability of the node is increased at the moment of inverting the input signal, so that the high-voltage level shifter is ensured to be inverted quickly and reliably. Thus, the utility model has a good balance between slew rate and static power consumption.

Drawings

Fig. 1 is a schematic diagram of a low-voltage control circuit of a level shifter according to the prior art.

Fig. 2 is a schematic diagram of a level shift circuit according to the prior art.

Fig. 3 is a schematic diagram of a level shift circuit with a fast response to a wide operating voltage amplitude of a DC-DC drive according to an embodiment of the present utility model.

In the drawing, M1 to M21 represent first to twenty-first transistors, C1 and C2 represent first and second capacitors, respectively, VIN represents an input terminal voltage, VX represents a switching node voltage, and VSS represents a ground voltage.

Detailed Description

The level shift circuit according to the present utility model will be described in detail with reference to the accompanying drawings in conjunction with the embodiments, and those skilled in the art will understand that the description is exemplary and that the present utility model is not limited to the embodiments.

As shown in fig. 3, a high voltage level shift circuit suitable for DC-DC driving in a wide operating voltage range according to an embodiment of the present utility model is shown, the level shift circuit comprising:

A first power supply VCC is provided,

The second power supply VBOOT is a bootstrap type high-voltage power supply of the DC-DC converter; the second power supply VBOOT is a voltage formed by superposing a fixed voltage on the basis of a switch node VX of the DC-DC converter, VBOOT changes along with the change of the switch node VX, when a high-end power tube between VIN and VX is conducted, VX can jump from 0V to VIN rapidly, and when a low-end power tube between VSS and VX is conducted, VX can drop from VIN to negative voltage rapidly, and the voltage value is the current flowing through the low-end power tube multiplied by the conduction impedance of the power tube.

When the input signal is low, the signal is,

Transistors M7 and M9 of the left branch NMOS are turned off, transistor M5 of the PMOS is turned on, and the upper plate of C1 is charged to VCC through M5. The bottom plate can be flushable to 4-5V (the specific value depends on the design) at the moment of M5 conduction, but over time, the charge of the bottom plate of C1 will be discharged through M3 until M3 turns off, at which time the gate voltage of the bottom plate of C1, i.e., M3, is about Vth. Thus, at this time M1 is in the off state, M11 is on, and I1 has a weak pull down on the source of MA through M11.

1. The moment when the input signal jumps from low to high

The left branch, M7 and M9 are on, M5 is off, the C1 upper plate begins to discharge through M7 and M9, the C1 lower plate discharges through M9, the C1 lower plate voltage is pulled down from Vth to approximately 0V, and M11 is off. Thus, at this time M1 is in an off state, and the weak pull-down of I1 to the source of MA is also off.

The right branch, M8 and M10 are turned off, M6 is turned on, VCC charges the C2 upper polar plate through M6 at this time, and the voltage of the C2 lower polar plate also rises rapidly due to the characteristic of the capacitor holding voltage, so that M2 is in a strong pull-down state at this time. At the same time, M12 is also on and the weak pull-down of I2 is also active.

2. After the input signal jumps high

The left branch, M7 and M9, are on, M11 is off, M1 remains off, and I1 remains off for weak pull-down of the source of MA.

The right branch, M8 and M10, is off and M6 is on. The upper C2 plate is still VCC and the lower C2 plate voltage discharges through M4 until M4 turns off, at which point the lower C2 plate voltage is about one Vth. At this point, M2 is in the off state, while the weak pull-down of I2 also continues to be in the active state.

The moment when the input signal jumps from low to high

According to the description of the jump instant, at this time, left Bian Zhilu M1 is turned off, I1 is also turned off by M11, and M2 is in a strong pull-down state,

Observing the circuit between VBOOT and LX, where point A has no pull-down capability, it will be pulled up to VBOOT-Vth by M13, where the currents of M13, M15, M17, M19 and M21 approach 0.

The point B is strongly pulled down by M2 to generate a large current, and the large current is mirrored through M16, M18, M20 and M21, and finally a current comparison is generated between M16 and M21, so that an output high-low level signal is generated,

The transistors MA and MB are selected from high-voltage NMOS, so that the transistors M1 and M2 are protected, the voltage breakdown problem is avoided, and the high-voltage isolation function is realized. The transistors M13 and M14 are low-voltage PMOS, and the points A and B can quickly follow the voltage change of VBOOT in a diode connection mode, so that devices between VBOOT and LX work in the voltage range of VBOOT-LX.

The core point of the circuit operation is that the pull-down capability of the transistor M1 or M2 is enhanced at the moment of the input signal overturning by utilizing the capacitive bootstrap characteristic, the smooth overturning of the circuit node LX under low voltage is ensured, and the overturning speed can be accelerated.

When the input signal IN is shifted 1 from 0, the right branch is observed, and at this time, the transistors M8 and M10 are turned from on to off, and the transistor M6 is turned from off to on, and the first power supply VCC rapidly charges the upper plate of the capacitor C2 through the transistor M6. Because the capacitor has the characteristic of keeping charge, the C2 lower polar plate can be quickly pulled up, so that the M2 pull-down capability is quickly increased in a short time, and the discharge of the point B is ensured. Looking at the left branch, transistors M7 and M9 change from off to on, capacitor C1 discharges primarily through M7 and M9, the current through M3 is small, the pull-down capability of M1 is weak, and M11 turns off the pull-down of the I1 current source.

Transistor M2 now has a strong pull-down current I2 and is mirrored through transistor M14 to transistor M16. Transistor M1 is a weak pull-down current and is mirrored through transistor M13 to transistor M15, and the current of transistor M15 flows into transistor M19 and is mirrored to transistor M21. The currents of transistors M1 and M2 are mirrored, eventually forming a comparison between the currents of transistors M21 and M16, and generating a high-low signal of the output voltage.

The present utility model has been described in detail with reference to the specific embodiments thereof, and it will be understood by those skilled in the art that the description is illustrative and that various modifications and changes can be made therein without departing from the spirit and scope of the utility model as defined by the appended claims.

Claims

1. A high voltage level shifter circuit suitable for DC-DC driving over a wide operating voltage range, the level shifter circuit comprising:

A first power supply VCC is provided,

The second power supply VBOOT is a bootstrap type high-voltage power supply of the DC-DC converter; the second power supply VBOOT is a voltage formed by superposing a fixed voltage on the basis of the switching node voltage VX of the DC-DC converter, and VBOOT changes along with the change of the switching node voltage VX;

A logic input terminal IN for receiving a logic input signal of the first power supply VCC at a high level and inputting a level signal to the circuit;

the two capacitances C1, C2,

The left branch comprises a transistor M7, a transistor M9 and a transistor M5,

The right branch comprises a transistor M8, a transistor M10 and a transistor M6.

2. A wide operating voltage range high voltage level shifter circuit suitable for DC-DC drive as set forth in claim 1,

Transistor M5 is connected in turn to transistor M3 and transistor M1, transistor M6 is connected in turn to transistor M4 and transistor M2, transistor M2 has a strong pull-down current I2 and is mirrored to transistor M16 through transistor M14, and transistor M1 is a weak pull-down current and is mirrored to transistor M15 through transistor M13.

3. A wide operating voltage range high voltage level shifter circuit suitable for DC-DC drive as set forth in claim 1,

Also included are switching transistor M11, switching transistor M12 and current sources I1, I2, with one and only one of switching transistor M11 and switching transistor M12 being in an on state.