CN221507020U - Inter-harmonic measuring device based on FPGA and STM32 - Google Patents
Inter-harmonic measuring device based on FPGA and STM32 Download PDFInfo
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- CN221507020U CN221507020U CN202323510581.7U CN202323510581U CN221507020U CN 221507020 U CN221507020 U CN 221507020U CN 202323510581 U CN202323510581 U CN 202323510581U CN 221507020 U CN221507020 U CN 221507020U
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Abstract
The utility model belongs to the technical field of digital signal processing, and relates to an inter-harmonic measurement device based on an FPGA (field programmable gate array) and an STM (structure-switching matrix) 32, which comprises a signal processing circuit, an A/D (analog to digital) converter, an FPGA computing system, an STM32 control system and a main board, wherein the main board is provided with the FPGA computing system and the STM32 control system, the signal processing circuit is electrically connected with the A/D converter, the A/D converter is electrically connected with the FPGA computing system, the FPGA computing system is electrically connected with the STM32 control system, and the signal processing circuit comprises a signal acquisition circuit and an adjustable amplifying circuit and consists of a U1 analog switch, a U3 analog switch, a U2 operational amplifier and a U4 operational amplifier. In the utility model, STM32 and FPGA complement each other, and the inter-harmonic measuring device has the advantages of high precision and high speed.
Description
Technical Field
The utility model belongs to the technical field of digital signal processing, and particularly relates to an inter-harmonic measuring device based on an FPGA (field programmable gate array) and an STM (STM 32), which is used for monitoring the quality of electric energy.
Background
The inter-harmonic components in the power system not only can disturb the stable operation of the power equipment, but also can cause waveform distortion of current and voltage, so that the utilization rate of electric energy is reduced. The existence of inter-harmonics can aggravate the aging and degradation of the power equipment, shorten the service life of the power equipment, and even endanger personal safety when serious.
At present, an inter-harmonic measuring device based on a flicker measuring principle given by IEC61000-4-7 standard is complex in structure and high in cost. The device for synchronously measuring the inter-harmonic based on the phase-locked loop circuit needs to adopt a hardware phase-locked loop to carry out frequency multiplication sampling, and has higher realization difficulty and poorer flexibility. Inter-harmonic wave measurement is carried out based on the virtual instrument and the acquisition card, and a computer is required to cooperate, so that the device is inconvenient to install and apply.
Disclosure of utility model
In order to solve the technical problems, the utility model provides an inter-harmonic measuring device based on an FPGA (field programmable gate array) and an STM (solid state memory) 32, which takes the FPGA and the STM32 as control cores and combines the existing FFT algorithm, so that the inter-harmonic of multiple paths of voltages and currents can be measured in real time and with high precision, and the content of the inter-harmonic and the effective value can be displayed. The technical scheme adopted by the utility model is as follows:
The utility model provides an interharmonic measuring device based on FPGA and STM32, includes signal processing circuit, AD converter, FPGA computing system, STM32 control system and mainboard, carry on FPGA computing system and STM32 control system on the mainboard, signal processing circuit and AD converter electric connection, AD converter and FPGA computing system electric connection, FPGA computing system and STM32 control system electric connection, signal processing circuit includes signal acquisition circuit and adjustable amplifier circuit.
Preferably, the signal processing circuit includes: the voltage signal input sampling resistor comprises a U1 analog switch, a U3 analog switch, a U2 operational amplifier and a U4 operational amplifier, wherein a voltage signal is input into one end of the sampling resistor R1, one end of the sampling resistor R3 is connected to GND, the other ends of the R1 and the R3 are connected with an input pin 3 of the U1, one end of the sampling resistor R4 is connected to GND, the other end of the R4 is connected with an input pin 14 of the U1, output pins 2 and 15 of the U1 are connected with an inverting input pin 2 of the U2, the normal phase input pin 3 of the U2 is connected with GND through a resistor R2, the input pin 2 of the U2 is connected with one end of the resistors R5 and R6, the output pin 6 of the U2 is connected with output pins 10 and 7 of the U3, the other end of the R5 is connected with input pins 3 and 11 of the U3, the other end of the R6 is connected with the input pins 6 and 14 of the U3, the output pins 2 and 15 of the U4 are connected with the normal phase input pin 5 of the U4, the inverting input pin 6 of the U4 is connected with one end of the resistors R7 and R8, and the other end of the R8 is connected with the GND, and the output pin 7 of the U4 is connected with the output pin 7.
Preferably, the STM32 control system is connected to the serial port communication interface and the internet port communication interface of the motherboard respectively.
Preferably, a serial port screen and a USB interface are arranged on the front panel of the measuring device, the USB interface is electrically connected with the main board, and the serial port screen is electrically connected with the STM32 control system.
Preferably, the a/D converter is an AD76932 analog/digital converter.
Preferably, the FPGA computing system employs a purple light PGL50G.
Preferably, the STM32 control system adopts an STM32H743VITE chip.
Preferably, the mainboard adopts AN87600-MAIN mainboard.
The utility model has the advantages that:
Utilize STM32 and FPGA to realize inter-harmonic measuring device, effectively integrated the advantage of two part cores: STM32 has rich peripheral interfaces and the capability of processing digital and analog signals simultaneously; the FPGA has high sampling speed and huge data processing capacity, and the measurement of the inter-harmonic is realized by utilizing the existing FFT algorithm in the FPGA, so that the FPGA has the advantages of high precision and high speed. The STM32 and the FPGA are complementary to each other and complement each other.
Drawings
In order to more clearly illustrate the embodiments of the present utility model, or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below. It is apparent that the drawings in the following description are specific embodiments of the utility model and that other drawings within the scope of the utility model may be obtained from these drawings by those skilled in the art without inventive effort.
FIG. 1 is a hardware configuration diagram of an inter-harmonic measurement device according to an embodiment of the present utility model;
Fig. 2 is a block diagram of a signal processing circuit of an embodiment of the present utility model;
FIG. 3 is a flow chart of the computation of inter-harmonics in accordance with an embodiment of the present utility model.
Detailed Description
The following description of the embodiments of the present utility model will be made apparent and complete in conjunction with the accompanying drawings, in which it is evident that the embodiments described are some, but not all embodiments of the present utility model.
As shown in FIG. 1, the inter-harmonic measurement device based on the FPGA and the STM32 comprises a signal processing circuit, an A/D converter, an FPGA computing system, an STM32 control system and a main board. The system is characterized in that an FPGA computing system and an STM32 control system are carried on the main board, the main board platform provides conditions for high-speed data processing, the signal processing circuit is electrically connected with the A/D converter, the A/D converter is electrically connected with the FPGA computing system, the FPGA computing system is electrically connected with the STM32 control system, the STM32 control system is respectively connected with a serial port communication interface and a network port communication interface of the main board, a serial port screen (for displaying data by utilizing serial port communication) and a USB interface are arranged on a front panel of the measuring device, the USB interface is electrically connected with the main board, and the serial port screen is electrically connected with the STM32 control system. The mainboard adopts AN87600-MAIN, and the STM32 control system is mounted on the mainboard, and the FPGA computing system is connected with the mainboard in AN inserting way.
220V alternating current is converted into 12V direct current through a filter and an AC/DC (alternating current/direct current) converter, and then is converted into 5V and 3.3V power sources through a DCDC (direct current conversion device) to supply power to each chip and circuit.
As shown in fig. 2, the signal processing circuit includes a signal acquisition circuit and an adjustable amplifying circuit, and the signal processing circuit can convert the measured voltage signal into a signal suitable for the a/D range (the system is designed to be minus 5 to plus 5V). The voltage signal is input into one end of a sampling resistor R1, one end of the sampling resistor R3 is connected to GND, the other ends of the sampling resistor R1 and the sampling resistor R3 are connected with an input pin 3 of a U1 analog switch DG444DY, one end of a sampling resistor R4 is connected to GND, the other end of the sampling resistor R4 is connected with an input pin 14 of U1, and the R4 is used for selecting an input signal to be a voltage signal or a hardware zero signal. Output pins 2 and 15 of the U1 analog switch are connected to inverting input pin 2 of U2 operational amplifier OPA134U, and non-inverting input pin 3 of the U2 operational amplifier is connected to GND through resistor R2. The input pin 2 of the operational amplifier U2 is simultaneously connected with one ends of the resistors R5 and R6, the output pin 6 of the U2 is connected with the output pins 10 and 7 of the U3 analog switch DG444DY, the other end of the R5 is respectively connected with the input pins 3 and 11 of the U3 analog switch, the other end of the R6 is respectively connected with the input pins 6 and 14 of the U3 analog switch, the output pins 2 and 15 of the U3 analog switch are connected together to serve as output, the U3 analog switch and peripheral electronic elements form an adjustable amplifying circuit, and the amplification factor is controlled by adjusting the switch state of the U3 analog switch. The output pins 2 and 15 of the U3 analog switch are connected to the non-inverting input pin 5 of the U4 operational amplifier 4572, the inverting input pin 6 of the U4 is respectively connected with one ends of the resistors R7 and R8, the other end of the R8 is connected to GND (analog ground), and the other end of the R7 is connected with the output pin 7 of the U4.
The voltage signal is acquired from the input end through the sampling resistors R1 and R3 by a resistor voltage division method, and when current is acquired, the current signal is converted into the voltage signal through the sampling resistor, and the subsequent processing is consistent with the voltage sampling. The output pin 7 is used as the output end of the signal processing circuit to convert the tested signal into a signal suitable for the A/D range and then output the signal.
The A/D converter comprises a group UADC (voltage analog/digital converter) and IADC (current analog/digital converter), and an AD76932 analog/digital converter is selected, the highest sampling rate is 500kSPS, the 16-bit precision is achieved, and the input range is +/-5V. The SPI serial interface is connected with the FPGA computing system, and the connection mode can enable the bus to be connected with a plurality of A/D converters, so that the test requirement of one path of voltage and current can be met, and the test of multiple paths of voltage and current can be expanded.
The FPGA computing system adopts a purple light PGL50G and is mainly responsible for controlling the A/D converter to sample and controlling the analog switches U1 and U3 to switch the measuring range according to the instruction of the STM32 control system. The core operation of the inter-harmonic measurement device is completed by the FPGA computing system, which comprises accumulation and calculation and FFT algorithm execution, and the operation result and waveform data are transmitted to the STM32 control system for subsequent processing. The connection between the FPGA computing system and the STM32 control system adopts an FMC bus interface, and an IP core tool is used for generating a FIFO (data storage buffer) by using a block RAM (random access memory) inside the FPGA computing system for transmitting data between the FPGA computing system and the ARM.
The STM32 control system adopts an STM32H743VITE chip as a core, has high-speed running speed and rich user interface functions, is a control core of an inter-harmonic measurement device, completes the distribution of an operating system and each task, and performs post-operation on the FFT result to obtain the final result of the inter-harmonic.
The foregoing measurement method of the inter-harmonic measurement apparatus is related art, as shown in fig. 3, and the following describes the inter-harmonic measurement method according to the present utility model in further detail with reference to the specific embodiment:
1. The A/D converter measures the harmonic source frequency, the STM32 control system calculates and gives the sampling frequency of the FPGA according to the harmonic source frequency, for example, 50Hz of the harmonic source signal, and the sampling frequency calculation formula is shown as follows: sampling frequency=harmonic source frequency/number of sampling periods×harmonic sampling point×k, resulting in sampling frequency=50/10×1024×39= 199680;
2. The A/D converter samples according to the sampling frequency obtained in the step 1, and converts the analog signal processed by the signal processing circuit into a digital signal;
3. The FPGA computing system carries out K frequency division processing on the sampling signal, 10 periods of the sampling signal are acquired, the sampling point number is 1024, the FPGA carries out FFT computation on the 1024 data after resampling to obtain the real part and the imaginary part results of each frequency component with the frequency interval of 5Hz, and the amplitude information of each frequency component is obtained;
4. the STM32 control system obtains amplitude information of each frequency with a frequency interval of 5Hz from the FPGA computing system, and calculates the content of each subharmonic. Parameters such as inter-harmonic, harmonic subgroup, harmonic group and the like are obtained through the contents of the subharmonic. And then display them on the serial screen.
According to the inter-harmonic measuring device based on the FPGA and the STM32, voltage and current signals are detected and processed through the signal processing circuit, then are converted and processed through the AD converter and transmitted to the FPGA computing system for early-stage operation, and the STM32 control system performs later-stage operation and achieves a human-computer interaction function.
In the embodiments of the present utility model, technical features that are not described in detail are all existing technologies or conventional technical means, and are not described herein.
Finally, it should be noted that: the above examples are only specific embodiments of the present utility model, and are not intended to limit the scope of the present utility model. Those skilled in the art will appreciate that: any person skilled in the art may modify or easily conceive of changes to the technical solutions described in the foregoing embodiments or make equivalent substitutions for some of the technical features within the technical scope of the present disclosure; such modifications, changes or substitutions do not depart from the spirit and scope of the technical solutions of the embodiments of the present utility model, and are intended to be included in the scope of the present utility model.
Claims (8)
1. The inter-harmonic measurement device based on the FPGA and the STM32 is characterized by comprising a signal processing circuit, an A/D converter, an FPGA computing system, an STM32 control system and a main board, wherein the main board is provided with the FPGA computing system and the STM32 control system, the signal processing circuit is electrically connected with the A/D converter, the A/D converter is electrically connected with the FPGA computing system, the FPGA computing system is electrically connected with the STM32 control system, and the signal processing circuit comprises a signal acquisition circuit and an adjustable amplifying circuit.
2. An inter-harmonic measurement device based on an FPGA and STM32 as claimed in claim 1, wherein the signal processing circuitry comprises: the voltage signal input sampling resistor comprises a U1 analog switch, a U3 analog switch, a U2 operational amplifier and a U4 operational amplifier, wherein a voltage signal is input into one end of the sampling resistor R1, one end of the sampling resistor R3 is connected to GND, the other ends of the R1 and the R3 are connected with an input pin 3 of the U1, one end of the sampling resistor R4 is connected to GND, the other end of the R4 is connected with an input pin 14 of the U1, output pins 2 and 15 of the U1 are connected with an inverting input pin 2 of the U2, the normal phase input pin 3 of the U2 is connected with GND through a resistor R2, the input pin 2 of the U2 is connected with one end of the resistors R5 and R6, the output pin 6 of the U2 is connected with output pins 10 and 7 of the U3, the other end of the R5 is connected with input pins 3 and 11 of the U3, the other end of the R6 is connected with the input pins 6 and 14 of the U3, the output pins 2 and 15 of the U4 are connected with the normal phase input pin 5 of the U4, the inverting input pin 6 of the U4 is connected with one end of the resistors R7 and R8, and the other end of the R8 is connected with the GND, and the output pin 7 of the U4 is connected with the output pin 7.
3. The inter-harmonic measurement device based on the FPGA and the STM32 according to claim 1, wherein the STM32 control system is respectively connected with a serial port communication interface and a network port communication interface of the main board.
4. The device for measuring inter-harmonics based on the FPGA and the STM32 according to claim 1, wherein a serial port screen and a USB interface are arranged on a front panel of the measuring device, the USB interface is electrically connected with the main board, and the serial port screen is electrically connected with the STM32 control system.
5. An inter-harmonic measurement device based on FPGA and STM32 as claimed in claim 1, wherein the a/D converter is an AD76932 analog/digital converter.
6. An inter-harmonic measurement device based on an FPGA and STM32 as claimed in claim 1, wherein the FPGA computing system employs a purple light PGL50G.
7. An interharmonic measurement device based on an FPGA and an STM32 as claimed in claim 1, wherein the STM32 control system employs an STM32H743VITE chip.
8. AN inter-harmonic measurement device based on FPGA and STM32 as claimed in claim 1, wherein the motherboard is AN87600-MAIN motherboard.
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| CN202323510581.7U CN221507020U (en) | 2023-12-22 | 2023-12-22 | Inter-harmonic measuring device based on FPGA and STM32 |
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| CN202323510581.7U CN221507020U (en) | 2023-12-22 | 2023-12-22 | Inter-harmonic measuring device based on FPGA and STM32 |
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