CN221263809U - Optical communication circuit and optical transceiver - Google Patents

Abstract

The utility model discloses an optical communication circuit and an optical transceiver. The circuit comprises: the optical transmitter comprises a signal receiving module, a serializer, an optical transmitting module, an optical receiving module, a deserializer and a signal output module. The signal receiving module level signal is converted into an input parallel level signal; the serializer is connected with the signal receiving module; the serializer converts the input parallel level signal into input serial data; the light emitting module is coupled with the serializer; the optical transmitting module generates an optical signal according to the input serial data; the light receiving module is connected with the light emitting module through an optical fiber; the optical receiving module converts the optical signal into output serial data; the deserializer is coupled with the light receiving module; the deserializer converts the output serial data into an output parallel level signal; the signal output module is connected with the deserializer; the signal output module converts the output parallel level signal into a level signal. The embodiment of the utility model is beneficial to improving the transmission rate of the low-speed signal and reducing the communication cost of the low-speed signal.

Description

Optical communication circuit and optical transceiver

Technical Field

The present utility model relates to the field of optical transceiver technologies, and in particular, to an optical communication circuit and an optical transceiver.

Background

In the communication of low-rate devices, cable connection is currently adopted, and communication is performed by means of electric signals. Because the low-rate equipment can only transmit one signal at a time when communicating, the transmission rate of communication signals is lower, and a plurality of cables are required to be erected when the simultaneous transmission of a plurality of signals is required, the communication cost is higher.

Disclosure of utility model

The utility model provides an optical communication circuit and an optical transceiver, which are used for improving the transmission rate of low-speed signals and reducing the communication cost of the low-speed signals.

According to an aspect of the present utility model, there is provided an optical communication circuit comprising:

The signal receiving module is used for converting an input level signal into an input parallel level signal;

The first end of the serializer is connected with the signal receiving module; the serializer is used for converting the input parallel level signal into input serial data;

The second end of the serializer is coupled with the first end of the light emitting module through the input differential module; the third end of the serializer is coupled and connected with the second end of the light emitting module through the input differential module; the optical transmitting module is used for generating an optical signal according to the input serial data differentially input by the serializer;

the first end of the light receiving module is connected with the third end of the light emitting module through an optical fiber; the optical receiving module is used for converting the optical signal into output serial data;

The second end of the light receiving module is coupled with the first end of the deserializer through an output differential module; the third end of the light receiving module is coupled and connected with the second end of the deserializer through the output differential module; the deserializer is used for converting the output serial data differentially input by the light receiving module into an output parallel level signal;

The signal output module is connected with the third end of the deserializer; the signal output module is used for converting the output parallel level signal into a level signal and outputting the level signal.

Optionally, the signal receiving module includes: the first signal conversion unit and the first signal switching unit;

the first signal conversion unit and the first signal switching unit are connected with the serializer;

The first signal conversion unit is used for converting an input level signal into an input parallel level signal and outputting the input parallel level signal to the serializer; the first signal switching unit is used for switching the input parallel level signal to the serializer.

Optionally, the first signal conversion unit includes at least one of an RS232 level circuit or an RS422 level circuit.

Optionally, the serializer includes: the device comprises a multipath parallel input unit, an input latch, a first balance encoder, a parallel-serial unit, a first driving unit, a first phase-locked loop circuit and a time sequence controller;

The first ends of the multipath parallel input units are connected with the signal receiving module; the second end of the multipath parallel input unit is connected with the first end of the input latch; a second end of the input latch is connected with a first end of the first balance encoder; the second end of the first balance encoder is connected with the first end of the parallel-serial unit; the second end of the parallel-serial unit is connected with the first end of the first driving unit; the second end of the first driving unit is connected with the light emitting module; the third end of the first driving unit is connected with the light emitting module; a first end of the first phase-locked loop circuit is connected with a third end of the input latch; a second end of the first phase-locked loop circuit is connected with a third end of the first balance encoder; the third end of the first phase-locked loop circuit is connected with the third end of the parallel-to-serial unit; the first end of the time schedule controller is connected with the fourth end of the first phase-locked loop circuit; the fourth end of the first driving unit is connected with the second end of the time sequence controller;

The multipath parallel input unit is used for acquiring input parallel level signals; the input latch is used for storing signal states; the first balance encoder is used for direct current balance encoding; the parallel-to-serial unit is used for converting the input parallel level signal into the serial data; the first driving unit is used for driving the serial data output according to a control signal; the first phase-locked loop circuit is used for controlling the input latch, the first balance encoder and the parallel-serial unit to work according to clock signals; the time schedule controller is used for controlling the first phase-locked loop circuit and the first driving unit to work according to the enabling signal.

Optionally, the light emitting module includes: the device comprises a data input unit, a laser modulation unit, a laser, a temperature compensation circuit and a drive control circuit;

The first end of the data input unit is connected with the serializer; the second end of the data input unit is connected with the laser modulation unit; the second end of the laser modulation unit is connected with the first end of the laser; the first end of the temperature compensation circuit is connected with the third end of the laser modulation unit; the second end of the temperature compensation circuit is connected with the first end of the drive control circuit; and a second end of the drive control circuit is connected with a second end of the laser.

Optionally, the light receiving module includes: the device comprises a light detection and amplification unit, a limiting amplifier, a buffer, a data output unit and a signal checking circuit;

The first end of the light detection and amplification unit is connected with the first end of the limiting amplifier; the second end of the limiting amplifier is connected with the first end of the buffer; the second end of the buffer is connected with the data output unit; the signal checking circuit is connected between the second end of the limiting amplifier and the first end of the buffer.

Optionally, the deserializer includes: the device comprises a second driving unit, a serial-parallel unit, a second balance encoder, an output latch, a multi-path parallel output unit, a second phase-locked loop circuit, a clock control circuit and a clock recovery unit;

The first end of the second driving unit is connected with the light receiving module; the second end of the second driving unit is connected with the light receiving module; the third end of the second driving unit is connected with the first end of the serial-parallel unit; the second end of the serial-parallel unit is connected with the first end of the second balance encoder; a second end of the second balance encoder is connected with a first end of the output latch; the second end of the output latch is connected with the multipath parallel output unit; the first end of the second phase-locked loop circuit is connected between the third end of the second driving unit and the first end of the serial-parallel unit; the second end of the second phase-locked loop circuit is connected with the clock control circuit; a third end of the second phase-locked loop circuit is connected with the clock recovery unit;

The second driving unit is used for driving the output serial data; the serial-parallel unit is used for converting the output serial data into an output parallel level signal; the second balance encoder is used for decoding; the output latch is used for storing a signal state and outputting an enabling signal; the phase-locked loop circuit is used for controlling the clock control circuit and the clock recovery unit; the clock control circuit is used for outputting a locking signal; the clock recovery unit is used for outputting a clock signal.

Optionally, the signal output module includes: the second signal conversion unit and the second signal switching unit;

The second signal conversion unit and the second signal switching unit are connected with the deserializer;

The second signal conversion unit is used for converting the output parallel level signal into a level signal and outputting the level signal; the second signal switching unit is used for outputting the output parallel level signal.

Optionally, the input differential module includes: a first capacitor and a second capacitor;

The first capacitor is connected between the first end of the light emitting module and the second end of the serializer; the second capacitor is connected between the second end of the light emitting module and the third end of the serializer;

the output differential module includes: a third capacitor and a fourth capacitor;

The third capacitor is connected between the first end of the deserializer and the second end of the light receiving module; the fourth capacitor is connected between the second end of the deserializer and the third end of the light receiving module.

According to another aspect of the present utility model, there is also provided an optical transceiver including the optical communication circuit described in any one of the above embodiments.

The embodiment of the utility model unifies the form of the level signal to be transmitted into the parallel level signal through the signal receiving module, converts the low-speed input parallel level signal into the high-speed input serial data through the serializer, and transmits the input serial data into the optical transmitting module in the form of the differential signal through the input differential module. The optical transmitting module converts the input serial data into an optical signal and transmits the optical signal into the optical receiving module through an optical fiber. The optical receiving module converts the optical signal into output serial data, and transmits the output serial data to the deserializer in the form of differential signals through the output differential module. The deserializer converts the output serial data into an output parallel level signal and outputs the output parallel level signal to the signal output module. The signal output module converts the output parallel level signal into the level signal to be transmitted again, thereby realizing the optical communication transmission of the low-speed signal. Compared with the prior art, the embodiment of the utility model converts the low-speed signal into the high-speed signal through the serializer and transmits the signal through the light emitting module, the light receiving module and the optical fiber, thereby realizing the optical communication transmission of the low-speed signal, being beneficial to improving the transmission rate of the low-speed signal and reducing the communication cost of the low-speed signal.

It should be understood that the description in this section is not intended to identify key or critical features of the embodiments of the utility model or to delineate the scope of the utility model. Other features of the present utility model will become apparent from the description that follows.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present utility model, the drawings required for the description of the embodiments will be briefly described below, and it is apparent that the drawings in the following description are only some embodiments of the present utility model, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.

FIG. 1 is a schematic diagram of an optical communication circuit according to an embodiment of the present utility model;

FIG. 2 is a schematic diagram of another optical communication circuit according to an embodiment of the present utility model;

Fig. 3 is a schematic diagram of an optical transceiver according to an embodiment of the present utility model.

Detailed Description

In order that those skilled in the art will better understand the present utility model, a technical solution in the embodiments of the present utility model will be clearly and completely described below with reference to the accompanying drawings in which it is apparent that the described embodiments are only some embodiments of the present utility model, not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the present utility model without making any inventive effort, shall fall within the scope of the present utility model.

It should be noted that the terms "first," "second," and the like in the description and the claims of the present utility model and the above figures are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged where appropriate such that the embodiments of the utility model described herein may be implemented in sequences other than those illustrated or otherwise described herein. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.

The embodiment of the utility model provides an optical communication circuit. The circuit can be applied to the optical transceiver to reduce the number of communication wire harnesses of the optical transceiver and the use cost. Fig. 1 is a schematic diagram of an optical communication circuit according to an embodiment of the utility model. Referring to fig. 1, the circuit includes: the optical transmitter includes a signal receiving module 110, a serializer 120, an optical transmitting module 130, an optical receiving module 230, a deserializer 220, and a signal output module 210.

The signal receiving module 110 is configured to convert an input level signal into an input parallel level signal; a first end of the serializer 120 is connected with the signal receiving module 110; the serializer 120 is used for converting an input parallel level signal into input serial data; the second end of the serializer 120 is coupled to the first end of the light emitting module 130 through the input differential module 140; the third end of the serializer 120 is coupled to the second end of the light emitting module 130 through the input differential module 140; the optical transmitting module 130 is configured to generate an optical signal according to the input serial data differentially input by the serializer 120; the first end of the light receiving module 230 is connected to the third end of the light emitting module 130 through an optical fiber 300; the light receiving module 230 is used for converting the optical signal into output serial data; the second end of the light receiving module 230 is coupled to the first end of the deserializer 220 through the output differential module 240; the third end of the light receiving module 230 is coupled to the second end of the deserializer 220 through the output differential module 240; the deserializer 220 is used for converting the output serial data differentially input by the light receiving module 230 into an output parallel level signal; the signal output module 210 is connected with a third terminal of the deserializer 220; the signal output module 210 is configured to convert the output parallel level signal into a level signal and output the level signal.

Specifically, the signal receiving module 110 processes a level signal to be transmitted to be converted into an input parallel level signal. Wherein the level signals to be transmitted comprise parallel level signals. It should be noted that, when the level signal to be transmitted is a parallel level signal, the signal receiving module 110 does not convert the signal, but directly switches the parallel level signal to the serializer 120; when the level signal to be transmitted is a non-parallel level signal, the signal receiving module 110 converts the level signal to be transmitted into a parallel level signal and sends the parallel level signal to the serializer 120. Serializer 120 is a time division multiplexed, point-to-point serial communication technique. The input parallel level signal is actually a low-speed parallel signal. The serializer 120 encodes the input parallel level signal to convert the input parallel level signal into a high-speed serial signal, i.e., input serial data. The serializer 120 transmits the input serial data in the form of a differential signal into the light-emitting module 130 through the input differential module 140. The input serial data is output to the optical transmitting module 130 through the input differential module 140 in a single phase by the serializer 120.

The light emitting module 130 receives the input serial data and converts the input serial data into an optical signal. The light emitting module 130 transmits an optical signal into the light receiving module 230 through the optical fiber 300.

The light receiving module 230 converts the received light signal into output serial data and transmits the output serial data in the form of a differential signal to the deserializer 220 through the output differential module 240. The output serial data is output to the deserializer 220 through the output differential module 240 in a single phase by the light receiving module 230. The deserializer 220 decodes the output serial data, thereby converting the output serial data into an output parallel level signal, and outputs the output parallel level signal to the signal output module 210.

The signal output module 210 converts the output parallel level signal. Note that, when the level signal input to the signal input module 110 is a parallel level signal, the signal output module 210 does not convert the output level signal; when the level signal input into the signal input module 110 is a non-parallel level signal, the signal output module 210 converts the output level signal into a transmission-required level signal.

The output parallel level signal and the input parallel level signal are substantially the same signals; the output serial data and the input serial data are substantially the same signals; in order to facilitate understanding, the present embodiment avoids confusion, and thus distinguishes between signals before and after optical communication.

The embodiment of the present utility model unifies the form of the level signal to be transmitted into a parallel level signal through the signal receiving module 110, converts the low-speed input parallel level signal into high-speed input serial data through the serializer 120, and transmits the input serial data into the optical transmitting module 130 in the form of a differential signal through the input differential module 140. The optical transmitting module 130 converts the input serial data into an optical signal and transmits the optical signal into the optical receiving module 230 through the optical fiber 300. The optical receiving module 230 converts the optical signal into output serial data and transmits the output serial data in the form of a differential signal to the deserializer 220 through the output differential module 240. The deserializer 220 converts the output serial data into an output parallel level signal and outputs the output parallel level signal to the signal output module 210. The signal output module 210 converts the output parallel level signal into a level signal to be transmitted again, thereby realizing optical communication transmission of the low-speed signal. Compared with the prior art, the embodiment of the utility model converts the low-speed signal into the high-speed signal through the serializer 120 and transmits the signal through the light emitting module 130, the light receiving module 230 and the optical fiber 300, thereby realizing the optical communication transmission of the low-speed signal, being beneficial to improving the transmission rate of the low-speed signal and reducing the communication cost of the low-speed signal.

Fig. 2 is a schematic diagram of another optical communication circuit according to an embodiment of the utility model. Optionally, referring to fig. 2, on the basis of the above embodiment, the signal receiving module 110 includes: a first signal conversion unit 111 and a first signal transfer unit 112.

The first signal conversion unit 111 and the first signal switching unit 112 are both connected to the serializer 120; the first signal conversion unit 111 is configured to convert an input level signal into an input parallel level signal and output the input parallel level signal to the serializer 120; the first signal switching unit 112 is used for switching the input parallel level signal to the serializer 120.

Specifically, when the level signal to be transmitted is a parallel level signal, the first signal switching unit 112 switches the parallel level signal to the serializer 120; when the level signal to be transmitted is a non-parallel level signal, the first signal conversion unit 111 converts the level signal to be transmitted into a parallel level signal and transmits it to the serializer 120.

On the basis of the above embodiments, the first signal conversion unit 111 may optionally include at least one of an RS232 level circuit or an RS422 level circuit.

Optionally, with continued reference to fig. 2, the serializer 120 includes: a multi-path parallel input unit 121, an input latch 122, a first balance encoder 123, a parallel-to-serial unit 124, a first driving unit 125, a first phase-locked loop circuit 126, and a timing controller 127.

A first end of the multi-path parallel input unit 121 is connected with the signal receiving module 110; a second terminal of the multiple parallel input unit 121 is connected to a first terminal of the input latch 122; a second terminal of the input latch 122 is connected to a first terminal of a first balanced encoder 123; a second end of the first balance encoder 123 is connected to a first end of the parallel-to-serial unit 124; the second end of the parallel-serial unit 124 is connected to the first end of the first driving unit 125; a second end of the first driving unit 125 is connected to the light emitting module 130; a third end of the first driving unit 125 is connected to the light emitting module 130; a first end of the first phase-locked loop circuit 126 is connected to a third end of the input latch 122; a second end of the first phase-locked loop circuit 126 is connected to a third end of the first balanced encoder 123; a third terminal of the first phase-locked loop circuit 126 is connected to a third terminal of the parallel-to-serial unit 124; a first terminal of the timing controller 127 is connected to a fourth terminal of the first phase-locked loop circuit 126; a fourth terminal of the first driving unit 125 is connected to a second terminal of the timing controller 127; the multi-path parallel input unit 121 is configured to acquire an input parallel level signal; the input latch 122 is used to store the signal state; the first balance encoder 123 is used for dc balance encoding; the parallel-to-serial unit 124 is used for converting the input parallel level signal into serial data; the first driving unit 125 is used for driving serial data output according to the control signal; the first phase-locked loop circuit 126 is configured to control the input latch 122, the first balanced encoder 123 and the parallel-to-serial unit 124 to operate according to a clock signal; the timing controller 127 is used for controlling the first phase-locked loop circuit 126 and the first driving unit 125 to operate according to the enable signal.

The control signal, the clock signal and the enable signal may be obtained by an upper circuit, or may be generated and output of the three signals may be controlled by a dedicated control module, which is not limited in this embodiment.

Optionally, with continued reference to fig. 2, the light emitting module 130 includes: a data input unit 131, a laser modulation unit 132, a laser 133, a temperature compensation circuit 134, and a drive control circuit 135.

A first end of the data input unit 131 is connected to the serializer 120; a second end of the data input unit 131 is connected with the laser modulation unit 132; a second end of the laser modulation unit 132 is connected to a first end of the laser 133; a first end of the temperature compensation circuit 134 is connected to a third end of the laser modulation unit 132; a second terminal of the temperature compensation circuit 134 is connected to a first terminal of the drive control circuit 135; a second terminal of the drive control circuit 135 is connected to a second terminal of the laser 133.

Specifically, the data input unit 131 receives serial data transmitted from the serializer 120, and transmits the received serial data to the laser modulation unit 132. The laser modulation unit 132 controls the intensity or amplitude of the laser light emitted from the laser 133 according to the serial data, thereby converting the serial data into an optical signal. The laser 133 generates a certain amount of heat during operation, however, the laser 133 emits laser light that is affected by temperature changes. The drive control circuit 135 detects the operating temperature of the laser 133 in addition to driving the laser 133, and sends the obtained temperature to the temperature compensation circuit 134. The temperature compensation circuit 134 corrects the signal conversion accuracy of the laser modulation unit 132 according to the operating temperature of the laser 133.

Optionally, with continued reference to fig. 2, the light receiving module 230 includes: a light detection and amplification unit 231, a limiting amplifier 232, a buffer 233, a data output unit 234, and a signal check circuit 235.

A first end of the light detection and amplification unit 231 is connected to a first end of the limiting amplifier 232; a second terminal of limiting amplifier 232 is connected to a first terminal of buffer 233; a second end of the buffer 233 is connected to the data output unit 234; the signal checking circuit 235 is connected between the second terminal of the limiting amplifier 232 and the first terminal of the buffer 233.

Optionally, with continued reference to fig. 2, the deserializer 220 includes: a second driving unit 221, a serial-parallel unit 222, a second balance encoder 223, an output latch 224, a multiplexed parallel output unit 225, a second phase-locked loop circuit 226, a clock control circuit 227, and a clock recovery unit 228.

A first end of the second driving unit 221 is connected to the light receiving module 230; a second end of the second driving unit 221 is connected to the light receiving module 230; the third end of the second driving unit 221 is connected to the first end of the serial-parallel unit 222; a second end of the serial-parallel unit 222 is connected to a first end of the second balance encoder 223; a second end of the second balanced encoder 223 is connected to a first end of the output latch 224; a second end of the output latch 224 is connected to a multiple parallel output unit 225; the first end of the second phase-locked loop circuit 226 is connected between the third end of the second driving unit 221 and the first end of the serial-parallel unit 222; a second end of the second phase-locked loop circuit 226 is connected to the clock control circuit 227; a third terminal of the second phase-locked loop circuit 226 is connected to the clock recovery unit 228; the second driving unit 221 is used for driving and outputting serial data; the serial-parallel unit 222 is configured to convert output serial data into output parallel level signals; the second balance encoder 223 is used for decoding; the output latch 224 is used to store the signal state and output enable signal; the phase-locked loop circuit 226 is used for controlling the clock control circuit 227 and the clock recovery unit 228; the clock control circuit 227 is used for outputting a locking signal; the clock recovery unit 228 is used for outputting a clock signal.

Optionally, with continued reference to fig. 2, the signal output module 210 includes: a second signal conversion unit 211 and a second signal transfer unit 212.

The second signal conversion unit 211 and the second signal transfer unit 212 are connected to the deserializer 220; the second signal conversion unit 211 is configured to convert an output parallel level signal into a level signal and output the level signal; the second signal switching unit 212 is used for outputting and outputting parallel level signals.

Specifically, when the level signal input into the signal input module 110 is a parallel level signal, the second signal switching unit 212 directly outputs the output parallel level signal; when the level signal input into the signal input module 110 is a non-parallel level signal, the second signal conversion unit 211 converts the output level signal into a transmission-required level signal.

Optionally, with continued reference to fig. 2, the input differential module 140 includes: a first capacitor C1 and a second capacitor C2.

The first capacitor C1 is connected between the first end of the light emitting module 130 and the second end of the serializer 120; the second capacitor C2 is connected between the second end of the light emitting module 130 and the third end of the serializer 120.

With continued reference to fig. 2, the output differential module 240 includes: a third capacitor C3 and a fourth capacitor C4.

The third capacitor C3 is connected between the first end of the deserializer 220 and the second end of the light receiving module 230; the fourth capacitor C4 is connected between the second end of the deserializer 220 and the third end of the light receiving module 230.

The embodiment of the utility model also provides an optical transceiver. Fig. 3 is a schematic diagram of an optical transceiver according to an embodiment of the present utility model. Referring to fig. 3, the optical transceiver 10 includes the optical communication circuit 20 provided in any of the above embodiments. The optical transceiver 10 provided in the embodiment of the present utility model has the beneficial effects of the optical communication circuit 20 provided in any of the above embodiments, and will not be described herein.

It should be appreciated that various forms of the flows shown above may be used to reorder, add, or delete steps. For example, the steps described in the present utility model may be performed in parallel, sequentially, or in a different order, so long as the desired results of the technical solution of the present utility model are achieved, and the present utility model is not limited herein.

The above embodiments do not limit the scope of the present utility model. It will be apparent to those skilled in the art that various modifications, combinations, sub-combinations and alternatives are possible, depending on design requirements and other factors. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present utility model should be included in the scope of the present utility model.

Claims (10)

1. An optical communication circuit, comprising:

The signal receiving module is used for converting an input level signal into an input parallel level signal;

The first end of the serializer is connected with the signal receiving module; the serializer is used for converting the input parallel level signal into input serial data;

The second end of the serializer is coupled with the first end of the light emitting module through the input differential module; the third end of the serializer is coupled and connected with the second end of the light emitting module through the input differential module; the optical transmitting module is used for generating an optical signal according to the input serial data differentially input by the serializer;

the first end of the light receiving module is connected with the third end of the light emitting module through an optical fiber; the optical receiving module is used for converting the optical signal into output serial data;

The second end of the light receiving module is coupled with the first end of the deserializer through an output differential module; the third end of the light receiving module is coupled and connected with the second end of the deserializer through the output differential module; the deserializer is used for converting the output serial data differentially input by the light receiving module into an output parallel level signal;

The signal output module is connected with the third end of the deserializer; the signal output module is used for converting the output parallel level signal into a level signal and outputting the level signal.

2. The optical communication circuit of claim 1, wherein the signal receiving module comprises: the first signal conversion unit and the first signal switching unit;

the first signal conversion unit and the first signal switching unit are connected with the serializer;

The first signal conversion unit is used for converting an input level signal into an input parallel level signal and outputting the input parallel level signal to the serializer; the first signal switching unit is used for switching the input parallel level signal to the serializer.

3. The optical communication circuit of claim 2, wherein the first signal conversion unit comprises at least one of an RS232 level circuit or an RS422 level circuit.

4. The optical communication circuit of claim 1, wherein the serializer comprises: the device comprises a multipath parallel input unit, an input latch, a first balance encoder, a parallel-serial unit, a first driving unit, a first phase-locked loop circuit and a time sequence controller;

The first ends of the multipath parallel input units are connected with the signal receiving module; the second end of the multipath parallel input unit is connected with the first end of the input latch; a second end of the input latch is connected with a first end of the first balance encoder; the second end of the first balance encoder is connected with the first end of the parallel-serial unit; the second end of the parallel-serial unit is connected with the first end of the first driving unit; the second end of the first driving unit is connected with the light emitting module; the third end of the first driving unit is connected with the light emitting module; a first end of the first phase-locked loop circuit is connected with a third end of the input latch; a second end of the first phase-locked loop circuit is connected with a third end of the first balance encoder; the third end of the first phase-locked loop circuit is connected with the third end of the parallel-to-serial unit; the first end of the time schedule controller is connected with the fourth end of the first phase-locked loop circuit; the fourth end of the first driving unit is connected with the second end of the time sequence controller;

The multipath parallel input unit is used for acquiring input parallel level signals; the input latch is used for storing signal states; the first balance encoder is used for direct current balance encoding; the parallel-to-serial unit is used for converting the input parallel level signal into the serial data; the first driving unit is used for driving the serial data output according to a control signal; the first phase-locked loop circuit is used for controlling the input latch, the first balance encoder and the parallel-serial unit to work according to clock signals; the time schedule controller is used for controlling the first phase-locked loop circuit and the first driving unit to work according to the enabling signal.

5. The optical communication circuit of claim 1, wherein the optical transmitting module comprises: the device comprises a data input unit, a laser modulation unit, a laser, a temperature compensation circuit and a drive control circuit;

The first end of the data input unit is connected with the serializer; the second end of the data input unit is connected with the laser modulation unit; the second end of the laser modulation unit is connected with the first end of the laser; the first end of the temperature compensation circuit is connected with the third end of the laser modulation unit; the second end of the temperature compensation circuit is connected with the first end of the drive control circuit; and a second end of the drive control circuit is connected with a second end of the laser.

6. The optical communication circuit of claim 1, wherein the optical receiving module comprises: the device comprises a light detection and amplification unit, a limiting amplifier, a buffer, a data output unit and a signal checking circuit;

The first end of the light detection and amplification unit is connected with the first end of the limiting amplifier; the second end of the limiting amplifier is connected with the first end of the buffer; the second end of the buffer is connected with the data output unit; the signal checking circuit is connected between the second end of the limiting amplifier and the first end of the buffer.

7. The optical communication circuit of claim 1, wherein the deserializer comprises: the device comprises a second driving unit, a serial-parallel unit, a second balance encoder, an output latch, a multi-path parallel output unit, a second phase-locked loop circuit, a clock control circuit and a clock recovery unit;

The first end of the second driving unit is connected with the light receiving module; the second end of the second driving unit is connected with the light receiving module; the third end of the second driving unit is connected with the first end of the serial-parallel unit; the second end of the serial-parallel unit is connected with the first end of the second balance encoder; a second end of the second balance encoder is connected with a first end of the output latch; the second end of the output latch is connected with the multipath parallel output unit; the first end of the second phase-locked loop circuit is connected between the third end of the second driving unit and the first end of the serial-parallel unit; the second end of the second phase-locked loop circuit is connected with the clock control circuit; a third end of the second phase-locked loop circuit is connected with the clock recovery unit;

The second driving unit is used for driving the output serial data; the serial-parallel unit is used for converting the output serial data into an output parallel level signal; the second balance encoder is used for decoding; the output latch is used for storing a signal state and outputting an enabling signal; the phase-locked loop circuit is used for controlling the clock control circuit and the clock recovery unit; the clock control circuit is used for outputting a locking signal; the clock recovery unit is used for outputting a clock signal.

8. The optical communication circuit of claim 1, wherein the signal output module comprises: the second signal conversion unit and the second signal switching unit;

The second signal conversion unit and the second signal switching unit are connected with the deserializer;

The second signal conversion unit is used for converting the output parallel level signal into a level signal and outputting the level signal; the second signal switching unit is used for outputting the output parallel level signal.

9. The optical communication circuit of claim 1, wherein the input differential module comprises: a first capacitor and a second capacitor;

The first capacitor is connected between the first end of the light emitting module and the second end of the serializer; the second capacitor is connected between the second end of the light emitting module and the third end of the serializer;

the output differential module includes: a third capacitor and a fourth capacitor;

The third capacitor is connected between the first end of the deserializer and the second end of the light receiving module; the fourth capacitor is connected between the second end of the deserializer and the third end of the light receiving module.

10. An optical transceiver comprising an optical communication circuit as claimed in any one of claims 1 to 9.