CN221202178U

CN221202178U - Charging docking station circuit and automobile

Info

Publication number: CN221202178U
Application number: CN202322691395.1U
Authority: CN
Inventors: 王豪
Original assignee: Guangdong Jike Intelligent Technology Co ltd
Current assignee: Guangdong Jike Intelligent Technology Co ltd
Filing date: 2023-10-08
Publication date: 2024-06-21
Anticipated expiration: 2033-10-08

Abstract

The utility model provides a charging docking station circuit and an automobile, wherein in the charging docking station circuit, a first input port and a second input port are respectively used for being electrically connected with an external first output interface and an external second output interface and are respectively electrically connected with a first decoy circuit, a first switch circuit, a second decoy circuit and a second switch circuit; the control ends of the first switch circuit and the second switch circuit are respectively and electrically connected with a first power supply control end and a second power supply control end of the main control circuit; the output end of each of the first switch circuit and the second switch circuit, the power supply end of the main control circuit and the input end of the first buck-boost circuit are electrically connected; the communication end and the input end of the first quick charge protocol circuit are respectively and electrically connected with the first communication end of the main control circuit and the output end of the first buck-boost circuit; the output end of the first fast charging protocol circuit is electrically connected with the first output port, so that the technical scheme of the charging docking station for improving external power in a superposition mode is realized.

Description

Charging docking station circuit and automobile

Technical Field

The utility model relates to the technical field of charging, in particular to a charging docking station circuit and an automobile.

Background

At present, electronic products are widely applied, and a charging technical scheme for solving the charging problem of the electronic products is also continuously developed, so that most of low-power electronic products can directly solve the charging problem through a conventional USB port and the like at present, and the charging is convenient and quick. However, with the development of electronic technology, the problem of charging of high-power electronic products is also urgently needed to be solved, such as the charging problem of a notebook computer, at present, the notebook computer is generally charged through a household 220V power interface under the action of a transformer, most of vehicle-mounted power supplies can not meet the requirement of high-power charging through a Type-C interface arranged under the condition of outdoor activities when the vehicle is driven, for example, two types-C are arranged in a handrail box of an electric automobile of a certain model, the maximum power of a single Type-C is 9V/3A, power can not be supplied to higher-power electronic equipment (such as a notebook computer of 20V/2.25A), and the charging is inconvenient.

Therefore, a more convenient technical scheme capable of supplying power to the high-power electronic equipment based on the existing Type-C interface is needed.

Disclosure of utility model

In order to solve the technical problems, the utility model provides a charging docking station circuit and an automobile.

The technical scheme adopted for solving the technical problems is as follows: a charging docking station circuit comprises a first input port, a second input port, a first decoy circuit, a second decoy circuit, a first switch circuit, a second switch circuit, a main control circuit, a first buck-boost circuit, a first fast charge protocol circuit and a first output port;

the first input port is used for being electrically connected with an external first output interface and is respectively and electrically connected with the input ends of the first decoy circuit and the first switch circuit;

The second input port is used for being electrically connected with an external second output interface and is respectively and electrically connected with the input ends of the second decoy circuit and the second switch circuit;

The control end of the first switch circuit is electrically connected with the first power supply control end of the main control circuit;

The control end of the second switch circuit is electrically connected with the second power supply control end of the main control circuit;

The output end of the first switch circuit is electrically connected with the output end of the second switch circuit to serve as a conversion voltage output end, and is electrically connected with the power supply end of the main control circuit and the input end of the first voltage increasing and decreasing circuit respectively;

The first communication end of the main control circuit is electrically connected with the communication end of the first quick charge protocol circuit;

the output end of the first buck-boost circuit is electrically connected with the input end of the first fast charge protocol circuit;

The output end of the first fast charge protocol circuit is electrically connected with the first output port.

Further, the circuit also comprises a first voltage sampling circuit and a second voltage sampling circuit;

the sampling end of the first voltage sampling circuit is electrically connected with the output voltage end of the first input port;

The output end of the first voltage sampling circuit is electrically connected with the first sampling end of the main control circuit;

The sampling end of the second voltage sampling circuit is electrically connected with the output voltage end of the second input port;

The output end of the second voltage sampling circuit is electrically connected with the second sampling end of the main control circuit.

Further, the first switching circuit comprises a first MOS transistor switching unit and a first triode switching unit;

the second switching circuit comprises a second MOS transistor switching unit and a second triode switching unit;

The input end of the first MOS tube switch unit is electrically connected with the output voltage end of the first input port;

the output end of the first MOS tube switching unit is used as the output end of the first switching circuit;

the control end of the first MOS transistor switch unit is electrically connected with the current collecting end of the first triode switch unit;

the base terminal of the first triode switch unit is electrically connected with the first control terminal of the main control circuit;

The input end of the second MOS tube switch unit is electrically connected with the output voltage end of the second input port;

the output end of the second MOS tube switch unit is used as the output end of the second switch circuit;

the control end of the second MOS transistor switch unit is electrically connected with the current collecting end of the second triode switch unit;

The base terminal of the second triode switch unit is electrically connected with the second control terminal of the main control circuit.

Further, the abnormal signal end of the first decoy circuit is electrically connected with the first signal detection end of the main control circuit;

The abnormal signal end of the second decoy circuit is electrically connected with the second signal detection end of the main control circuit.

Further, the circuit also comprises a second buck-boost circuit, a second fast charge protocol circuit and a second output port;

The input end of the second step-up and step-down circuit is electrically connected with the conversion voltage output end;

the output end of the second buck-boost circuit is electrically connected with the input end of the second fast charge protocol circuit;

The communication end of the second quick charge protocol circuit is electrically connected with the second communication end of the main control circuit;

the output end of the second fast charge protocol circuit is electrically connected with the second output port.

Further, the circuit also comprises a step-down circuit, an identification circuit, a third output port and a fourth output port;

the input end of the step-down circuit is electrically connected with the conversion voltage output end;

The output end of the voltage reduction circuit is electrically connected with the voltage end of the identification circuit, the voltage end of the third output port and the voltage end of the fourth output port respectively;

The data end of the identification circuit is electrically connected with the data end of the fourth output port;

The data end of the third output port is electrically connected with the data end of the second input port.

Further, the circuit also comprises a third switch circuit;

The input end of the third switch circuit is electrically connected with the conversion voltage output end;

the output end of the third switch circuit is electrically connected with the output end of the voltage reduction circuit;

The control end of the third switch circuit is electrically connected with the third power supply control end of the main control circuit.

Further, the third switching circuit comprises a third MOS transistor switching unit and a third triode switching unit;

The input end of the third MOS transistor switch unit is electrically connected with the conversion voltage output end;

the output end of the third MOS transistor switch unit is used as the output end of the third switch circuit;

The control end of the third MOS transistor switch unit is electrically connected with the current collecting end of the third triode switch unit;

the base terminal of the third triode switch unit is electrically connected with the third control terminal of the main control circuit.

Further, the current sampling circuit is also included;

the first input end and the second input end of the current sampling circuit are respectively and electrically connected with the grounding end of the third output port and the grounding end of the fourth output port;

the output end of the current sampling circuit is electrically connected with the third sampling end of the main control circuit.

The application also provides an automobile, which comprises an automobile main body and a charging docking station circuit;

The automobile body comprises a first output interface and a second output interface;

The charging docking station circuit comprises a first input port, a second input port, a first decoy circuit, a second decoy circuit, a first switch circuit, a second switch circuit, a main control circuit, a first buck-boost circuit, a first fast charge protocol circuit and a first output port;

The first input port is electrically connected with the first output interface and is electrically connected with the input ends of the first decoy circuit and the first switch circuit respectively;

The second input port is electrically connected with the second output interface and is electrically connected with the input ends of the second decoy circuit and the second switch circuit respectively;

The utility model has the beneficial effects that: the external first output interface and the external second output interface are respectively decoy through the first decoy circuit and the second decoy circuit, under the condition that working voltage is provided for the main control circuit through the first switch circuit and the second switch circuit, the first voltage-boosting and voltage-reducing circuit and the first quick charge protocol circuit are controlled by the main control circuit to superpose the respective decoy voltage of the external first output interface and the external second output interface, and the decoy voltage is output through the first output port, so that the technical scheme of the charging docking station for improving external power in a superposition mode is realized, and the convenience for supplying power to high-power electronic equipment is improved.

Drawings

Fig. 1 is a schematic structural diagram of a charging dock circuit according to the present utility model;

Fig. 2 is a schematic structural diagram of a charging dock circuit including a voltage sampling circuit according to the present utility model;

Fig. 3 is a schematic structural diagram of a charging dock circuit including a specific structure of a switch circuit according to the present utility model;

FIG. 4 is a schematic diagram of a charging dock circuit including exception handling according to the present utility model;

fig. 5 is a schematic structural diagram of a charging dock circuit including a second output port according to the present utility model;

Fig. 6 is a schematic structural diagram of a charging dock circuit including a third output port and a fourth output port according to the present utility model;

Fig. 7 is a schematic structural diagram of a charging dock circuit including a third switch circuit according to the present utility model;

Fig. 8 is a schematic structural diagram of a charging dock circuit including a specific structure of a third switch circuit according to the present utility model;

Fig. 9 is a schematic structural diagram of a charging dock circuit including a current sampling circuit according to the present utility model;

fig. 10 is a schematic circuit diagram of a first decoy circuit of a charging dock circuit according to the present utility model;

fig. 11 is a schematic circuit diagram of a second decoy circuit of the charging dock circuit according to the present utility model;

Fig. 12 is a schematic circuit diagram of a voltage stabilizing circuit in a main control circuit of a charging docking station circuit according to the present utility model;

Fig. 13 is a schematic circuit diagram of a main control chip circuit in a main control circuit of a charging docking station circuit according to the present utility model;

Fig. 14 is a schematic circuit diagram of a 45W buck-boost circuit of a charging dock circuit according to the present utility model;

Fig. 15 is a schematic circuit diagram of a 45W fast charging protocol circuit of the charging docking station circuit according to the present utility model;

Fig. 16 is a schematic circuit diagram of a 20W buck-boost circuit of a charging dock circuit according to the present utility model;

Fig. 17 is a schematic circuit diagram of a 20W fast charging protocol circuit of the charging dock circuit according to the present utility model;

Fig. 18 is a schematic circuit diagram of a step-down circuit of a charging dock circuit according to the present utility model;

Fig. 19 is a schematic circuit diagram of a 5V output interface circuit of a charging dock circuit according to the present utility model;

fig. 20 is a schematic circuit diagram of a third switch circuit of the charging dock circuit according to the present utility model.

Detailed Description

The present utility model will be further described in detail with reference to the drawings and examples, which are only for the purpose of illustrating the utility model and are not to be construed as limiting the scope of the utility model.

Referring to fig. 1-20, an embodiment of the disclosure relates to a charging docking station circuit, which includes a first input port, a second input port, a first spoofing circuit, a second spoofing circuit, a first switch circuit, a second switch circuit, a master control circuit, a first buck-boost circuit, a first fast charging protocol circuit, and a first output port;

In this embodiment, the external first output interface and the external second output interface are common power supply USB ports of the external electronic device, for example, may be vehicle-mounted USB power supply ports, specifically, two paths of C ports of an armrest box of an electric automobile of a certain model, and the maximum power of a single C port is 9V3A, where the C port may be specifically Type-C. The types of the first input port and the second input port need to be matched to the types of the external first output interface and the external second output interface. The first decoy circuit and the second decoy circuit realize corresponding decoy functions based on a conventional decoy chip, and are used for respectively decoy an external first output interface and an external second output interface to output the highest voltage to the first switch circuit and the second switch circuit through a first input port and a second input port. The first switch circuit and the second switch circuit are switch circuits realized based on the MOS tube, when the MOS tube is cut off, the voltage output by the first input port and/or the second input port can be transmitted to the negative electrode from the positive electrode of the parasitic diode of the MOS tube, and finally, the working voltage is provided for the main control circuit. The main control circuit is used for respectively controlling the on-off of the first switch circuit and the second switch circuit so as to superimpose two highest voltages, and the power is output by the first output port after being distributed through the first buck-boost circuit and the first fast charge protocol circuit. The main control circuit is realized based on a conventional control chip, the first buck-boost circuit is realized based on a conventional buck-boost chip, and the first fast charge protocol circuit is realized based on a conventional fast charge protocol chip. The main control circuit is connected with the first quick charge protocol circuit through an I2C serial bus. The first output port may be a USB power port, such as Type-C.

In a specific embodiment, referring to fig. 10-15, the first input port is USBC1, the second input port is USBC2, and both USBC1 and USBC2 are Type-C interfaces. The external first output interface and the external second output interface are Type-C interfaces, and respectively provide 9V3A power at the highest. The first decoy circuit is implemented based on a decoy chip U1, the second decoy circuit is implemented based on a decoy chip U2, and both U1 and U2 can employ HUSB238. The first switching circuit is realized based on the PMOS tube Q1, and the second switching circuit is realized based on the PMOS tube Q3. The main control circuit consists of a voltage stabilizing circuit and a main control chip circuit. The main control chip circuit is realized based on the main control chip U13. The main control chip U13 is connected with the LED lamp D1, and when the LED lamp D1 is normally on, normal work is indicated. The main control chip U13 can control the on-off of the first switch circuit and the second switch circuit through the power_1 and the power_2 at any time according to actual needs, if only one of the USBC1 and the USBC2 is identified, only 9V/3A is taken for the identified one, the other circuit is input to be closed, the voltage reverse string is prevented, and the LED lamp D1 can be controlled to flash at the moment to indicate abnormal POWER supply. The first buck-boost circuit is implemented based on buck-boost chip U8. The first fast charge protocol circuit is implemented based on the fast charge protocol chip U10. The main control chip U13 is connected with the fast charging protocol chip U10 through a data line SDA3 and a clock line SCL 3. The first output port is USBC4, and a Type-C interface is adopted. Upon power up, CC1 and CC2 of HUSB' 238 will communicate with the power supply of the PD protocol (i.e., the external first output interface and the external second output interface) and fool the set 9V. HUSB238 is a decoy chip, which can decoy PD and QC protocols, and is equivalent to a power-taking chip. When Q1 and Q3 are not conducted, unidirectional small current provides voltage VCC_9V through diodes inside Q1 and Q3, and VCC_9V is mainly used by a main control chip U13. In this embodiment, through the PD protocol of the two-way Type-C interface (the external first output interface and the external second output interface), the maximum power of 9V/3A can be obtained, the maximum power of 9V/6A (54W) can be obtained by combining, the maximum power of 45W can be output through the buck-boost chip U8 and the fast charge protocol chip U10, and the output can be provided for notebook charging (20V/2.25A) through USBC 4. It should be noted that, IN fig. 10-20, the same symbols on the connection lines of the electronic components indicate interconnection, for example, two cc1_in1 IN fig. 10 are connected, adc_1 IN fig. 10 is connected to adc_1 IN fig. 11, csp_i and csn_i at two ends of resistor R27 IN fig. 12 are respectively connected to csp_i and csn_i on buck-boost chip U8, and the schematic circuit diagrams IN fig. 10-20 can add corresponding auxiliary electronic components and connection lines according to actual implementation needs and conventional designs so as to facilitate specific implementation of the technical scheme.

Further, referring to fig. 2, the circuit further includes a first voltage sampling circuit and a second voltage sampling circuit;

In this embodiment, the first voltage sampling circuit and the second voltage sampling circuit are conventional voltage sampling circuits, and refer specifically to fig. 10-13. The first voltage sampling circuit can be realized by two resistors R4 and R5, the second voltage sampling circuit can be realized by two resistors R9 and R10, the second sampling end ADC_2 is connected to the main control chip U13, and the actual decoy voltage is monitored through the main control chip U13, so that the on-off of the first switching circuit and the second switching circuit is controlled. The main control chip U13 is provided with a working voltage VCC_MCU by the voltage stabilizing chip U3 under the cooperation of a resistor R14, a capacitor C7, a capacitor C8, a capacitor C9 and a capacitor C10.

Further, referring to fig. 3, the first switching circuit includes a first MOS transistor switching unit and a first triode switching unit;

In this embodiment, the first MOS transistor switch unit and the second MOS transistor switch unit may be implemented based on PMOS transistors, and the first transistor switch unit and the second transistor switch unit may be implemented based on NPN transistors. In a specific embodiment, referring to fig. 10 and 11, the first MOS transistor switching unit is mainly implemented based on the PMOS transistor Q1, the first transistor switching unit is mainly implemented based on the NPN transistor Q5, the second MOS transistor switching unit is mainly implemented based on the PMOS transistor Q3, and the second transistor switching unit is mainly implemented based on the NPN transistor Q12.

Further, referring to fig. 4, the abnormal signal end of the first spoofing circuit is electrically connected to the first signal detecting end of the main control circuit;

In this embodiment, when the first spoofing circuit and/or the second spoofing circuit is abnormal in a burst, an abnormal signal may be sent to the master control circuit, and the master control circuit performs corresponding processing accordingly. In a specific embodiment, referring to fig. 10, 11 and 13, through the use of the signal transmission circuits U1 and U2, a high level signal can be sent to the main control chip U13 in the main control circuit through the gate_1 and/or gate_2, and the main control chip U13 can send a control signal through the power_1 and/or power_2 accordingly, so as to control the on/off of the first switch circuit and/or the second switch circuit, and prevent the circuit fault caused by the abnormality.

Further, referring to fig. 5, the circuit further includes a second buck-boost circuit, a second fast charge protocol circuit, and a second output port;

In this embodiment, the second buck-boost circuit is implemented based on a conventional buck-boost chip, and the second fast charge protocol circuit is implemented based on a conventional fast charge protocol chip. The main control circuit is connected with the first quick charge protocol circuit through an I2C serial bus. The second output port may be a USB power port, such as Type-C. In a specific embodiment, referring to fig. 10-17, the second output port is USBC3. Through the PD protocol of the two-way Type-C interface (the external first output interface and the external second output interface), the maximum power of 9V/3A can be obtained, the maximum power of 9V/6A (54W) can be obtained through combination, then power distribution is carried out, two types-C (USBC 3 and USBC 4) can be supplied with power, when the USBC3 and the USBC4 are simultaneously output, the power of the USBC3 can be distributed by 20W, and the power of the USBC4 can be distributed by 30W. Meanwhile, DMC and DPC between USBC3 and USBC1 interconnect, besides realizing the function of charging, can also realize the function of data transmission. It should be noted that, the implementation circuits of the second buck-boost circuit and the second fast charge protocol circuit may be added with corresponding auxiliary electronic components and connection wires according to actual needs, and may be implemented completely with reference to corresponding chip manuals.

Further, referring to fig. 6, the circuit further includes a step-down circuit, an identification circuit, a third output port, and a fourth output port;

In this embodiment, the step-down circuit is implemented based on a conventional step-down chip, the identification circuit is implemented based on a conventional USB identification chip, and the third output port and the fourth output port are USB type interfaces. In a specific embodiment, referring to fig. 18 and 19, the step-down circuit is implemented based on U11, and can convert 9V to 5V. The identification circuit is realized based on U12 and is a USB identification chip. The third output port is A1 of the USBA type, and the fourth output port is A2 of the USBA type. The data port of A1 is connected with the data port of USBC2, and A1 can be used as a 5V data port. The data port of A2 is connected with the data port of U12, and A2 can be used as a 5V charging port. When VCC_9V is 9V, VCC_5V obtained by U11 conversion is 5V.

Further, referring to fig. 7, the circuit further includes a third switch circuit;

In this embodiment, when the voltage at the output end of the converted voltage is insufficient to enable the step-down circuit to work, the third switch circuit can be controlled to be turned on by the main control circuit, and at this time, the output end of the converted voltage is directly communicated with the output end of the step-down circuit, and the output end of the converted voltage directly provides working voltages for the identification circuit, the third output port and the fourth output port.

Further, referring to fig. 8, the third switching circuit includes a third MOS transistor switching unit and a third triode switching unit;

In this embodiment, the third MOS transistor switching unit may be implemented based on a PMOS transistor, and the third transistor switching unit may be implemented based on a PNP transistor. In a specific embodiment, referring to fig. 20, the third MOS transistor switching unit is implemented based on the PMOS transistor Q14, and the third transistor switching unit is implemented based on the PNP transistor Q13. The base electrode of the PNP triode Q13 is connected with the third control end of the main control chip U13 through a resistor R62. Under the condition that VCC_9V is normal 9V, Q14 is not conducted, and if both paths (USBC 1 and USBC 2) are 5V input, the conduction of Q14 can be controlled through the main control chip U13.

Further, referring to fig. 9, the current sampling circuit is further included;

In this embodiment, the current sampling circuit is configured to detect currents of the third output port and the fourth output port, and the main control chip U13 may allocate power according to current conditions of the third output port and the fourth output port. In a specific embodiment, referring to fig. 19, the current sampling circuit is implemented by a resistor R45, and a current sampling terminal adc_3 is connected to the main control chip U13.

In a specific embodiment, at power-up, if one of the USBC1 is tricked to 9V, the corresponding Q1 is turned on. The VCC_9V end has 9V voltage; if the other path of USBC2 is not successfully trapped, and no voltage or 5V exists, the main control chip U13 judges that 9V does not exist through the ADC_2, and the Q3 is not conducted. When Q3 is in a non-conducting state and the internal diode is turned off reversely, the voltage of the end 9V of VCC_9V is isolated from the network where USBC2 is located. In this embodiment, the maximum rated power of each of A1 and A2 is 5V/2.4A (12W), and the master control chip U13 may dynamically redistribute the total power input by controlling the power output of USBC3 and USBC 4.

The above embodiments should not limit the present utility model in any way, and all technical solutions obtained by equivalent substitution or equivalent conversion fall within the protection scope of the present utility model.

Claims

1. The charging docking station circuit is characterized by comprising a first input port, a second input port, a first decoy circuit, a second decoy circuit, a first switch circuit, a second switch circuit, a main control circuit, a first buck-boost circuit, a first fast charge protocol circuit and a first output port;

2. The charging dock circuit of claim 1, further comprising a first voltage sampling circuit and a second voltage sampling circuit;

3. The charging dock circuit of claim 2, wherein the first switching circuit comprises a first MOS transistor switching unit and a first triode switching unit;

4. The charging dock circuit of claim 1, wherein the anomaly signal end of the first spoof circuit is electrically connected to the first signal detection end of the master circuit;

5. The charging dock circuit of claim 1, further comprising a second buck-boost circuit, a second fast charge protocol circuit, a second output port;

6. The charging dock circuit of claim 5, further comprising a buck circuit, an identification circuit, a third output port, a fourth output port;

7. The charging dock circuit of claim 6, further comprising a third switching circuit;

8. The charging dock circuit of claim 7, wherein the third switching circuit comprises a third MOS transistor switching unit and a third triode switching unit;

9. The charging dock circuit of claim 6, further comprising a current sampling circuit;

10. An automobile is characterized by comprising an automobile main body and a charging docking station circuit;