CN221201170U

CN221201170U - Integrated circuit chip static eliminating assembly

Info

Publication number: CN221201170U
Application number: CN202322826845.3U
Authority: CN
Inventors: 钟方彪; 田秋; 任娟
Original assignee: Shenzhen Jingcheng Micro Technology Co ltd
Current assignee: Shenzhen Jingcheng Micro Technology Co ltd
Priority date: 2023-10-20
Filing date: 2023-10-20
Publication date: 2024-06-21
Anticipated expiration: 2033-10-20

Abstract

The utility model relates to the technical field of chips and discloses an integrated circuit chip static eliminating assembly which comprises a chip body, wherein a first static-free shell and a second static-free shell are respectively arranged at the top and the bottom of the chip body, the interiors of the second static-free shells of the first static-free shells are respectively connected with a static-free material, the exteriors of the first static-free shells are fixedly connected with a first mounting plate, and the exteriors of the second static-free shells are fixedly connected with a second mounting plate. Through being equipped with first antistatic shell and second antistatic shell respectively at the top and the bottom of chip body, all be equipped with antistatic material in the inside of first antistatic shell and second antistatic shell, first antistatic shell and second antistatic shell are installed respectively at the top and the bottom of chip body, and the dead lever will insert the inside of fixed orifices, fixes first antistatic shell and second antistatic shell, and the antistatic material of inside can realize antistatic effect, convenience very during the use.

Description

Integrated circuit chip static eliminating assembly

Technical Field

The utility model relates to the technical field of chips, in particular to an integrated circuit chip static electricity eliminating component.

Background

Integrated circuits, or microcircuits, microchips, wafers/chips, are a form of miniaturization in electronics that includes mainly semiconductor devices, as well as passive components, and are often manufactured on the surface of semiconductor wafers.

Most of the integrated circuit chips on the market have the following problems when in use:

When the traditional integrated circuit chip is in actual use, when workers contact with the chip after being electrified, the phenomenon of static electricity can be generated, the anti-static effect can not be realized, and the use is very inconvenient; the toughness of the circuit board is poor when the traditional integrated circuit chip is actually used, and the corner of the circuit board is damaged to different degrees when the traditional integrated circuit chip is used for a long time, so that the service life of the integrated circuit chip is reduced.

Disclosure of utility model

In order to overcome the above-mentioned drawbacks of the prior art, the present utility model provides an integrated circuit chip static electricity eliminating assembly to solve the above-mentioned problems in the prior art.

The utility model provides the following technical scheme: the integrated circuit chip static eliminating assembly comprises a chip body, wherein a first static-free shell and a second static-free shell are respectively arranged at the top and the bottom of the chip body, static-free materials are respectively connected to the inside of the second static-free shell of the first static-free shell, the second static-free shells of the first static-free shell are in a mutually corresponding form, the first mounting plate is fixedly connected to the outside of the first static-free shell, the second mounting plate is fixedly connected to the outside of the second static-free shell, the first static-free shell and the second static-free shell are respectively arranged at the top and the bottom of the chip body, and a fixing rod is inserted into the inside of a fixing hole so as to fix the first static-free shell and the second static-free shell, and the static-free materials in the inside can realize a static-free effect, so that the integrated circuit chip static eliminating assembly is very convenient to use;

Further, the outside of chip body is equipped with first reinforcement strip and second respectively, first inner groovy is offered to the inside of first reinforcement strip, the second inner groovy is offered to the inside of second reinforcement strip, and first inner groovy and second inner groovy are inlayed respectively in the outside of chip body, can increase toughness to the four sides of chip body, and under the state of long-time use, the corner of chip body can appear the impaired condition of different degree to life-span when having increased the use has been avoided.

Further, the fixed orifices is offered to the inside of first mounting panel, second mounting panel external connection dead lever, the dead lever is connected in the inside of fixed orifices through the male mode, and when first mounting panel and second mounting panel were installed, its dead lever was fixed to first mounting panel and second mounting panel with inserting the inside of fixed orifices, conveniently.

Further, the jack is offered to the inside of first reinforcement strip, the externally connected inserted bar of second reinforcement strip, the inserted bar is connected in the inside of jack through the mode of inlaying, first reinforcement strip and second reinforcement strip all are symmetrical distribution form, first indent and second indent all connect the corner at the chip body through the mode of inlaying, can play reinforced effect to the corner of chip body.

Further, the outside connection spacing ring of dead lever, the spacing ring laminating is at the top of first mounting panel, after the dead lever inserts the inside of fixed orifices, the spacing ring will be fixed in the outside of dead lever, plays spacing effect to the dead lever.

Further, dead lever and fixed orifices all are evenly distributed form, dead lever and fixed orifices all are circular form, and the inside in fixed orifices is inserted to a plurality of dead levers simultaneous, can promote the stability when first antistatic outer shell and second antistatic outer shell use.

1. According to the utility model, the first anti-static shell and the second anti-static shell are respectively arranged at the top and the bottom of the chip body, and anti-static materials are respectively arranged in the first anti-static shell and the second anti-static shell, the first anti-static shell and the second anti-static shell are respectively arranged at the top and the bottom of the chip body, and the fixing rod is inserted into the fixing hole so as to fix the first anti-static shell and the second anti-static shell, and the anti-static materials in the inner part can realize an anti-static effect, so that the anti-static chip is very convenient to use;

2. According to the utility model, the first reinforcing strip and the second reinforcing strip are respectively arranged outside the chip body, and the first inner groove and the second inner groove are respectively inlaid outside the chip body, so that the toughness of four sides of the chip body can be increased, and the situation that the corners of the chip body are damaged to different degrees in a long-time use state is avoided, so that the service life of the chip body is prolonged.

Drawings

Fig. 1 is a schematic diagram of the overall structure of the present utility model.

Fig. 2 is a schematic diagram of a chip body structure according to the present utility model.

Fig. 3 is a schematic structural diagram of a first antistatic housing according to the present utility model.

Fig. 4 is a schematic view of a first reinforcing strip structure according to the present utility model.

Fig. 5 is a schematic view of a second reinforcing strip structure according to the present utility model.

The reference numerals are: 1. a first antistatic housing; 2. a second antistatic housing; 3. a chip body; 4. a first reinforcing strip; 5. a second reinforcing strip; 6. a first mounting plate; 7. a second mounting plate; 8. a fixed rod; 9. a limiting ring; 10. an antistatic material; 11. a fixing hole; 12. a first inner groove; 13. a jack; 14. a second inner groove; 15. and a plunger.

Detailed Description

The embodiments of the present utility model will be described more fully hereinafter with reference to the accompanying drawings, in which the embodiments of the present utility model are shown by way of illustration only, and the utility model is not limited to the embodiments of the present utility model, but other embodiments of the present utility model will be apparent to those skilled in the art without making any inventive effort.

Referring to fig. 1-5, the utility model provides an integrated circuit chip static eliminating assembly, which comprises a chip body 3, wherein a first static-free shell 1 and a second static-free shell 2 are respectively arranged at the top and the bottom of the chip body 3, the interiors of the second static-free shells 2 of the first static-free shell 1 are respectively connected with a static-free material 10, the second static-free shells 2 of the first static-free shell 1 are in a mutually corresponding form, the exteriors of the first static-free shells 1 are fixedly connected with a first mounting plate 6, and the exteriors of the second static-free shells 2 are fixedly connected with a second mounting plate 7;

the first antistatic outer shell 1 and the second antistatic outer shell 2 are respectively arranged at the top and the bottom of the chip body 3, and the fixing rod 8 is inserted into the fixing hole 11 so as to fix the first antistatic outer shell 1 and the second antistatic outer shell 2, and the antistatic material 10 inside can realize antistatic effect, so that the use is very convenient.

The outside of chip body 3 is equipped with first reinforcement strip 4 and second reinforcement strip 5 respectively, first inner groovy 12 is offered to the inside of first reinforcement strip 4, second inner groovy 14 is offered to the inside of second reinforcement strip 5, and first inner groovy 12 and second inner groovy 14 inlay respectively in the outside of chip body 3, can increase toughness to the four sides of chip body 3, and under the state of long-time use, avoided the corner of chip body 3 to appear the impaired condition of different degree to life-span when having increased the use.

Wherein, fixed orifices 11 are offered to the inside of first mounting panel 6, second mounting panel 7 external connection dead lever 8, dead lever 8 is connected in the inside of fixed orifices 11 through the male mode, and when first mounting panel 6 and second mounting panel 7 were installed, its dead lever 8 would insert the inside of fixed orifices 11, conveniently fixed first mounting panel 6 and second mounting panel 7.

The jack 13 is seted up to the inside of first reinforcement strip 4, the external connection inserted bar 15 of second reinforcement strip 5, inserted bar 15 is connected in the inside of jack 13 through the mode of inlaying, first reinforcement strip 4 and second reinforcement strip 5 all are symmetrical distribution form, first inner groove 12 and second inner groove 14 all connect the corner at chip body 3 through the mode of inlaying, can play reinforced effect to the corner of chip body 3.

Wherein, the outside of dead lever 8 is connected spacing ring 9, spacing ring 9 laminating is at the top of first mounting panel 6, after dead lever 8 inserts the inside of fixed orifices 11, and spacing ring 9 will fix in the outside of dead lever 8, plays spacing effect to dead lever 8.

Wherein, dead lever 8 and fixed orifices 11 all are the average distribution form, dead lever 8 and fixed orifices 11 all are circular form, and the inside of a plurality of dead levers 8 simultaneous insertion fixed orifices 11 can promote the stability when first antistatic backing 1 and second antistatic backing 2 use.

The working principle of the utility model is as follows: when using this integrated circuit chip static elimination subassembly, first reinforcement strip 4 and second reinforcement strip 5 are installed in the corner of chip body 3 at first, first indent 12 and second indent 14 will inlay in the outside of chip body 3, just so can fix first reinforcement strip 4 and second reinforcement strip 5, can increase toughness to the four sides of chip body 3, and under the state of using for a long time, the circumstances that the corner of chip body 3 can appear different degree impaired has been avoided, thereby the life-span when having increased, then install first antistatic backing 1 at the top of chip body 3, the bottom at chip body 3 is installed to second antistatic backing 2, and dead lever 8 inserts the inside of fixed orifices 11, and spacing ring 9 is fixed in the outside of dead lever 8 and laminating at the top of first mounting panel 6, thereby fix first antistatic backing 1 and second antistatic backing 2, and inside antistatic backing 10 can realize antistatic effect, when using very conveniently.

The last points to be described are: first, in the description of the present application, it should be noted that, unless otherwise specified and defined, the terms "mounted," "connected," and "connected" are to be construed broadly, and may be mechanical or electrical, or may be a direct connection between two elements, and "upper," "lower," "left," "right," etc. are merely used to indicate relative positional relationships, which may be changed when the absolute position of the object being described is changed;

secondly: in the drawings of the disclosed embodiments, only the structures related to the embodiments of the present disclosure are referred to, and other structures can refer to the common design, so that the same embodiment and different embodiments of the present disclosure can be combined with each other under the condition of no conflict;

Finally: the foregoing description of the preferred embodiments of the utility model is not intended to limit the utility model to the precise form disclosed, and any such modifications, equivalents, and alternatives falling within the spirit and principles of the utility model are intended to be included within the scope of the utility model.

Claims

1. An integrated circuit chip static elimination assembly, includes chip body (3), its characterized in that: the top and the bottom of chip body (3) are equipped with first antistatic outer shell (1) and second antistatic outer shell (2) respectively, antistatic material (10) are all connected to the inside of first antistatic outer shell (1) second antistatic outer shell (2), be the form that corresponds each other between first antistatic outer shell (1) second antistatic outer shell (2), the outside fixed connection first mounting panel (6) of first antistatic outer shell (1), the outside fixed connection second mounting panel (7) of second antistatic outer shell (2).

2. An integrated circuit chip static elimination assembly according to claim 1, wherein: the chip is characterized in that a first reinforcing strip (4) and a second reinforcing strip (5) are arranged outside the chip body (3) respectively, a first inner groove (12) is formed in the first reinforcing strip (4), and a second inner groove (14) is formed in the second reinforcing strip (5).

3. An integrated circuit chip static elimination assembly according to claim 1, wherein: the fixing device is characterized in that a fixing hole (11) is formed in the first mounting plate (6), the second mounting plate (7) is externally connected with a fixing rod (8), and the fixing rod (8) is connected in the fixing hole (11) in an inserting mode.

4. An integrated circuit chip static elimination assembly according to claim 2, wherein: the utility model discloses a chip, including jack (13) is offered to the inside of first reinforcement strip (4), external connection inserted bar (15) of second reinforcement strip (5), inserted bar (15) are connected in the inside of jack (13) through the mode of inlaying, first reinforcement strip (4) and second reinforcement strip (5) all are symmetrical distribution form, the corner at chip body (3) is all connected through the mode of inlaying to first indent (12) and second indent (14).

5. An integrated circuit chip static elimination assembly according to claim 3, wherein: the outside of dead lever (8) is connected with spacing ring (9), spacing ring (9) laminating is at the top of first mounting panel (6).

6. An integrated circuit chip static elimination assembly according to claim 3, wherein: the fixing rods (8) and the fixing holes (11) are uniformly distributed, and the fixing rods (8) and the fixing holes (11) are circular.