CN221007857U - Phased array TR assembly - Google Patents
Phased array TR assembly Download PDFInfo
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- CN221007857U CN221007857U CN202322707343.9U CN202322707343U CN221007857U CN 221007857 U CN221007857 U CN 221007857U CN 202322707343 U CN202322707343 U CN 202322707343U CN 221007857 U CN221007857 U CN 221007857U
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- 239000003990 capacitor Substances 0.000 claims description 80
- 239000012535 impurity Substances 0.000 claims description 32
- 238000009396 hybridization Methods 0.000 claims 3
- 238000010586 diagram Methods 0.000 description 4
- 230000010355 oscillation Effects 0.000 description 4
- 238000012899 de-mixing Methods 0.000 description 3
- 238000000034 method Methods 0.000 description 3
- 230000005540 biological transmission Effects 0.000 description 2
- 238000001514 detection method Methods 0.000 description 2
- 238000001914 filtration Methods 0.000 description 2
- 230000000903 blocking effect Effects 0.000 description 1
- 238000002592 echocardiography Methods 0.000 description 1
- 230000004807 localization Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000010363 phase shift Effects 0.000 description 1
- 230000035945 sensitivity Effects 0.000 description 1
- 238000010408 sweeping Methods 0.000 description 1
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Abstract
The application relates to a phased array TR assembly, which generates electromagnetic wave modes for interference through a waveform generator, and the waveform generator generates target wave modes by utilizing PWM and other square waves under the modulation of a plurality of transistors, so that more peak clutter can be generated after current passes through the waveform generator. In practice, the power amplifier itself is also composed of more transistors, and for this purpose, the present application provides more noise cancellation loops inside the power amplifier to reduce the generation of peak noise. The clutter removal circuit structure effectively improves the effective transmitting power of the phased array radar and reduces the resolution difficulty of the received back phased array radar TR assembly.
Description
Technical Field
The application relates to the technical field of phased array radars, in particular to a phased array TR assembly.
Background
The phased array TR assembly is totally called TRANSMITTER AND RECEIVER, one end is connected with an antenna, and the other end is connected with an intermediate frequency processing unit to form a wireless receiving and transmitting system. Its function is to amplify, phase shift and attenuate the signal.
With the localization of chip layers of phased array radars, phased array radars are widely used in the military, agricultural and meteorological fields. However, the synthetic voltage wave clutter removal capability of the traditional phased array radar is not strong, so that clutter signals exist in the sweeping electromagnetic waves transmitted by the phased array radar TR component, on one hand, the effective transmitting power of the phased array radar is reduced, and on the other hand, the analysis difficulty after the phased array radar TR component is received is increased. This results in reduced phased array radar detection efficiency, for which reason it is necessary to provide a phased array TR assembly for a conventional phased array radar.
Disclosure of utility model
Based on the problems, the phased array TR component is provided for solving the problems that the detection efficiency of the phased array radar is reduced due to the fact that the synthetic voltage wave clutter removal capability of the traditional phased array radar is not strong.
The application provides a phased array TR assembly, comprising:
the circulator is used for externally connecting the phase shifter;
A horizontal contractor electrically connected to the circulator;
a power amplifier electrically connected to the horizontal contractor;
the clutter removing circuit is electrically connected with the power amplifier;
the waveform generator is electrically connected with the clutter removal circuit;
A receiver electrically connected to the circulator;
An analog-to-digital converter is electrically connected to the receiver.
The application relates to a phased array TR assembly, which generates electromagnetic wave modes for interference through a waveform generator, and the waveform generator generates target wave modes by utilizing PWM and other square waves under the modulation of a plurality of transistors, so that more peak clutter can be generated after current passes through the waveform generator. In practice, the power amplifier itself is also composed of more transistors, and for this purpose, the present application provides more noise cancellation loops inside the power amplifier to reduce the generation of peak noise. Through these de-mixing circuits, the waveform generator can generate suitable voltage waveforms, which are transmitted to the power amplifier under the transmission of carrier current, the power amplifier ensures that the generated voltage waveforms can enable the array of the phased array to generate target interference waves through the horizontal contractor and the circulator, and the receiver receives reflected echoes of the interference waves and converts electromagnetic wave signals into digital quantities through the analog-to-digital converter. In the whole process, the clutter removal circuit structure effectively improves the effective transmitting power of the phased array radar and reduces the analysis difficulty of the phased array radar TR assembly after receiving and returning.
Drawings
The accompanying drawings, which are included to provide a further understanding of the application, are incorporated in and constitute a part of this specification. The drawings and their description are illustrative of the application and are not to be construed as unduly limiting the application.
Fig. 1 is a schematic structural diagram of a phased array TR assembly according to an embodiment of the present application.
Fig. 2 is a circuit diagram of a power amplifier of a phased array TR assembly according to an embodiment of the present application.
Fig. 3 is a circuit diagram of a compensating filter circuit of a phased array TR assembly according to an embodiment of the present application.
Fig. 4 is a circuit diagram of a clutter removal circuit of a phased array TR assembly according to an embodiment of the present application.
Reference numerals:
a 100-circulator; 200-horizontal contractors; a 300-power amplifier; 311-a first power supply;
312-a first resistor; 313-a first capacitance; 314-a second capacitance; 315-a first inductance;
316-a first NPN type MOS tube; 321-a first adjustable resistor; 322-a second adjustable resistor;
323-a third capacitance; 331-a second inductance; 332-fourth capacitance; 333-fifth capacitance;
334-a second resistor; 341-a second power supply; 342-a first impurity removal capacitor; 343-a second impurity removing capacitor;
344-removing impurity inductance; 345-second NPN MOS transistor; 400-clutter removal circuit;
410-RC wave-removing circuit; 411-a third impurity removing capacitor; 412-a impurity removal resistor; 421-high pass;
422-high pass capacitance; 423-a first high pass resistance; 424-a second high pass resistance;
425-third high pass resistance; 426-a third power supply; 427-fourth power supply; 500-a waveform generator;
600-receiver; 700-analog-to-digital converter; 800-compensating filter circuit; 810-a voltage follower; 820-compensating inductance; 830-compensation capacitance.
Detailed Description
The present application will be described in further detail with reference to the drawings and examples, in order to make the objects, technical solutions and advantages of the present application more apparent. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the scope of the application.
The application provides a phased array TR assembly.
As shown in fig. 1, in one embodiment of the present application, a phased array TR assembly includes circulator 100, horizontal puncturer 200, power amplifier 300, clutter removal circuit 400, waveform generator 500, receiver 600, and analog-to-digital converter 700.
The circulator 100 is used to connect a phase shifter.
The horizontal contractor 200 is electrically connected to the circulator 100.
The power amplifier 300 is electrically connected to the horizontal contractor 200.
The noise cancellation circuit 400 is electrically connected to the power amplifier 300.
The waveform generator 500 is electrically connected to the clutter removal circuit 400.
The receiver 600 is electrically connected to the circulator 100.
The analog-to-digital converter 700 is electrically connected to the receiver 600.
Specifically, the waveform generator 500 generates the electromagnetic wave pattern for interference, and the waveform generator 500 generates the target wave pattern by using a square wave such as PWM under the modulation of a plurality of transistors, so that more peak noise is generated after the current passes through the waveform generator 500, and the noise cancellation circuit 400 is disposed on the connection link between the waveform generator 500 and the power amplifier 300 to cancel the noise generated by the waveform generator 500. In practice, the power amplifier 300 is composed of more transistors, and for this reason, the present application provides more noise cancellation loops inside the power amplifier 300 to reduce the generation of peak noise.
The present embodiment relates to a phased array TR assembly. Through the de-mixing circuit, the waveform generator 500 is capable of generating suitable voltage waveforms, which are transmitted to the power amplifier 300 under the transmission of the carrier current, the power amplifier 300 ensures that the generated voltage waveforms can enable the array of phased array cells to generate the target interference wave through the horizontal contractor 200 and the circulator 100, and the receiver 600 receives the reflected echo of the interference wave and converts the electromagnetic wave signal into digital quantity through the analog-digital converter 700. In the whole process, the clutter removal circuit 400 effectively improves the effective transmitting power of the phased array radar and reduces the analysis difficulty after the receiving back of the TR component of the phased array radar.
As shown in fig. 2, in an embodiment of the present application, the power amplifier 300 includes a first power source 311, a first resistor 312, a first capacitor 313, a second capacitor 314, a first inductor 315, and a first NPN MOS transistor 316. The first end of the first capacitor 313 is electrically connected to the noise cancellation circuit 400. The second end of the first capacitor 313 and the first end of the first resistor 312 are electrically connected to the point a. The gate of the first NPN MOS transistor 316 is electrically connected to point a. The second end of the first resistor 312 and the first end of the first inductor 315 are electrically connected to the point B. The first power supply 311 is electrically connected to the point B. The first end of the second capacitor 314 is electrically connected to point B. The drain of the first NPN MOS transistor 316 is electrically connected to the second end of the first inductor 315. A second terminal of the second capacitor 314 is electrically connected to a second terminal of the first inductor 315.
Specifically, the first end of the first capacitor 313 is electrically connected to the clutter removing circuit 400, and the clutter removing circuit 400 only filters the clutter of the waveform generator 500, and does not change the overall voltage waveform of the current, so that the first capacitor 313 with the ac/dc blocking function can generate a potential signal on the polar plate at the second end, so as to realize the on-off of the gate of the first NPN MOS transistor 316, and further realize the chopping of the dc output by the first power supply 311. It should be noted that the first capacitor 313 has a filtering function, and can filter out clutter.
On the other hand, the first power supply 311 is electrically connected to the point B, the first end of the second capacitor 314 is electrically connected to the point B, the drain of the first NPN MOS transistor 316 is electrically connected to the second end of the first inductor 315, and the second end of the second capacitor 314 is electrically connected to the second end of the first inductor 315, so that the first inductor 315 and the second capacitor 314 form an LC filter circuit, and the LC filter circuit filters the first power supply 311.
The present embodiment relates to a power amplifier 300. The first capacitor 313 filters the signal input, the LC filter circuit formed by the first inductor 315 and the second capacitor 314 filters the input of the first power supply 311, so that the effective transmitting power of the phased array radar is effectively improved, and the resolution difficulty of the received and recovered phased array radar TR assembly is reduced.
As shown in fig. 2, in an embodiment of the present application, the power amplifier 300 further includes a first adjustable resistor 321, a second adjustable resistor 322, and a third capacitor 323. The first end of the first adjustable resistor 321 is electrically connected to the source of the first NPN MOS transistor 316. The second end of the first adjustable resistor 321 is grounded. The first end of the second adjustable resistor 322 is electrically connected to the point a. The first end of the second adjustable resistor 322 is grounded. The source of the first NPN MOS transistor 316 is electrically connected to the first end of the third capacitor 323. The second end of the third capacitor 323 is grounded.
The present embodiment relates to a power amplifier 300. The first end of the second adjustable resistor 322 is electrically connected to the point a, the first end of the first resistor 312 is electrically connected to the point a, the second adjustable resistor 322 and the first resistor 312 realize voltage division, and the sensitivity of the electrical signal given by the second end plate of the first capacitor 313 is ensured. The first adjustable resistor 321 and the third capacitor 323 form an RC filter circuit, so that the voltage stability of the source electrode and the drain electrode of the first NPN MOS tube 316 is ensured, the occurrence of peak clutter is reduced, the effective transmitting power of the phased array radar is effectively improved, and the analysis difficulty of the received back phased array radar TR assembly is reduced.
As shown in fig. 2, in an embodiment of the present application, the power amplifier 300 further includes a second inductor 331, a fourth capacitor 332, a fifth capacitor 333, and a second resistor 334. The first end of the fourth capacitor 332 is electrically connected to the drain of the first NPN MOS transistor 316. The second end of the fourth capacitor 332 and the first end of the second inductor 331 are electrically connected to the point C. The second end of the second inductor 331 and the first end of the second resistor 334 are electrically connected to the point D. The second end of the second inductor 331 and the first end of the fifth capacitor 333 are electrically connected to the point D. The second resistor 334 has a second end grounded. The second end of the fifth capacitor 333 is grounded.
The present embodiment relates to a power amplifier 300. In practice, the drain of the first NPN MOS transistor 316 is the output point of the signal receiving block of the power amplifier 300. After a series of filtering, the voltage waveform output by the output point is subjected to LC trap circuit formed by the fourth capacitor 332 and the second inductor 331 due to the possibility of peak clutter occurring in the transistor close to the first NPN type MOS transistor 316, so that the voltage waveform of the target frequency passes, the voltage output point is filtered by the RC filter circuit formed by the fifth capacitor 333 and the second resistor 334, the occurrence of the peak clutter is reduced, the effective transmitting power of the phased array radar is effectively improved, and the resolution difficulty of the received back phased array radar TR assembly is reduced.
As shown in fig. 2, in an embodiment of the application, the power amplifier 300 further includes a second power supply 341, a first impurity removing capacitor 342, a second impurity removing capacitor 343, an impurity removing inductor 344, and a second NPN MOS transistor 345. The gate of the second NPN MOS transistor 345 is electrically connected to point C. The drain of the second NPN MOS transistor 345 is electrically connected to the second power supply 341. The source of the second NPN MOS transistor 345 is grounded. The impurity removing inductor 344 is electrically connected to a connection link between the drain of the second NPN MOS transistor 345 and the second power supply 341. The first end of the first impurity removing capacitor 342 is electrically connected to the second power source 341. The second end of the first impurity removing capacitor 342 is grounded. The first end of the second impurity removing capacitor 343 is electrically connected to the drain of the second NPN MOS transistor 345. The second end of the second impurity removing capacitor 343 is grounded.
The present embodiment relates to a power amplifier 300. In practice, the drain of the second NPN MOS transistor 345 is the output of the power amplifier 300. The drain electrode of the second NPN MOS transistor 345 chops according to the level signal of the second inductor 331 to realize the variable flow of the voltage of the second power supply 341, and in order to prevent noise generated by the second power supply 341 and the second NPN MOS transistor 345, the impurity removing inductance 344 and the first impurity removing capacitor 342 form an LC filter circuit. The second de-mixing capacitor 343 de-spikes the output of the power amplifier 300.
As shown in fig. 3, in an embodiment of the present application, the phased array TR assembly further includes a compensation filter circuit 800. The compensation filter circuit 800 includes a voltage follower 810. The voltage follower 810 has its inverting input grounded. The positive input of the voltage follower 810 is electrically connected to the output of the voltage follower 810.
The present embodiment relates to a voltage follower 810, and the main function of the voltage follower 810 is to match the impedance of two circuit modules with forward input terminals connected to output terminals. And voltage oscillation generated by two circuit modules connected with the forward input end and the output end due to large impedance difference is prevented. Eliminating voltage oscillations can reduce spikes in voltage modes.
As shown in fig. 3, in an embodiment of the present application, the positive input terminal of the voltage follower 810 is electrically connected to the drain of the second NPN MOS transistor 345. The output of the voltage follower 810 is electrically connected to the horizontal contractor 200.
The present embodiment relates to a voltage follower 810. The positive input end of the voltage follower 810 is electrically connected to the drain electrode of the second NPN MOS transistor 345, and the output end of the voltage follower 810 is electrically connected to the horizontal contractor 200. In order to prevent voltage oscillation between the drain electrode of the second NPN MOS transistor 345 and the horizontal contractor 200 due to the large impedance difference, a voltage follower 810 is required to be introduced to eliminate the voltage oscillation, which can reduce the peak of the voltage waveform.
As shown in fig. 3, in an embodiment of the present application, the compensation filter circuit 800 further includes a compensation inductor 820 and a compensation capacitor 830. The compensation inductance 820 is electrically connected to a connection link between the positive input of the voltage follower 810 and the output of the voltage follower 810. A first terminal of the compensation capacitor 830 is electrically connected to an output terminal of the voltage follower 810. The second end of the compensation capacitor 830 is grounded.
The present embodiment relates to a compensation filter circuit 800. The compensating inductor 820 is electrically connected to the connection link between the positive input terminal of the voltage follower 810 and the output terminal of the voltage follower 810, mainly for eliminating common mode noise. The first end of the compensation capacitor 830 is electrically connected to the output end of the voltage follower 810, and the second end of the compensation capacitor 830 is grounded, so as to mainly eliminate differential mode clutter.
As shown in fig. 4, in an embodiment of the present application, the clutter removal circuit 400 includes an RC wave removal circuit 410. The RC wave-removing circuit includes a third removing capacitor 411 and a removing resistor 412. The first end of the impurity removing resistor 412 is electrically connected to the waveform generator 500. The second terminal of the impurity removing resistor 412 and the first terminal of the third impurity removing capacitor 411 are electrically connected to the point E. The second end of the third impurity removing capacitor 411 is grounded.
The present embodiment relates to an RC wave-cutting circuit 410. The impurity capacitor and the third impurity removing capacitor 411 form an RC wave removing circuit 410, clutter of the waveform generator 500 is filtered, peak clutter is reduced, effective transmitting power of the phased array radar is effectively improved, and analysis difficulty after the phased array radar TR assembly is received is reduced.
As shown in FIG. 4, in an embodiment of the present application, the clutter removal circuit 400 further comprises a high pass device 421, a high pass capacitor 422, a first high pass resistor 423, a second high pass resistor 424, a third high pass resistor 425, a third power supply 426 and a fourth power supply 427. The positive input of the high pass 421 is electrically connected to point E. The high-pass capacitor 422 is electrically connected to the connection link between the positive input of the high-pass device 421 and the point E. The first high-pass resistor 423 is electrically connected to a connection link between the point E and the output terminal of the high-pass device 421. The positive input of the high pass 421 is grounded. The inverting input of the high pass device 421 is electrically connected to the output of the high pass device 421. The second high-pass resistor 424 is electrically connected to a connection link between the inverting input of the high-pass device 421 and the output of the high-pass device 421. A first terminal of the third high-pass resistor 425 is electrically connected to the inverting input terminal of the high-pass device 421. The second end of the third high-pass resistor 425 is grounded. The forward reference voltage terminal of the high pass device 421 is electrically connected to the third power supply 426. The reverse reference voltage terminal of the high pass device 421 is electrically connected to the fourth power supply 427. The output terminal of the high pass device 421 is electrically connected to the first terminal of the first capacitor 313.
This embodiment relates to a clutter removal circuit 400. The high pass 421 is effectively an operational amplifier. The high-pass capacitor 422 is capable of allowing a high-frequency ac signal to pass through, and outputs a level signal to the first terminal of the first capacitor 313 in comparison with the high-pass device 421.
The technical features of the above embodiments may be combined arbitrarily, and the steps of the method are not limited to the execution sequence, so that all possible combinations of the technical features in the above embodiments are not described for brevity of description, however, as long as there is no contradiction between the combinations of the technical features, they should be considered as the scope of the description of the present specification.
The foregoing examples illustrate only a few embodiments of the application and are described in detail herein without thereby limiting the scope of the application. It should be noted that it will be apparent to those skilled in the art that several variations and modifications can be made without departing from the spirit of the application, which are all within the scope of the application. Accordingly, the scope of the application should be assessed as that of the appended claims.
Claims (10)
1. A phased array TR assembly, comprising:
the circulator is used for externally connecting the phase shifter;
A horizontal contractor electrically connected to the circulator;
a power amplifier electrically connected to the horizontal contractor;
the clutter removing circuit is electrically connected with the power amplifier;
the waveform generator is electrically connected with the clutter removal circuit;
A receiver electrically connected to the circulator;
An analog-to-digital converter is electrically connected to the receiver.
2. The phased array TR assembly of claim 1, wherein the power amplifier comprises a first power supply, a first resistor, a first capacitor, a second capacitor, a first inductor, and a first NPN MOS transistor;
The first end of the first capacitor is electrically connected with the clutter removal circuit;
The second end of the first capacitor and the first end of the first resistor are electrically connected to the point A;
The grid electrode of the first NPN type MOS tube is electrically connected to the point A;
the second end of the first resistor and the first end of the first inductor are electrically connected to the point B;
the first power supply is electrically connected to the point B;
The first end of the second capacitor is electrically connected to the point B;
The drain electrode of the first NPN type MOS tube is electrically connected with the second end of the first inductor;
the second end of the second capacitor is electrically connected with the second end of the first inductor.
3. The phased array TR assembly of claim 2, wherein the power amplifier further comprises a first adjustable resistor, a second adjustable resistor, a third capacitor;
The first end of the first adjustable resistor is electrically connected with the source electrode of the first NPN type MOS tube;
The second end of the first adjustable resistor is grounded;
the first end of the second adjustable resistor is electrically connected to the point A;
The first end of the second adjustable resistor is grounded;
The source electrode of the first NPN type MOS tube is electrically connected with the first end of the third capacitor;
the second end of the third capacitor is grounded.
4. The phased array TR assembly of claim 3, wherein the power amplifier further comprises a second inductance, a fourth capacitance, a fifth capacitance, and a second resistance;
the first end of the fourth capacitor is electrically connected with the drain electrode of the first NPN type MOS tube;
The second end of the fourth capacitor and the first end of the second inductor are electrically connected to the point C;
The second end of the second inductor and the first end of the second resistor are electrically connected to the point D;
the second end of the second inductor and the first end of the fifth capacitor are electrically connected to the point D;
The second end of the second resistor is grounded;
the second end of the fifth capacitor is grounded.
5. The phased array TR assembly of claim 4, wherein the power amplifier further comprises a second power supply, a first de-hybridization capacitor, a second de-hybridization capacitor, a de-hybridization inductor, and a second NPN MOS transistor;
The grid electrode of the second NPN type MOS tube is electrically connected to the point C;
The drain electrode of the second NPN type MOS tube is electrically connected with the second power supply;
The source electrode of the second NPN type MOS tube is grounded;
the impurity removing inductor is electrically connected to a connecting link between the drain electrode of the second NPN type MOS tube and the second power supply;
The first end of the first impurity removing capacitor is electrically connected with the second power supply;
The second end of the first impurity removing capacitor is grounded;
The first end of the second impurity removing capacitor is electrically connected with the drain electrode of the second NPN type MOS tube;
the second end of the second impurity removing capacitor is grounded.
6. The phased array TR assembly of claim 5, further comprising a compensation filter circuit;
The compensation filter circuit comprises a voltage follower;
The reverse input end of the voltage follower is grounded;
the positive input end of the voltage follower is electrically connected with the output end of the voltage follower.
7. The phased array TR assembly of claim 6, wherein a positive input of the voltage follower is electrically connected to a drain of the second NPN MOS transistor;
The output end of the voltage follower is electrically connected with the horizontal contractor.
8. The phased array TR assembly of claim 7, wherein the compensation filter circuit further comprises a compensation inductance and a compensation capacitance;
The compensation inductor is electrically connected to a connecting link between the positive input end of the voltage follower and the output end of the voltage follower;
The first end of the compensation capacitor is electrically connected with the output end of the voltage follower;
The second end of the compensation capacitor is grounded.
9. The phased array TR assembly of claim 8, wherein the de-clutter circuit comprises an RC de-wave circuit;
the RC wave removing circuit comprises a third impurity removing capacitor and an impurity removing resistor;
the first end of the impurity removing resistor is electrically connected with the waveform generator;
the second end of the impurity removing resistor and the first end of the third impurity removing capacitor are electrically connected to the point E;
The second end of the third impurity removing capacitor is grounded.
10. The phased array TR assembly of claim 9, wherein the de-clutter circuit further comprises a high pass device, a high pass capacitor, a first high pass resistor, a second high pass resistor, a third power supply, and a fourth power supply;
The positive input end of the high-pass device is electrically connected with the E point;
The high-pass capacitor is electrically connected to a connecting link between the positive input end of the high-pass device and the E point;
The first high-voltage resistor is electrically connected to a connecting link between the E point and the output end of the high-pass device;
The positive input end of the high pass device is grounded;
The reverse input end of the high-pass device is electrically connected with the output end of the high-pass device;
The second high-voltage resistor is electrically connected to a connection link between the reverse input end of the high-pass device and the output end of the high-pass device;
The first end of the third high-pass resistor is electrically connected with the reverse input end of the high-pass device;
the second end of the third high-pass resistor is grounded;
the positive reference voltage end of the high pass device is electrically connected with the third power supply;
The reverse reference voltage end of the high pass device is electrically connected with the fourth power supply;
The output end of the high-pass device is electrically connected with the first end of the first capacitor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202322707343.9U CN221007857U (en) | 2023-10-08 | 2023-10-08 | Phased array TR assembly |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202322707343.9U CN221007857U (en) | 2023-10-08 | 2023-10-08 | Phased array TR assembly |
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| CN221007857U true CN221007857U (en) | 2024-05-24 |
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| CN202322707343.9U Active CN221007857U (en) | 2023-10-08 | 2023-10-08 | Phased array TR assembly |
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| CN (1) | CN221007857U (en) |
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