CN220983343U - PCIe signal test fixture compatible with EDSFF interfaces and test system - Google Patents

Abstract

The utility model discloses a PCIe signal test fixture compatible with EDSFF interfaces and a test system, wherein the fixture comprises a substrate, a plurality of PCIe sending ends and a plurality of PCIe receiving ends; each PCIe transmitting end is arranged on the positive end face of the substrate; each PCIe receiving end is arranged on the opposite end face opposite to the positive end face in the substrate; each PCIe transmitting end and each PCIe receiving end respectively comprise a positive radio frequency connector and a negative radio frequency connector; the positive radio frequency connector and the negative radio frequency connector are both used for being connected with the test equipment; the edge of the substrate is provided with a splicing part in a protruding mode, wherein the splicing part is used for being connected with the EDSFF interface, and a plurality of golden fingers are arranged on the splicing part in parallel; the positive radio frequency connector and the negative radio frequency connector are respectively and electrically connected with the single gold finger. The utility model realizes the effective test of PCIe signals of EDSSF interfaces.

Description

PCIe signal test fixture compatible with EDSFF interfaces and test system

Technical Field

The utility model relates to the technical field of server signal testing, in particular to a PCIe signal testing jig compatible with EDSFF interfaces and a testing system.

Background

In order to ensure the stable operation of the server and the normal use of the interfaces and the components of the server, testing whether the signal integrity of the interfaces of the server meets the standard has become an essential important flow in the process of developing and maintaining the server. In the existing testing process, an interface signal is generally required to be connected to an oscilloscope through an SMA cable (i.e. a cable adapted to an SMA interface, which is called Sub Miniature VersionA in full), and signal integrity is verified by judging a waveform image displayed by the oscilloscope. However, signal transmission is often performed between the server hard disk interface and an external device through pins, rather than SMA cables. Therefore, signals need to be converted from pins of the interface to the SMA cable through a special test fixture to be connected with the oscilloscope.

At present, a hard disk interface commonly used on a server is U.2/U.3 hard disk interface, which can support a PCIE5.0 interface (a fifth generation high-speed serial computer expansion bus standard with a transmission rate of 32 GB/s), and a SAS3.0 interface (a third generation serial additional SCSI (Serial Attached SCSI) interface with a transmission rate of 12 GB/s), supports an NVMe (Non-Volatile Memory Express, non-volatile memory host controller interface specification) protocol, has the characteristics of high speed, low delay and low power consumption, and the theoretical transmission rate reaches 64Gbps. In 2017, EDSFF (ENTERPRISE AND DATACENTER SSD Form Factor, standard Form specification of solid state disk in enterprise and data center) interface standard technology was released. EDSFF provides a series of dynamic external dimensions for the solid state disk, and compared with the existing external dimensions of the solid state disk, the solid state disk has the advantages in the aspects of capacity, expandability, performance, maintainability, manageability, heat dissipation and power management. Today, all of the EDSFF compliant interfaces share the same protocol (NVMe), the same interface (PCIe), the same edge connector (compliant with the SFF-TA-1002 specification), the same pin arrangement and function (compliant with the SFF-TA-1009 specification).

In actual use, the EDSFF c &2c interface connector (as shown in fig. 4) is applied to the server motherboard, and the storage device e1.S or e1.L is directly connected. Since ESDFF c &2c adopts new interface technology. The conventional test fixture for U.2/U.3 interfaces cannot lead PCIe signals on the EDSFF C &2C to test equipment such as an oscilloscope, so that effective signal test cannot be performed.

Disclosure of Invention

The embodiment of the utility model provides a PCIe signal test fixture compatible with EDSFF interfaces and a test system, aiming at solving the problem that the test fixture cannot effectively test signals of EDSFF interfaces in the prior art.

In a first aspect, an embodiment of the present utility model provides a PCIe signal testing tool compatible with EDSFF interfaces, including a substrate, a plurality of PCIe sending ends, and a plurality of PCIe receiving ends; each PCIe transmitting end is arranged on the front end face of the substrate; each PCIe receiving end is arranged on the opposite end face opposite to the positive end face in the substrate; each PCIe transmitting end and each PCIe receiving end respectively comprise a positive radio frequency connector and a negative radio frequency connector; the positive radio frequency connector and the negative radio frequency connector are both used for being connected with test equipment; the edge of the substrate is provided with a splicing part in a protruding mode, wherein the splicing part is used for being connected with a EDSFF interface, and a plurality of golden fingers are arranged on the splicing part in parallel; the positive radio frequency connector and the negative radio frequency connector are respectively and electrically connected with a single gold finger.

In some embodiments, the plug comprises a first plug and a second plug; the first plug-in connection part and the second plug-in connection part are arranged in parallel, and the front end face of the first plug-in connection part is flush with the front end face of the second plug-in connection part.

In some embodiments, the front face of the plug is flush with the front face of the substrate; the reverse end face of the plug-in connection part is flush with the reverse end face of the base plate.

In some embodiments, the distance between each of the positive rf connectors and the corresponding negative rf connector is greater than or equal to 5mm.

In some embodiments, positive and negative traces are disposed within the substrate; the positive radio frequency connector is connected to the corresponding golden finger through the positive wiring; the negative radio frequency connector is connected to the corresponding golden finger through the negative wiring; the length of the positive wiring and the negative wiring corresponding to the single PCIe sending end or the single PCIe receiving end are the same.

In some embodiments, a reference clock connector is also included; the reference clock connector is arranged on the front end face of the substrate.

In some embodiments, the golden finger includes a plurality of golden finger groups, each golden finger group including a first golden finger and a second golden finger that are adjacently arranged; the first golden finger in the single golden finger group is electrically connected with the positive radio frequency connector in the single PCIe transmitting end or the single PCIe receiving end; and the second golden finger in the single golden finger group is electrically connected with the negative radio frequency connector in the single PCIe transmitting end or the single PCIe receiving end.

In some embodiments, the golden finger further comprises a grounded golden finger; the grounding golden finger is arranged between two adjacent golden finger groups.

In some embodiments, the substrate further comprises a ground; the grounding part is electrically connected with the grounding golden finger.

In a second aspect, an embodiment of the present utility model further provides a PCIe signal testing system compatible with EDSFF interfaces, including a PCIe signal testing jig compatible with EDSFF interfaces as described in the first aspect, and further including a server motherboard, a testing device, and a testing cable; a EDSFF interface is arranged on the server main board, a plug-in part on the substrate is plugged into the EDSFF interface, and a golden finger on the plug-in part is electrically connected with the EDSFF interface; one end of the test cable is connected to the test device; the other end of the test cable is connected to the positive radio frequency connector and the negative radio frequency connector in the PCIe transmitting end or connected to the positive radio frequency connector and the negative radio frequency connector in the PCIe receiving end.

Based on the structure and the connection mode thereof, the PCIe signal test fixture compatible with EDSFF interfaces provided by the embodiment of the utility model can realize effective connection with EDSSF interfaces and lead out PCIe signals of EDSSF interfaces by arranging the plug-in parts and golden fingers thereon, and then the PCIe signals are transmitted to test equipment through a positive radio frequency connector and a negative radio frequency connector in a PCIe transmitting end or a PCIe receiving end, thereby realizing effective test of PCIe signals of EDSSF interfaces.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present utility model, the drawings required for the description of the embodiments will be briefly described below, and it is obvious that the drawings in the following description are some embodiments of the present utility model, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.

Fig. 1 is a schematic block diagram of a front end face of a PCIe signal testing fixture compatible with EDSFF interfaces provided by an embodiment of the present utility model;

Fig. 2 is a schematic block diagram of an anti-end face of a PCIe signal test fixture compatible with EDSFF interfaces according to an embodiment of the present utility model;

fig. 3 is a schematic diagram illustrating connection between a PCIe signal testing fixture compatible with EDSFF interfaces and a EDSFF C connector according to an embodiment of the present utility model;

Fig. 4 is a schematic diagram of connection between a PCIe signal testing fixture compatible with EDSFF interfaces and a EDSFF C connector according to an embodiment of the present utility model;

Fig. 5 is a schematic diagram of a PCIe signal testing system compatible with EDSFF interfaces according to an embodiment of the present utility model.

Wherein, the reference numerals specifically are:

10. PCIe signal test fixture compatible with EDSFF interfaces; 100. a substrate; 110. a plug-in part; 111. a first plug-in connection; 112. a second plug-in connection; 120. a golden finger; 121. a golden finger group; 1211. a first golden finger; 1212. a second golden finger; 122. a grounding golden finger; 130. a positive wiring; 140. negative wiring; 150. a grounding part; 200. PCIe transmitting end; 300. PCIe receiving end; 400. a positive radio frequency connector; 500. a negative radio frequency connector; 600. a reference clock connector; 20. PCIe signal test system compatible with EDSFF interface; 21. a server motherboard; 211. EDSFF interfaces; 2111. pins; 22. a testing device; 23. a test cable; 30. EDSFF 1C connectors; 40. EDSFF 2C connector.

Detailed Description

The following description of the embodiments of the present utility model will be made clearly and fully with reference to the accompanying drawings, in which it is evident that the embodiments described are some, but not all embodiments of the utility model. All other embodiments, which can be made by those skilled in the art based on the embodiments of the utility model without making any inventive effort, are intended to be within the scope of the utility model.

It should be understood that the terms "comprises" and "comprising," when used in this specification and the appended claims, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.

It is also to be understood that the terminology used in the description of the utility model is for the purpose of describing particular embodiments only and is not intended to be limiting of the utility model. As used in this specification and the appended claims, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.

It should be further understood that the term "and/or" as used in the present specification and the appended claims refers to any and all possible combinations of one or more of the associated listed items, and includes such combinations.

Referring to fig. 1 to fig. 4, as shown in fig. 1 and fig. 2, an embodiment of the present utility model provides a PCIe signal testing tool 10 compatible with EDSFF interfaces, including a substrate 100, a plurality of PCIe sending ends 200, and a plurality of PCIe receiving ends 300; each PCIe transmitting end 200 is disposed on a front end surface of the substrate 100; each PCIe receiving end 300 is disposed on an opposite end surface of the substrate 100 opposite to the front end surface; each PCIe transmitting end 200 and each PCIe receiving end 300 respectively include a positive radio frequency connector 400 and a negative radio frequency connector 500; the positive radio frequency connector 400 and the negative radio frequency connector 500 are both used for connection with the test equipment 22; the edge of the substrate 100 is provided with a plug portion 110 for connecting with the EDSFF interface 211 in a protruding manner, and a plurality of golden fingers 120 are arranged on the plug portion 110 in parallel; the positive rf connector 400 and the negative rf connector 500 are electrically connected to the single gold finger 120, respectively.

In this embodiment, the substrate 100 is a main body structure of the PCIe signal testing fixture 10 compatible with EDSFF interfaces, and a Very Low Loss class PCB (Printed Circuit Board ) board is required to be adopted, and the signal Loss factor of the class board, that is, df, is between 0.003 and 0.0065, so that excessive Loss of PCIe signals can be effectively avoided. The edge of the substrate 100 is provided with a plug portion 110 in a protruding manner, and the plug portion 110 is used for firmly and effectively connecting the main structure of the PCIe signal testing fixture 10 compatible with the EDSFF interface with the EDSFF interface 211 so as to lead out the PCIe signal of the EDSFF interface 211 and test the PCIe signal. The socket 110 is integrally formed with the substrate 100, and a plurality of gold fingers 120 are disposed thereon in parallel. The golden finger 120 is composed of conductive contacts that can electrically connect with each 2111 of the EDSFF interface 211 and draw out PCIe signals of the EDSFF interface 211. The PCIe transmitting end 200 (commonly called TX end, i.e. Transmit end) can export PCIe signals of the EDSFF interface 211 led out by the golden finger 120 to the test device 22, and correspondingly, the PCIe receiving end 300 (commonly called RX end, i.e. Receive end) can Receive PCIe signals of the test device 22. PCIe transmitting end 200 and PCIe receiving end 300 are respectively disposed on a front end face and a back end face of substrate 100, so as to effectively divide, prevent access errors of test cable 23 in a signal test process, and prevent signal interference.

Transmission of PCIe signals needs to be accomplished through the positive radio frequency connector 400 and the negative radio frequency connector 500. Each PCIe transmitting end 200 and each PCIe receiving end 300 include a positive radio frequency connector 400 and a negative radio frequency connector 500, and when testing, the test cable 23 needs to be connected to the positive radio frequency connector 400 and the negative radio frequency connector 500 in the PCIe receiving end 300 at the same time, or connected to the positive radio frequency connector 400 and the negative radio frequency connector 500 in the PCIe receiving end 300 at the same time, so as to perform testing. The positive radio frequency Connector 400 and the negative radio frequency Connector 500 are embedded on the surface of the substrate 100, and the positive radio frequency Connector 400 and the negative radio frequency Connector 500 are connectors in the form of MMPX (Miniature Micro-coaxial Push-on Connector) interfaces, have excellent electrical characteristics and smaller mechanical dimensions, are manufactured by adopting brass materials, have impedance of 50Ohm, have working frequency of 67GHz, have data transmission rate of 80Gbps, and can meet the signal test requirement of PCIE 5.0. In an actual setting, the PCIe sending ends 200 located on the front end face may be arranged in parallel or in a grid-like distribution, so that PCIe sending ends 200 in each row/each column are arranged at equal intervals, and PCIe receiving ends 300 may also be arranged in the same form on the opposite end face, so as to implement ordered PCIe signal testing and prevent signal interference.

In one embodiment, as shown in fig. 2, the plug portion 110 includes a first plug portion 111 and a second plug portion 112; the first plugging portion 111 and the second plugging portion 112 are arranged in parallel, and a front end surface of the first plugging portion 111 is flush with a front end surface of the second plugging portion 112.

In the present embodiment, the plug portion 110 includes a first plug portion 111 and a second plug portion 112, and the first plug portion 111 and the second plug portion 112 are disposed in parallel. The first plug portion 111 and the second plug portion 112 are both extended structures on the substrate 100, so that, in order to ensure smooth connection with the EDSFF interface 211, the front end faces of the first plug portion 111 and the second plug portion 112 are flush with each other, and the opposite end faces are also flush with each other. In the actual testing process, as shown in fig. 3, for the EDSFF C connector 30, only the first plug portion 111 is required to be inserted into the EDSFF interface 211 on the EDSFF C connector 30; for EDSFF C connector 40, as shown in fig. 4, first plug portion 111 and second plug portion 112 need to be inserted into two EDSFF interfaces 211 on EDSFF C connector 30 respectively (two EDSFF interfaces 211 on EDSFF C connector 30 are different in size, and the sizes of first plug portion 111 and second plug portion 112 need to be set correspondingly).

In one embodiment, as shown in fig. 3, the front end surface of the plugging portion 110 is flush with the front end surface of the substrate 100; the opposite end face of the plug-in portion 110 is flush with the opposite end face of the substrate 100.

In the present embodiment, the front end face and the back end face of the plugging portion 110 are respectively flush with the front end face and the back end face of the substrate 100, and further, the plugging portion 110 and the substrate 100 maintain good integrity and can be smoothly inserted into the EDSFF interface 211.

In an embodiment, the distance between each of the positive rf connectors 400 and the corresponding negative rf connector 500 is greater than or equal to 5mm.

In this embodiment, for a single PCIe transmitting end 200 or a single PCIe receiving end 300, a distance range between one positive radio frequency connector 400 and a corresponding negative radio frequency connector 500 included therein is set to be greater than or equal to 5mm, and a certain distance is maintained, so as to ensure that signal interference is not generated between test cables 23 connected to each of the positive radio frequency connector 400 and the corresponding negative radio frequency connector 500.

In one embodiment, as shown in fig. 1, the substrate 100 is provided with a positive trace 130 and a negative trace 140; the positive radio frequency connector 400 is connected to the corresponding golden finger 120 through the positive trace 130; the negative radio frequency connector 500 is connected to the corresponding golden finger 120 through the negative trace 140; the positive trace 130 and the negative trace 140 corresponding to the single PCIe transmit end 200 or the single PCIe receive end 300 have the same length. It is to be understood that only the positive trace 130 and the negative trace 140 corresponding to two PCIe senders 200 are shown in fig. 1.

In this embodiment, the positive trace 130 may transmit PCIe signals between the positive rf connector 400 and the gold finger 120, and the negative trace 140 may transmit PCIe signals between the negative rf connector 500 and the gold finger 120. The positive trace 130 and the negative trace 140 are transmission structures integrated inside the substrate 100, and by setting the positive trace 130 and the negative trace 140 to be the same length, the integrity and the simultaneity of signal transmission can be ensured, and the occurrence of signal delay and the like can be prevented.

In one embodiment, as shown in FIG. 1, reference clock connector 600 is also included; the reference clock connector 600 is disposed on the front surface of the substrate 100.

In this embodiment, the reference clock connector 600 is capable of providing a reference clock signal to the test equipment 22 to synchronize the transmission of PCIe signal data. Meanwhile, the reference clock connector 600 is arranged on the front end face of the substrate 100, so that distinction between the front end face and the back end face can be provided for a tester in the testing process, and the situation of misconnection is prevented.

In an embodiment, as shown in fig. 1, the golden finger 120 includes a plurality of golden finger groups 121, and each golden finger group 121 includes a first golden finger 1211 and a second golden finger 1212 that are adjacently arranged; the first gold finger 1211 in the single gold finger group 121 is electrically connected to the positive radio frequency connector 400 in the single PCIe transmitting end 200 or the single PCIe receiving end 300; the second gold finger 1212 in the single gold finger set 121 is electrically connected to the negative rf connector 500 in the single PCIe transmit end 200 or the single PCIe receive end 300.

In this embodiment, the golden finger 120 may be divided into a plurality of golden finger groups 121, and each golden finger group 121 includes one first golden finger 1211 and one second golden finger 1212 that are adjacently arranged. Each golden finger group 121 corresponds to a single PCIe transmit end 200 or a single PCIe receive end 300, respectively. The first gold finger 1211 of the single gold finger set 121 is connected to the single positive rf connector 400, the second gold finger 1212 is connected to the single negative rf connector 500, and the positive rf connector 400 and the negative rf connector 500 belong to the same PCIe transmitting end 200 or PCIe receiving end 300. Furthermore, each PCIe transmitting end 200 or PCIe receiving end 300 may perform reliable signal transmission.

In one embodiment, as shown in fig. 1, the golden finger 120 further includes a grounded golden finger 122; the grounding gold finger 122 is disposed between two adjacent gold finger groups 121.

In the present embodiment, the grounding golden finger 122 is used for grounding the PCIe signal testing jig 10 compatible with EDSFF interfaces, so as to ensure reliable operation of the testing process. The grounding golden finger 122 is disposed between two adjacent golden finger groups 121, so as to separate the adjacent golden finger groups 121, further prevent signal interference between each PCIe sending end 200 or each PCIe receiving end 300, improve anti-interference capability during PCIe signal transmission, and improve test quality.

In one embodiment, as shown in fig. 2, the substrate 100 further includes a grounding portion 150; the grounding portion 150 is electrically connected to the grounding gold finger 122.

In the present embodiment, the ground portion 150 may be provided in the form of a ground layer and provided at one of the end surfaces of the substrate 100. The grounding part 150 is electrically connected with the grounding golden finger 122, so that the overall grounding consistency of the PCIe signal test fixture 10 compatible with EDSFF interfaces can be ensured, and stable and reliable signal transmission can be realized.

Referring to fig. 5, as shown in fig. 5, the embodiment of the present utility model further provides a PCIe signal testing system 20 compatible with EDSFF interfaces, including the PCIe signal testing jig 10 compatible with EDSFF interfaces as described above, further including a server motherboard 21, a testing device 22, and a testing cable 23; a EDSFF interface 211 is arranged on the server main board 21, a plug-in part 110 on the substrate 100 is plugged into the EDSFF interface 211, and a golden finger 120 on the plug-in part 110 is electrically connected with the EDSFF interface 211; one end of the test cable 23 is connected to the test device 22; the other end of the test cable 23 is connected to the positive radio frequency connector 400 and the negative radio frequency connector 500 in the PCIe transmitting end 200, or to the positive radio frequency connector 400 and the negative radio frequency connector 500 in the PCIe receiving end 300.

In the present embodiment, EDSFF interfaces 211 are provided on a connector, which may be EDSFF C connector 30 or EDSFF C connector 40, and edsff 1C connector 30 or EDSFF C connector 40 is fixed on the server motherboard 21. EDSFF of the interfaces 211 are provided with a plurality of 2111, and each golden finger 120 is electrically connected with a single 2111 after the plugging portion 110 is plugged into the EDSFF of the interfaces 211. The golden finger 120 connected with the positive radio frequency connector 400 and the negative radio frequency connector 500 can transmit PCIe signals. In a particular test procedure, a section of test cable 23 may be first connected to a test device 22, such as an oscilloscope. The other end of the test cable 23 is then connected to the desired PCIe transmit end 200 or PCIe receive end 300, and the single test cable 23 is connected to a single positive radio frequency connector 400 or negative radio frequency connector 500. Then, the plugging portion 110 is plugged into the EDSFF interface 211, so that transmission and test of PCIe signals can be performed. Wherein the test cable 23 also employs MPXX cable corresponding to the positive radio frequency connector 400 and the negative radio frequency connector 500 in the form of MPXX interface connectors.

Based on the structure and the connection mode thereof, the PCIe signal testing jig compatible with EDSFF interfaces provided by the embodiment of the utility model can realize effective connection with EDSSF interfaces and lead out PCIe signals of EDSSF interfaces by arranging the plug-in parts and golden fingers thereon, and then the PCIe signals are transmitted to testing equipment through a positive radio frequency connector and a negative radio frequency connector in a PCIe transmitting end or a PCIe receiving end, thereby realizing effective testing of PCIe signals of EDSSF interfaces.

The present utility model is not limited to the above embodiments, and various equivalent modifications and substitutions can be easily made by those skilled in the art within the technical scope of the present utility model, and these modifications and substitutions are intended to be included in the scope of the present utility model. Therefore, the protection scope of the utility model is subject to the protection scope of the claims.

Claims (10)

1. The PCIe signal test fixture compatible with EDSFF interfaces is characterized by comprising a substrate, a plurality of PCIe sending ends and a plurality of PCIe receiving ends; each PCIe transmitting end is arranged on the front end face of the substrate; each PCIe receiving end is arranged on the opposite end face opposite to the positive end face in the substrate; each PCIe transmitting end and each PCIe receiving end respectively comprise a positive radio frequency connector and a negative radio frequency connector; the positive radio frequency connector and the negative radio frequency connector are both used for being connected with test equipment;

The edge of the substrate is provided with a splicing part in a protruding mode, wherein the splicing part is used for being connected with a EDSFF interface, and a plurality of golden fingers are arranged on the splicing part in parallel; the positive radio frequency connector and the negative radio frequency connector are respectively and electrically connected with a single gold finger.

2. The EDSFF interface compatible PCIe signal test fixture according to claim 1, wherein the socket includes a first socket and a second socket; the first plug-in connection part and the second plug-in connection part are arranged in parallel, and the front end face of the first plug-in connection part is flush with the front end face of the second plug-in connection part.

3. The PCIe signal testing jig compatible with EDSFF interfaces according to claim 1, wherein a front end face of the plugging portion is flush with a front end face of the substrate; the reverse end face of the plug-in connection part is flush with the reverse end face of the base plate.

4. The PCIe signal test fixture compatible with EDSFF interfaces of claim 1 wherein a distance range between each of the positive radio frequency connectors and the corresponding negative radio frequency connector is greater than or equal to 5mm.

5. The PCIe signal test fixture compatible with EDSFF interfaces as defined in claim 1 wherein positive wires and negative wires are provided in the substrate; the positive radio frequency connector is connected to the corresponding golden finger through the positive wiring; the negative radio frequency connector is connected to the corresponding golden finger through the negative wiring; the length of the positive wiring and the negative wiring corresponding to the single PCIe sending end or the single PCIe receiving end are the same.

6. The EDSFF interface compatible PCIe signal test fixture of claim 1 further comprising a reference clock connector; the reference clock connector is arranged on the front end face of the substrate.

7. The PCIe signal test fixture compatible with EDSFF interfaces according to claim 1, wherein the golden finger includes a plurality of golden finger groups, each golden finger group includes a first golden finger and a second golden finger that are adjacently arranged; the first golden finger in the single golden finger group is electrically connected with the positive radio frequency connector in the single PCIe transmitting end or the single PCIe receiving end; and the second golden finger in the single golden finger group is electrically connected with the negative radio frequency connector in the single PCIe transmitting end or the single PCIe receiving end.

8. The EDSFF-interface-compatible PCIe signal test fixture according to claim 7, wherein the golden finger further comprises a grounded golden finger; the grounding golden finger is arranged between two adjacent golden finger groups.

9. The EDSFF interface compatible PCIe signal test fixture of claim 8, wherein the substrate further comprises a ground portion; the grounding part is electrically connected with the grounding golden finger.

10. A PCIe signal testing system compatible with EDSFF interfaces, comprising the PCIe signal testing jig compatible with EDSFF interface according to any one of claims 1 to 9, further comprising a server motherboard, a testing device, and a testing cable; a EDSFF interface is arranged on the server main board, a plug-in part on the substrate is plugged into the EDSFF interface, and a golden finger on the plug-in part is electrically connected with the EDSFF interface; one end of the test cable is connected to the test device; the other end of the test cable is connected to the positive radio frequency connector and the negative radio frequency connector in the PCIe transmitting end or connected to the positive radio frequency connector and the negative radio frequency connector in the PCIe receiving end.