CN2209425Y

CN2209425Y - Dimmer

Info

Publication number: CN2209425Y
Application number: CN 94212512
Authority: CN
Inventors: 石和平
Original assignee: Individual
Current assignee: Individual
Priority date: 1994-05-26
Filing date: 1994-05-26
Publication date: 1995-10-04
Anticipated expiration: 2004-05-26

Abstract

The utility model relates to a dimmer, which is composed of an input circuit, a rectifier, a full control electronic switch, a variable duty ratio pulse generator, a step-down circuit, a delay circuit, and a protective circuit. The utility model is characterized in that the output end of the variable duty ratio pulse generator is connected with the control end of the full control electronic switch to control the on-off of the variable duty ratio pulse generator to load current, so the light of one or a plurality of fluorescent lamps, or incandescent lamps, or the combination of fluorescent lamps and incandescent lamps can be continuously regulated within a large range.

Description

Dimmer

The utility model relates to a kind of especially glow discharge spot lamp electronic installation of fluorescent light brightness for example of electric light source of regulating.

Before the utility model, the existing half control electronic switching device silicon controlled dimmer that uses, but when controllable silicon is applied to adjusting brightness of fluorescent lamp, need independently filament transformer, between fluorescent lamp and dimmer, there are many to be connected electric wire, and at thyristor operating angle hour, the 100Hz stroboscopic is serious and extinguish, and not seeing yet so far has utility goods to emerge.

The purpose of this utility model provides a kind of dimmer, and it can carry out large-scale light modulation to one or the fluorescent lamp of sending away with electric ballast more, also can be to the combined light source light modulation of incandescent lamp or fluorescent lamp and incandescent lamp.

The purpose of this utility model is achieved in that by rectifier, controls electronic switch entirely, and the variable duty ratio pulse generator is formed dimmer.The output of variable duty ratio pulse generator is connected with the control end of full control electronic switch; Two power ends of full control electronic switch and the output that is connected in parallel on the direct current of rectifier after load is connected, the input of rectifier is connected with mains supply, with the switch of the full control of variable duty ratio pulse generator control electronic switch to load current, not having in the load makes voltage drop to the following filter circuit of fluorescent lamp extinction voltage.

Owing to adopted such scheme, the utility model can be continuously adjustable to the load output duty cycle, the DC pulse that voltage amplitude is consistent with the rectifier output voltage, make fluorescent lamp operation more than extinction voltage, solved employing silicon controlled dimmer when hanging down the angle of flow, therefore the problem that causes fluorescent lamp to extinguish because of voltage peak is low can carry out light modulation on a large scale to fluorescent lamp.Because the pulse of the exportable upper frequency of variable duty ratio pulse generator, so fluorescent lamp can not glimmer during light modulation.Simultaneously, between dimmer and load wiring simple, be convenient to install.

Below in conjunction with drawings and Examples scheme of the present utility model is further described.

Fig. 1 is a block diagram of the present utility model

Fig. 2 is the electrical schematic diagram of variable duty ratio pulse generator among embodiment of the utility model

Fig. 3 is the electrical schematic diagram of variable duty ratio pulse generator among another embodiment of the utility model

Fig. 4 is the electrical schematic diagram of variable duty ratio pulse generator among another embodiment of the utility model

Fig. 5 is the complete electrical schematic diagram of an embodiment of the utility model

1 input circuit among the figure, 2 rectifiers, 3 full control electronic switches, 4 variable duty ratio pulse generators, 5 reduction voltage circuits, 6 delay circuits, 7 protective circuits.

In Fig. 1, the input of input circuit (1) is connected with external power, and output is connected with the input of rectifier (2).A dc output end of rectifier (2) is connected with an end of load, and a power end controlling electronic switch (3) entirely is connected with the other end of load, and another power end is connected with another dc output end of rectifier (2).Rectifier (2) but two output parallel filters.The output of variable duty ratio pulse generator (4) is connected with the control end of full control electronic switch (3).Full control electronic switch is meant at control end and adds control signal of telecommunication may command its electronic device that electric current is opened and closed such as bipolar transistor, field effect transistor, IGBT pipe or smart power switch IPM integrated circuit.Control end is meant base stage or grid, and the power end is meant collector electrode or drain electrode and emitter or source electrode.Reduction voltage circuit (5) is connected in parallel on two dc output ends of rectifier (2), and its output is connected with the ground end with the power input of variable duty ratio pulse generator (4) and delay circuit (6).The output of delay circuit (6) is connected with the control end of variable duty ratio pulse generator (4).The function of delay circuit be make variable duty ratio pulse generator (4) in one period short time after turning on light output duty cycle reach maximum pulse, to satisfy the requirement that some has the electric ballast of preheat function.Inductive load produces when turn-offing spike that protective circuit (7) is used to absorb full control electronic switch.

Fig. 2 is a variable duty ratio pulse generator (4) among the embodiment, by resistance R ₁, and R ₂, potentiometer W ₁Capacitor C ₁, diode D ₁And D ₂, not gate A, B and C form.The output of not gate B and capacitor C ₁An end connect capacitor C ₁The other end and potentiometer W ₁Sliding end pass through R after connecting ₂Or directly the input of NAND gate A connects diode D ₁And D ₂Behind the series aiding connection with potentiometer W ₁Two stiff ends, resistance R ₁Series connection forms loop, diode D ₁And D ₂Tie point and the output of NAND gate A, the input of not gate B and C links together.The variable pulse of the exportable duty ratio of output of this tie point NOR gate C.W ₁Be used to regulate duty ratio.Not gate C rises and isolates and driving action, and nonessential.Also can be with several not circuit parallel connections to increase driving force.R among Fig. 2 ₁And R ₂And it is nonessential.Diode D ₁And D ₂Reversal connection simultaneously.Circuit in the present embodiment is suitable for driving VMOS field effect transistor or IGBT pipe.

Fig. 3 is the variable duty ratio pulse generator (4) among another embodiment, by time-base integrated circuit D, resistance R ₃, R ₄And R ₅, capacitor C ₂And C ₃, diode D ₃And D ₄Form.Power supply vdd terminal and resistance R ₃, potentiometer W ₂Two stiff ends, resistance R ₄, diode D ₃Negative electrode, anode, C ₂End in sequential series with receiving.The D end and the potentiometer W of time-base integrated circuit ₂Sliding end, diode D ₄Anode connect TH end and diode D ₄Negative electrode, D ₃Anode, C ₂An end connect, the TR end can be connected on D ₃Anode, also can be connected on D ₃Negative electrode, the R end is connected with power vd D with vdd terminal, VS end is connected with ground, CO holds through C ₃Hold, OUT holds through resistance R with being connected to ₅The output duty cycle variable pulse.Resistance R among Fig. 3 ₄And R ₅, capacitor C ₃And it is nonessential.Diode D ₃And D ₄Reversal connection simultaneously, the R end of time-base integrated circuit can not be connected with vdd terminal and be connected with delay circuit as control end.When the R end was electronegative potential, output OUT was an electronegative potential, so should for example use transistor T at OUT termination one inverter ₁, resistance R ₆Be connected into inverter by current-limiting resistance R ₇Output variable duty ratio pulse signal.Also available integrated circuit inverter or utilize prior art that the another time-base integrated circuit is connected into the Shi Mite circuit and make inverter.

Fig. 4 is the electrical schematic diagram of variable duty ratio pulse generator (4) among the another embodiment.By time-base integrated circuit E, resistance R ₈, R ₉, R ₁₀, potentiometer W ₃, capacitor C ₄And C ₅, diode D ₅And D ₆Form.The R end of time-base integrated circuit E and vdd terminal and power vd D, resistance R ₈An end connect D end and resistance R ₈The other end, diode D ₅Anode, D ₆Negative electrode connect TR and TH end and potentiometer W ₃Sliding end, capacitor C ₄An end connect VS and capacitor C ₄The other end, C ₅An end hold with being connected to, C0 end is connected to capacitor C ₅The other end.Diode D ₅Negative electrode and potentiometer W ₃One fixedly connected, diode D ₆Anode pass through resistance R ₉With potentiometer W ₃Another stiff end connect.The OUT end of time-base integrated circuit passes through resistance R ₁₀Or directly export the variable duty ratio pulse.Resistance R among Fig. 4 ₉And R ₁₀, capacitor C ₅And nonessential, diode D ₅And D ₆Reversal connection simultaneously.The R end of time-base integrated circuit can not be connected with vdd terminal and be connected with delay circuit as control end.Should for example use transistor T this moment in the output termination one inverter output variable duty ratio pulse of time-base integrated circuit ₂, resistance R ₁₁Be connected into inverter, by current-limiting resistance R ₁₂Output variable duty ratio pulse, also available integrated circuit inverter or utilize prior art that the another time-base integrated circuit is connected into the Shi Mite circuits for triggering and make inverter.Time-base integrated circuit D in Fig. 3 and Fig. 4 circuit and E can be with 555 or 7555, or the integrated circuit of 1/2556 or 7556 models, and in addition, variable duty ratio pulse generator (4) also can utilize prior art to adopt two groups of monostable circuits to form.This circuit is suitable for driving bipolar transistor, also can be used for the driving of VMOS pipe or IGBT pipe.

Fig. 5 is the complete circuit of an embodiment of the utility model.K switch, fuse FU, inductance L and capacitor C ₆Form input circuit, K switch, fuse FU is connected on both ends of power after inductance L and the series connection of rectifier filter ac input end and forms loop, capacitor C ₆Be connected in parallel on the two ends of external power.Fuse FU wherein, inductance L and capacitor C ₆And it is nonessential.Diode D ₈-D11 forms bridge rectifier, also can form half-wave rectifying circuit, capacitor C with a diode ₇Be connected in parallel on the dc output end of bridge rectifier, strobe.Two inputs of NAND gate F and G are connected together respectively and become not circuit, constitute the oscillating part of variable duty ratio pulse generator.NAND gate H and I form the control and the drive part of variable duty ratio pulse generator (4).Each input of NAND gate H and I links together as signal input part, is connected with the output of NAND gate F.Other two of NAND gate H and I terminates at the control end that becomes variable duty ratio pulse generator (4) together, R ₁₇And C ₉Series connection becomes delay circuit (6), C ₉With R ₁₇Link be the output of delay circuit (6), be connected with the control end of variable duty ratio pulse generator.Diode D ₁₄Work the effect of releasing, its anode and capacitor C ₉Anode connect, negative electrode is connected with the output of step-down road (5) or the positive output end of rectifier (2).Diode D ₁₄And it is nonessential.The action principle of delay circuit is, when rigidly connecting logical K switch, and capacitor C ₉Be electronegative potential, make the output output high potential of NAND gate H and I, VMOS field effect transistor standard-sized sheet is logical, through after a while, and C ₉Voltage rise to the turning-on voltage of NAND gate H and I, the output output variable duty ratio pulse of NAND gate H and I is with the needs of the electric ballast that satisfies some needs warm-up time.Delay circuit (6) is also nonessential.The control end of variable duty ratio pulse generator (4) should connect high potential or be connected with two inputs in addition of NAND gate H and I when no delay circuit (6).Resistance R ₁₈, voltage-stabiliser tube D ₁₅, capacitor C ₁₀Form reduction voltage circuit (5), resistance R ₁₈One end is connected with the positive output end of rectifier filter, the other end and voltage-stabiliser tube D ₁₅Negative electrode connect, be connected with the vdd terminal of variable duty ratio pulse generator as the output of reduction voltage circuit, the anode of voltage-stabiliser tube is connected with the negative output terminal of rectifier filter, as holding altogether.Capacitor C ₁₀Be connected in parallel on voltage-stabiliser tube D ₁₅Two ends.Capacitor C wherein ₁₀With voltage-stabiliser tube D ₁₅And nonessential, voltage-stabiliser tube D ₁₅An also available resistance replaces.Diode D ₁₆Be connected in parallel on load two ends, anode is connected with the positive output end of rectifier filter (2), as protective circuit (7).Diode D ₁₆Also available electric capacity or piezo-resistance or bi-directional voltage stabilizing semiconductor device replace.LED ₁, LED ₂, LED ₃And LED ₄, connect the back as indicator light with resistance, LED ₁The indicator light of forming is connected on before the mains switch, in order to indicate the position of dimmer, LED in the dark ₂The indicator cock state, LED ₃And LED ₄The complementary size that shows duty ratio.Indicator light can replace with the neon lamp.Indicator light is also nonessential.

Claims

1. dimmer, by rectifier, full control electronic switch, the variable duty ratio pulse generator is formed, it is characterized in that: the output of variable duty ratio pulse generator is connected with the control end of full control electronic switch, the two power ends of controlling electronic switch entirely and the dc output end that is connected in parallel on rectifier after load is connected.

2. dimmer according to claim 1 is characterized in that: can increase by a filter, filter is connected in parallel on two outputs of rectifier.

3. dimmer according to claim 1 is characterized in that: can increase by a delay circuit, the output of delay circuit is connected with the control end of variable duty ratio pulse generator.

4. dimmer according to claim 1 is characterized in that: the variable duty ratio pulse generator is by resistance R ₁And R ₂, potentiometer W ₁, capacitor C ₁, diode D ₁And D ₂, not gate A, B and C form, the output of not gate B and capacitor C ₁An end connect capacitor C ₁The other end and potentiometer W ₁Sliding end pass through resistance R after connecting ₂Or directly the input of NAND gate A connects diode D ₁And D ₂Behind the series aiding connection with potentiometer W ₁Two stiff ends, resistance R ₁Series connection forms loop, diode D ₁And D ₂Link and the output of NAND gate A, the input of not gate B and C links together.

5. dimmer according to claim 1 is characterized in that: the variable duty ratio pulse generator is by time-base integrated circuit D, resistance R ₃And R ₄, capacitor C ₂And C ₃, diode D ₃And D ₄Form, the power supply vdd terminal is through resistance R ₃, potentiometer W ₂Two stiff ends, diode D ₃Negative electrode, anode, C ₂End in sequential series with receiving, the D end and the potentiometer W of time-base integrated circuit ₂Sliding end, diode D ₄Anode connect TH end and diode D ₄Negative electrode, D ₃Anode, C ₂An end connect, the R end is connected with vdd terminal, OUT holds as output.

6. dimmer according to claim 1 is characterized in that: the variable duty ratio pulse generator is by time-base integrated circuit E, resistance R ₈And R ₉, potentiometer W ₃, capacitor C ₄And C ₅, diode D ₅And D ₆Form R ₈An end be connected the D of the other end and time-base integrated circuit end, diode D with the power supply vdd terminal ₅Anode, D ₆Negative electrode connect the TR of time-base integrated circuit and TH end and potentiometer W ₃Sliding end, capacitor C ₄An end connect capacitor C ₄The other end be connected with ground.Diode D ₅Negative electrode and potentiometer W ₃Stiff end connect diode D ₆Anode pass through resistance R ₉With potentiometer W ₃Another stiff end connect, the R end of time-base integrated circuit is connected with VDD, OUT holds as the variable duty ratio pulse output end.

7. according to claim 5 or 6 described variable duty ratio pulse generators, it is characterized in that: the R end of time-base integrated circuit is as control end, the OUT end passes through resistance or directly is connected with inverter, and the output of inverter is as the output of variable duty ratio pulse generator.

8. dimmer according to claim 1, it is characterized in that: the NAND gate F of variable duty ratio pulse generator is connected respectively separately with G two outputs, input of each of NAND gate H and I interconnects the back and is connected with the output of NAND gate F, and two inputs interconnect the control end of back as the variable duty ratio pulse generator in addition.

9. dimmer according to claim 1, it is characterized in that: reduction voltage circuit is by resistance R ₁₈, capacitor C ₁₀With voltage stabilizing didoe D ₁₅Form resistance R ₁₈An end be connected with the positive output end of rectifier, the other end is connected with the vdd terminal of variable duty ratio pulse generator.

10. dimmer according to claim 1, it is characterized in that: delay circuit is by resistance R ₁₇, diode D ₁₄, capacitor C ₉Form resistance R ₁₇An end be connected the other end and capacitor C with the vdd terminal of reduction voltage circuit ₉Connect the back as output, capacitor C ₉The other end be connected with the negative output terminal of rectifier.

11. dimmer according to claim 1 is characterized in that: protective circuit is a diode, and diode is connected in parallel on the load two ends, and its cathode terminal is connected with the positive output end of rectifier.