CN220934890U

CN220934890U - Power supply circuit

Info

Publication number: CN220934890U
Application number: CN202322598658.4U
Authority: CN
Inventors: 徐建华; 陈文韬; 王洪强; 戴中江
Original assignee: Chongqing Luobulinka Technology Co ltd
Current assignee: Chongqing Luobulinka Technology Co ltd
Priority date: 2023-09-25
Filing date: 2023-09-25
Publication date: 2024-05-10
Anticipated expiration: 2033-09-25

Abstract

The utility model relates to a power supply circuit, which comprises a power supply chip U1, a power supply module, a host computer JP and an auxiliary detection load module, wherein the power supply chip U1 comprises a power supply input end BAT and a first boost current output end OUT, the power supply module comprises a current output end, and the auxiliary detection load module comprises a detection input end and a detection output end; the current output end is connected with the detection input end and the power supply input end BAT respectively, the power supply input end BAT is connected with the first boost circuit output end OUT, the first boost current output end OUT is connected with the host computer JP, the detection input end is connected with the detection output end, and the detection output end is connected with the first boost current output end OUT. The problem that the power supply circuit cannot charge two or more electronic devices to be charged at the load end is solved.

Description

Power supply circuit

Technical Field

The utility model relates to the field of power supply circuits, in particular to a power supply circuit.

Background

With the current widespread use of electronic devices, the charging requirements of the electronic devices are also increasing, so that the charging devices are used more frequently.

The power supply circuit of the conventional charging device is generally only connected with one electronic device to be charged at the charging load end, and charges the electronic device to be charged with the output voltage, where the voltage at two ends of the electronic device to be charged is the load voltage that can be detected by the power supply circuit.

However, when two or more electronic devices to be charged are connected to the load end of the power supply circuit, the output voltage in the power supply circuit is divided by each electronic device to be charged, so that the charging voltage at two ends of each electronic device to be charged is smaller than the minimum value of the load voltage which can be detected by the power supply circuit, and the power supply chip U1 cannot normally detect the load condition, so that two or more electronic devices to be charged at the load end cannot be charged.

Disclosure of utility model

The utility model aims to provide a power supply circuit.

The technical scheme for solving the technical problems is as follows: the power supply chip U1, power supply module, host computer JP and supplementary detection load module, power supply chip U1 includes power supply input BAT and first boost current output OUT, and power supply module includes the current output, and supplementary detection load module includes detection input and detection output.

The current output end is connected with the detection input end and the power supply input end BAT respectively, the power supply input end BAT is connected with the first boost circuit output end OUT, the first boost current output end OUT is connected with the host computer JP, the detection input end is connected with the detection output end, and the detection output end is connected with the first boost current output end OUT.

The beneficial effects of the utility model are as follows: the power supply chip U1 is utilized to detect the voltage difference between two ends of the auxiliary detection load module by connecting the auxiliary detection load module in parallel with the power supply input end BAT and the first boost current output end OUT of the power supply chip U1. When the voltage of the main engine JP connected with the first boost current output end OUT exceeds one, each main engine JP divides the voltage output by the first boost current output end OUT, the divided voltage of each main engine JP is smaller than the minimum value of the load voltage which can be detected by the U1 chip, and meanwhile the voltage difference of two ends of the auxiliary detection load module 4 which is detected by the power supply chip U1 is larger than a threshold value, so that the power supply chip U1 boosts the voltage of the first boost current output end OUT, the boosted voltage can supply power for the main engine JP to be charged which is connected with the first boost current output end OUT, and therefore charging of two or more main engines JP of the load end is achieved. Meanwhile, the current output end can provide more current for the host computer JP to be charged through the auxiliary detection load module, so that the charging efficiency of the host computer JP to be charged can be improved.

On the basis of the technical scheme, the utility model can be improved as follows.

Further, the auxiliary detection load module further comprises a first resistor R5 and a first diode D1; the two ends of the first resistor R5 are respectively connected with the detection output end and the negative electrode of the first diode D1, and the positive electrode of the first diode D1 is connected with the detection input end.

The beneficial effect of adopting above-mentioned further scheme is that, first diode D1 has unidirectional conductivity, utilizes this first diode D1, can be when first boost current output OUT output current, this electric current can not flow to first resistance R5 and first diode D1 through the detection output, but can only flow to first diode D1 and first resistance R5 through the detection input to can avoid this first resistance R5 and first diode D1 to damage because of the short circuit.

Further, the power supply circuit further comprises an external power supply module, and the external power supply module comprises a first power supply introduction end VIN. The power supply chip U1 further includes a second power supply lead-in terminal VIN, where the second power supply lead-in terminal VIN is connected to the first power supply lead-in terminal VIN.

The beneficial effect of adopting above-mentioned further scheme is, first power introduction end VIN can be with electric current input power supply chip U1 through second power introduction end VIN, then power supply chip U1 charges for power supply module with this electric current through power supply input end BAT. After the power supply module charges and consumes electricity for the host computer JP, the electricity can be timely supplemented.

Further, the power supply chip U1 further comprises an LED lamp control end, and the LED lamp control end is connected with an LED lamp module.

The LED lamp module has the beneficial effects that the power supply chip U1 can display the residual electric quantity of the power supply module through the LED lamp module, so that a user can know the residual electric quantity of the power supply module more intuitively according to the display condition of the LED lamp module.

Further, the LED lamp control end comprises a first control end and a second control end, the LED lamp module comprises a first LED lamp, a second LED lamp, a third LED lamp, a fourth LED lamp, a triode Q1, a third resistor R2, a second power supply and a first power supply, and the triode Q1 comprises an emitter, a base and a collector;

The first control end is respectively connected with one end of the first LED lamp and one end of the second LED lamp, the second control end is respectively connected with one end of the third LED lamp and one end of the fourth LED lamp, and the other end of the second LED lamp and the other end of the fourth LED lamp are grounded; the other end of the first LED lamp and the other end of the third LED lamp are connected with the emitter of the triode Q1, the base of the triode Q1 is connected with one end of the third resistor R2, the collector of the triode Q1 is connected with the first power supply, and the other end of the third resistor R2 is connected with the second power supply.

The beneficial effect of adopting above-mentioned further scheme is, through the bright condition that goes out of first LED lamp, second LED lamp, third LED lamp and fourth LED lamp, the user can more audio-visual understanding power module's residual capacity.

Further, the power supply module further comprises a first grounding end, the power supply chip U1 further comprises an inductance driving end SW and a second grounding end GND, and a first inductance L1 is further arranged between the inductance driving end SW and the current output end. One end of a second capacitor C3 is further connected between the current output end and the power supply input end BAT, and the other end of the second capacitor C3, the first grounding end and the second grounding end are grounded.

The beneficial effect of adopting above-mentioned further scheme is, second inductance L2 sets up between inductance drive end SW and current output, can form the current-limiting protection to power module's current output. The output voltage of the power supply module can be stabilized by connecting the second capacitor C3 in parallel with the first grounding end and the current output end of the power supply module so as to form output overvoltage protection for the power supply module.

Further, a third capacitor C2 is connected in parallel to both ends of the host JP.

The beneficial effect of adopting above-mentioned further scheme is, the parallelly connected third electric capacity C2 in both ends of host computer JP can stabilize the input voltage when this host computer JP charges to form input overvoltage protection to this host computer JP.

Further, the host JP includes a charge state judgment module and a battery to be charged; the charging state judging module comprises a charging chip U3 and a main chip U4, wherein the charging chip U3 comprises a first power input end VCC, a charging state indicating end CHRG, a charging completion indicating end STDBY and a second boost current output end LX which are connected, and the main chip U4 comprises a second power input end DC_IN;

The first boost current output terminal OUT is connected to the first power input terminal VCC, the second power input terminal dc_in is connected to the charge state indication terminal CHRG and the charge completion indication terminal STDBY, respectively, and the second boost current output terminal LX is connected to the battery to be charged.

The beneficial effect of adopting above-mentioned further scheme is, power module is through the first boost current output OUT of power supply chip U1 and the first power input VCC of chip U3 that charges with electric current input treat host computer JP, treat to charge host computer JP and charge. At this time, the charging state indication terminal CHRG and the charging completion indication terminal STDBY of the charging chip U3 have voltages. The main chip U4 detects the signal conditions of the charge state indication terminal CHRG and the charge completion indication terminal STDBY through the second power input terminal dc_in, so that the voltage condition of the second boost current output terminal LX can be accurately known, and the charge state of the battery to be charged can be accurately determined.

Further, a second inductor L2 is further provided between the second boost current output terminal LX and the battery to be charged.

The beneficial effect of adopting above-mentioned further scheme is, through establishing ties second inductance L2 between second boost current output LX and waiting to charge the battery, can be when waiting to charge the battery, carry to waiting to charge the battery after the unstable electric current of boost output of second boost current output LX through second inductance L2 stationary flow to the battery to be charged to can wait to charge the battery and form the current-limiting protection.

Drawings

FIG. 1 is a schematic diagram of a power supply circuit according to the present utility model;

FIG. 2 is a schematic diagram of a power supply circuit according to the present utility model;

FIG. 3 is a schematic diagram of a charging interface circuit connected to the first boost current output OUT;

FIG. 4 is a schematic diagram of a circuit for detecting a state of charge of a host;

Fig. 5 is a schematic diagram of a conventional circuit for detecting a state of charge of a host.

In the drawings, the list of components represented by the various numbers is as follows:

1-supply chip U1, 11-supply input BAT, 12-first boost current output OUT, 2-supply module, 21-current output, 3-host JP, 4-auxiliary detection load module, 41-detection input, 42-detection output.

Detailed Description

The principles and features of the present utility model are described below with reference to the drawings, the examples are illustrated for the purpose of illustrating the utility model and are not to be construed as limiting the scope of the utility model.

As shown in fig. 1, a power supply circuit according to an embodiment of the present utility model includes a power supply chip U1, a power supply module 2, a host JP, and an auxiliary detection load module 4, where the power supply chip U1 includes a power supply input terminal BAT and a first boost current output terminal OUT, the power supply module 2 includes a current output terminal 21, and the auxiliary detection load module 4 includes a detection input terminal 41 and a detection output terminal 42. The current output terminal 21 is connected to the detection input terminal 41 and the power supply input terminal BAT, respectively, the power supply input terminal BAT is connected to the first boost circuit output terminal OUT, the first boost current output terminal OUT is connected to the host JP, the detection input terminal 41 is connected to the detection output terminal 42, and the detection output terminal 42 is connected to the first boost current output terminal OUT. The power supply chip U1 is of the model FM9969.

In some embodiments, the number of hosts JP is greater than or equal to 2. By connecting the auxiliary detection load module 4 in parallel with the power supply input terminal BAT and the first boost current output terminal OUT of the power supply chip U1, the voltage difference across the auxiliary detection load module 4 is detected by the power supply chip U1. When more than one host computer JP connected with the first boost current output end OUT is used, each host computer JP divides the voltage output by the first boost current output end OUT, the divided voltage of each host computer JP is smaller than the minimum value of the load voltage detected by the U1 chip, and meanwhile the voltage difference of two ends of the auxiliary detection load module 4 detected by the power supply chip U1 is larger than a threshold value, so that the power supply chip U1 boosts the voltage of the first boost current output end OUT, and the boosted voltage can supply power for the host computer JP to be charged connected with the first boost current output end OUT. For example, the voltage boosted by the first boost current output terminal OUT can respectively provide a charging voltage of 5V for each host to be charged, so as to charge two or more hosts JP of the load terminal. Meanwhile, the current output terminal 21 can provide more current for the host JP to be charged through the auxiliary detection load module 4, so that the charging efficiency of the host JP to be charged can be improved.

Optionally, as shown in fig. 2, the auxiliary detection load module 4 further includes a first resistor R5 and a first diode D1. The two ends of the first resistor R5 are respectively connected with the detection output end 42 and the negative electrode of the first diode D1, and the positive electrode of the first diode D1 is connected with the detection input end 41. The first diode D1 is IN4148. The model of the first resistor R5 is 1206-2KΩ+ -1%.

In some embodiments, the first diode D1 has unidirectional conductivity. Since the detection output end 42 of the auxiliary detection load module 4 is connected with the first boost current output end OUT, the detection input end 41 of the auxiliary detection load module 4 is connected with the current output end 21, if the first diode D1 is not connected in the auxiliary detection load module 4, the first boost current output end OUT and the current output end 21 both output currents to the first resistor R5, so that the auxiliary detection load module 4 is short-circuited, and the auxiliary detection load module 4 cannot work normally, so that the power supply chip U1 cannot detect and charge two or more hosts JP of the load end. By connecting the positive electrode of the first diode D1 with the detection input terminal 41, the negative electrode of the first diode D1 is connected with the detection output terminal 42 through the first resistor R5, so that the current output by the first boost current output terminal OUT does not flow to the first resistor R5 and the first diode D1 through the detection output terminal 42, and only the current output by the current output terminal 21 flows to the first diode D1 and the first resistor R5 through the detection input terminal 41, thereby preventing the first resistor R5 and the first diode D1 from being damaged due to short circuit.

Optionally, as shown in fig. 2, the power supply circuit further includes an external power module, where the external power module includes a first power supply lead-in terminal VIN. The power supply chip U1 further includes a second power supply lead-in terminal VIN, where the second power supply lead-in terminal VIN is connected to the first power supply lead-in terminal VIN.

In some embodiments, the first power supply lead-in terminal VIN can input a current to the power supply chip U1 through the second power supply lead-in terminal VIN, and then the power supply chip U1 charges the power supply module 2 through the power supply input terminal BAT. So that the power supply module 2 can timely supplement the electric quantity after consuming the electric quantity for the host computer JP.

Optionally, as shown in fig. 2, the first power supply lead-in terminal VIN is connected to one end of the first capacitor C1 and one end of the first zener diode DZ1, and the other end of the first capacitor C1 and the other end of the first zener diode DZ1 are grounded. The model number of the first bidirectional zener diode DZ1 is BSD5C051VB. The first capacitor C1 and the first bidirectional zener diode DZ1 are connected to the second power supply lead-in terminal VIM, so that the current and the voltage input by the first power supply lead-in terminal VIN are more stable, and the power supply module 2 can be charged more stably.

Optionally, as shown in fig. 2, the power supply chip U1 further includes an LED lamp control end, and the LED lamp control end is connected with an LED lamp module.

In some embodiments, the power supply chip U1 can control the LED lamp module according to the power condition of the power supply module 2, so that the remaining power condition of the power supply module 2 can be displayed by the LED lamp module, and thus a user can more intuitively know the remaining power of the power supply module 2.

Optionally, as shown in fig. 2, the LED lamp control end includes a first control end and a second control end, and the LED lamp module includes a first LED lamp, a second LED lamp, a third LED lamp, a fourth LED lamp, a triode Q1, a third resistor R2, a second power supply, and a first power supply, where the triode Q1 includes an emitter, a base, and a collector. The first control end is respectively connected with one end of the first LED lamp and one end of the second LED lamp, the second control end is respectively connected with one end of the third LED lamp and one end of the fourth LED lamp, and the other end of the second LED lamp and the other end of the fourth LED lamp are grounded; the other end of the first LED lamp and the other end of the third LED lamp are connected with the emitter of the triode Q1, the base of the triode Q1 is connected with one end of the third resistor R2, the collector of the triode Q1 is connected with the first power supply, and the other end of the third resistor R2 is connected with the second power supply. The model of the third resistor R2 is 0303-1K (1020) - +/-5%. The input voltage of the second power supply is 5V. Wherein, LED 10603-white light is a first LED lamp, LED 20603-white light is a second LED lamp, LED 3003-white light is a third LED lamp, and LED 40603-white light is a fourth LED lamp.

In some embodiments, the user can more intuitively understand the remaining power of the power supply module 2 through the on-off condition of the first LED lamp, the second LED lamp, the third LED lamp, and the fourth LED lamp. The on-off condition includes blinking, normally on, normally off. For example, when the first power supply lead-in terminal VIN charges the power supply module 2 through the power supply chip U1, the first LED lamp flashes, and the second LED lamp, the third LED lamp and the fourth LED lamp are all turned off, so that the residual power of the power supply module 2 is 0-25%. The first LED lamp is normally on, the second LED lamp flashes, the third LED lamp and the fourth LED lamp are all normally off, and the residual capacity of the power supply module 2 is 25% -50%. The first LED lamp and the second LED lamp are all normally on, the third LED lamp flashes, the fourth LED lamp is normally off, and the residual capacity of the power supply module 2 is 50% -75%. The first LED lamp, the second LED lamp and the third LED lamp are all normally on, and the fourth LED lamp flashes, so that the residual capacity of the power supply module 2 is 50% -75%. The first LED lamp, the second LED lamp, the third LED lamp and the fourth LED lamp are all normally on, and the residual power of the power supply module 2 is 100%.

In other embodiments, when the power supply module 2 charges the host JP to be charged at the load end through the power supply chip U1, the first LED lamp flashes, and the second LED lamp, the third LED lamp and the fourth LED lamp are all normally off, so that the residual power of the power supply module 2 is 0-3%. The first LED lamp is normally on, the second LED lamp, the third LED lamp and the fourth LED lamp are all normally off, and the residual capacity of the power supply module 2 is 3% -25%. The first LED lamp and the second LED lamp are all normally on, the third LED lamp and the fourth LED lamp are all normally off, and the residual capacity of the power supply module 2 is 25% -50%. The first LED lamp, the second LED lamp and the third LED lamp are all normally on, the fourth LED lamp is normally off, and the residual capacity of the power supply module 2 is 50% -75%. The first LED lamp, the second LED lamp, the third LED lamp and the fourth LED lamp are all normally on, and the residual power of the power supply module 2 is 75% -100%.

Optionally, as shown in fig. 2, the power supply module 2 further includes a first ground terminal, the power supply chip U1 further includes an inductor driving terminal SW and a second ground terminal GND, and a first inductor L1 is further disposed between the inductor driving terminal SW and the current output terminal 21. One end of a second capacitor C3 is further connected between the current output terminal 21 and the power supply input terminal BAT, and the other end of the second capacitor C3, the first ground terminal and the second ground terminal are grounded. The model number of the first inductor L1 is CSMNR, 4030-220M, and the inductance value is 22UH. The capacitance value of the second capacitor C3 is 10uF.

In some embodiments, the second inductor L2 is disposed between the inductor driving end SW and the current output end 21, and can form a current limiting protection for the current output end 21 of the power supply module 2. By connecting the second capacitor C3 in parallel to the first ground terminal and the current output terminal 21 of the power supply module 2, the output voltage of the power supply module can be stabilized to form an output overvoltage protection for the power supply module.

Optionally, as shown in fig. 2, the power supply chip U1 further includes a test terminal TAP.

Alternatively, as shown in fig. 2, a third capacitor C2 is connected in parallel to both ends of the host JP. Wherein, the capacitance value of the third capacitor C2 is 10uF.

In some embodiments, the third capacitor C2 is connected in parallel to two ends of the host JP, so as to stabilize the input voltage of the host JP when the host JP is charged, so as to form an input overvoltage protection for the host JP.

Alternatively, as shown in fig. 2, a fourth capacitor C4 is connected in parallel to both ends of the host JP. The capacitance value of the fourth capacitor C2 is 47uF.

The working principle of the power supply circuit of the conventional charging equipment is as follows: the external power supply is connected with the second power supply lead-in end VIN of the power supply chip U1 through the first power supply lead-in end VIN, so that power is supplied to the second power supply lead-in end VIN. The power supply input BAT of the power supply chip U1 charges a battery in the power supply module. When the battery in the power supply module is full of electricity, the power supply chip U1 stops charging the battery in the power supply module, and meanwhile, the first LED lamp, the second LED lamp, the third LED lamp and the fourth LED lamp in the LED lamp module are in a normally-on state. When the first boost current output terminal OUT of the power supply chip U1 detects that the plurality of charging interfaces of the load terminal have one host JP to be charged, the first boost current output terminal OUT of the power supply chip U1 boosts the voltage to 5V to charge the host JP to be charged. After detecting that the charging current is reduced to a preset value, the power supply chip U1 stops charging. But after the electric quantity of the host computer to be charged JP is full, the host computer to be charged JP is not disconnected with the charging interface, and after the host computer to be charged JP is connected with other charging interfaces, the output voltage of the first boost current output end OUT of the power supply chip U1 is divided by the two host computers to be charged JP, so that the charging voltages of the two ends of the two electronic devices to be charged are smaller than the minimum value of the load voltage which can be detected by the power supply circuit, the load condition cannot be detected normally by the charging voltages, and therefore the two or more electronic devices to be charged of the load ends cannot be charged.

The power supply circuit shown in fig. 2 has the following working principle: when the external power supply is connected with the second power supply lead-in terminal VIN of the power supply chip U1 through the first power supply lead-in terminal VIN, power is supplied to the second power supply lead-in terminal VIN. The power supply input BAT of the power supply chip U1 charges a battery in the power supply module. The detection input end of the auxiliary detection load module is connected with the current output end of the power supply module, and the detection output end of the auxiliary detection load module is connected with the first boost current output end OUT. By connecting the auxiliary detection load module 4 in parallel with the power supply input terminal BAT and the first boost current output terminal OUT of the power supply chip U1, the voltage difference between two ends of the auxiliary detection load module 4 is detected by using the power supply chip U1

Since the first boost current output terminal OUT is connected to more than one host computer JP, the smaller the input voltage of each host computer JP is, and the input voltage of each host computer JP cannot be detected by the U1 chip, the larger the voltage difference across the auxiliary detection load module 4 is. Therefore, when more than one host JP is connected to the first boost current output terminal OUT, the power supply chip U1 boosts the voltage of the first boost current output terminal OUT, so that the boosted voltage can supply power to the host to be charged JP connected to the first boost current output terminal OUT. For example, the voltage boosted by the first boost current output terminal OUT can respectively provide a charging voltage of 5V for each host to be charged, so as to charge two or more hosts JP of the load terminal. Meanwhile, the current output terminal 21 can provide more current for the host JP to be charged through the auxiliary detection load module 4, so that the charging efficiency of the host JP to be charged can be improved.

Optionally, the first boost current output OUT is connected to the host JP through a charging interface. When charging, with host computer JP with interface connection that charges, when ending the charging, with host computer JP with interface disconnection that charges, just can remove host computer JP alone for host computer JP's use and charge more convenient.

The circuit of the charging interface is shown in fig. 3, and the circuit of the charging interface includes TYPEC PIN, sixth resistor R3 and seventh resistor R4, TYPEC PIN including two first GND ends, two first VBUS ends, a first CC1 end and a first CC2 end, two first VBUS ends are all grounded, and two first VBUS ends are all connected with the first boost current output end OUT. One end of the sixth resistor R3 is connected with the first CC1 end, and the other end of the sixth resistor R3 is grounded. One end of the seventh resistor R4 is connected with the first CC2 end, and the other end of the seventh resistor R4 is grounded. Wherein, the model of the sixth resistor R3 and the seventh resistor R4 are 0603-5.1 K+/-1 percent.

Optionally, as shown in fig. 4, the host JP includes a charge state judgment module and a battery to be charged; the charging state judging module comprises a charging chip U3 and a main chip U4, the charging chip U3 comprises a first power input end VCC, a charging state indicating end CHRG, a charging completion indicating end STDBY and a second boost current output end LX, and the main chip U4 comprises a second power input end DC_IN. The first boost current output end OUT is connected with the first power input end VCC, the second power input end DC_IN is respectively connected with the charge state indication end CHRG and the charge completion indication module end, and the second boost current output end LX is connected with the battery to be charged. The model of the charging chip U3 is TP5400, and the charging chip U3 further comprises a first Vout end, a BAT end, a second GND end, a PROG end and a PAD end. The second GND terminal and the PAD terminal are grounded.

IN some embodiments, as shown IN fig. 5, a common working principle of detecting the charging state of the battery to be charged is that two serially connected fourth resistors are generally connected IN parallel between the first power input terminal VCC and the first ground terminal of the charging chip U3, one end of a fifth resistor is connected between the two fourth resistors, and the other end of the fifth resistor is connected with the second power input terminal dc_in of the main chip U4. Wherein the model of the third resistor and the fourth resistor is 0402-750K (7503) +/-1 percent. The model number of the fifth resistor is 0402-1K (102) - +/-5%. IN this way, the main chip U4 can detect the voltage of the second power input terminal dc_in, and can determine whether a current enters the charging chip U3 according to the voltage of the second power input terminal dc_in, so as to determine whether the battery to be charged is IN a charging state. However, when the voltage detected by the main chip U4 is any value of 0.9V or more and 2V or less, the state of charge cannot be determined (whether the voltage in this range is a high or low determination dead zone). The working principle of detecting the charging state of the battery to be charged as shown IN fig. 4 is that the first boost current output end OUT is connected with the first power input end VCC, the 5V voltage is input into the host JP, and the second power input end dc_in is respectively connected with the charging state indication end CHRG and the charging completion indication module end, so that the power supply module 2 inputs the current into the host to be charged JP through the first boost current output end OUT of the power supply chip U1 and the first power input end VCC of the charging chip U3, and charges the host to be charged JP. At this time, the charging state indication terminal CHRG and the charging completion indication terminal STDBY of the charging chip U3 have voltages. The main chip U4 detects the signal conditions of the charge state indicating end CHRG and the charge completion indicating end STDBY of the charging chip U3 through the second power input end DC_IN, so that whether current enters the charging chip U3 can be accurately known, and the charge state of the battery to be charged can be accurately determined.

In some embodiments, the relationship between the state of charge indication terminal CHRG, the signal condition of the charge completion indication terminal STDBY and the state of charge of the host JP of the charging chip U3 is shown in table 1. When the charging state indication terminal CHRG is red, and the charging completion indication terminal STDBY is green, the charging state of the host JP is in the charging state. When the charging state indication terminal CHRG is turned off in red and the charging completion indication terminal STDBY is turned on in green, the charging state of the host JP is a full battery state. When the charging state indication terminal CHRG is red, and the charging completion indication terminal STDBY is green, the charging state of the host JP is a no-battery state. When the charging state indication terminal CHRG is turned off in red and the charging completion indication terminal STDBY is turned off in green, the charging state of the host JP is a boosting operation state.

TABLE 1

Optionally, a second inductor L2 is further disposed between the second boost current output end LX and the battery to be charged. The model of the second inductor L2 is CSMNR, 4030-220M, and the inductance is 22 UH+/-20%.

In some embodiments, by connecting the second inductor L2 in series between the second boost current output end LX and the battery to be charged, the unstable current boosted and output by the second boost current output end LX can be delivered to the battery to be charged after being stabilized by the second inductor L2 during charging of the battery to be charged, so that current limiting protection can be formed for the battery to be charged.

In some embodiments, as shown in fig. 4 and 5, the host JP further includes a chip U5, an eighth resistor R14, a ninth resistor R9, a fifth capacitor C10, a sixth capacitor C11, a second diac DZ3, a second diode D2, a tenth resistor R37, an eleventh resistor R30, a third diode D3, a seventh capacitor C16, an eighth capacitor C15, a third diac D6, a ninth capacitor C14, a tenth capacitor C8, a chip U2, and an eleventh capacitor C9. The chip U5 comprises four SHELL ends, two third GND ends, two second VBUS ends, an SBU2 end, a DN2 end, a DP2 end, a second CC2 end, an SBU1 end, a DN1 end, a DP1 end and a second CC1 end. The chip U2 includes a first power-in terminal VIN, a second Vout terminal, and a fourth GND terminal. The first boost current output terminal OUT is respectively connected with one end of the second bidirectional zener diode DZ3, one end of the fifth capacitor, one end of the sixth capacitor, two second VBUS ends, the anode of the second diode D2, the first power input terminal VCC, and the other end of the second bidirectional zener diode DZ3, the other end of the fifth capacitor, the other end of the sixth capacitor, four SHELL ends and two third GND ends are all grounded. The second CC2 end is connected to one end of the ninth resistor R9, and the other end of the ninth resistor R9 is grounded. The second CC1 end is connected to one end of the eighth resistor R14, and the other end of the eighth resistor R14 is grounded. The negative pole of the second diode D2 is connected with one end of an eleventh resistor R30, the other end of the eleventh resistor R30 is connected with the first Vout end of the charging chip U3, one end of a third diode D3, one end of a third bidirectional voltage stabilizing diode D6, one end of a ninth capacitor C14, one end of a tenth capacitor C8 and a first power supply leading-in end VIN, and the other end of the third bidirectional voltage stabilizing diode D6, the other end of the ninth capacitor C14 and the other end of the tenth capacitor C8 are grounded. The PROG end of the charging chip U3 is connected to one end of the tenth resistor R37, and the other end of the tenth resistor R37 is grounded. The BAT end of the charging chip U3 is connected with one end of a seventh capacitor C16, one end of an eighth capacitor C15 and the battery to be charged, and the other end of the seventh capacitor C16 and the other end of the eighth capacitor C15 are grounded. The fourth GND terminal is grounded, the second Vout terminal is connected to one terminal of the eleventh capacitor C9, and the other terminal of the eleventh capacitor C9 is grounded.

The model of the chip U5 is TYPEC PIN, and the model of the chip U3 is LR8103A-T30. The model of the eighth resistor R14 and the model of the ninth resistor R9 are 0402-5.1K, and the model of the tenth resistor R37 is 0402-6.8 K+/-1%. The model of the fifth capacitor C10 is 0805-10uF (106)/25 V+ -20%, the model of the sixth capacitor C11 is 0402-104/25 V+ -20%, the models of the seventh capacitor C16, the eighth capacitor C15 and the ninth capacitor C14 are 0805-22uF (226)/16 V+ -20%, and the models of the tenth capacitor C8 and the eleventh capacitor C9 are 0603-1uF (105)/25 V+ -10%. The model numbers of the second bidirectional zener diode DZ3 and the third bidirectional zener diode D6 are BSD5C051VB. The model of the third diode D3 is SS14SOD-123.

Those skilled in the art will appreciate that the present utility model may be implemented as a system, method, or computer program product. Accordingly, the present disclosure may be embodied in the following forms, namely: may be entirely hardware, entirely software (including firmware, resident software, micro-code, etc.), or may be in the form of a combination of hardware and software generally referred to herein as a "circuit," module "or" system. Furthermore, in some embodiments, the utility model may also be embodied in the form of a computer program product in one or more computer-readable media, which contain computer-readable program code. The computer readable storage medium can be, for example, but not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or a combination of any of the foregoing.

In the description of the present specification, a description referring to terms "one embodiment," "some embodiments," "examples," "specific examples," or "some examples," etc., means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the present utility model. In this specification, schematic representations of the above terms are not necessarily directed to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples. Furthermore, the different embodiments or examples described in this specification and the features of the different embodiments or examples may be combined and combined by those skilled in the art without contradiction.

While embodiments of the present utility model have been shown and described above, it will be understood that the above embodiments are illustrative and not to be construed as limiting the utility model, and that variations, modifications, alternatives and variations may be made to the above embodiments by one of ordinary skill in the art within the scope of the utility model.

Claims

1. A power supply circuit, comprising:

The power supply chip U1 (1), a power supply module (2), a host computer JP (3) and an auxiliary detection load module (4), wherein the power supply chip U1 (1) comprises a power supply input end BAT (11) and a first boost current output end OUT (12), the power supply module (2) comprises a current output end (21), and the auxiliary detection load module (4) comprises a detection input end (41) and a detection output end (42);

The current output end (21) is respectively connected with the detection input end (41) and the power supply input end BAT (11), the power supply input end BAT is connected with the first boost circuit output end OUT, the first boost current output end OUT (12) is connected with the host computer JP (3), the detection input end (41) is connected with the detection output end (42), and the detection output end (42) is connected with the first boost current output end OUT (12).

2. The power supply circuit according to claim 1, characterized in that the auxiliary detection load module (4) further comprises a first resistor R5 and a first diode D1; the two ends of the first resistor R5 are respectively connected with the detection output end (42) and the cathode of the first diode D1, and the anode of the first diode D1 is connected with the detection input end (41).

3. The power supply circuit of claim 1, further comprising an external power module, the external power module comprising a first power supply lead-in VIN;

the power supply chip U1 (1) further includes a second power supply introduction terminal VIN, where the second power supply introduction terminal VIN is connected to the first power supply introduction terminal VIN.

4. The power supply circuit according to claim 3, wherein the first power supply lead-in terminal VIN is connected to one end of the first capacitor C1 and one end of the first zener diode DZ1, respectively, and the other end of the first capacitor C1 and the other end of the first zener diode DZ1 are grounded.

5. The power supply circuit according to claim 1, wherein the power supply chip U1 (1) further comprises an LED lamp control terminal, and the LED lamp control terminal is connected with an LED lamp module.

6. The power supply circuit of claim 5, wherein the LED lamp control terminal comprises a first control terminal and a second control terminal, the LED lamp module comprises a first LED lamp, a second LED lamp, a third LED lamp, a fourth LED lamp, a triode Q1, a third resistor R2, a first power supply, and a second power supply, the triode Q1 comprises an emitter, a base, and a collector;

The first control end is respectively connected with one end of a first LED lamp and one end of a second LED lamp, the second control end is respectively connected with one end of a third LED lamp and one end of a fourth LED lamp, and the other end of the first LED lamp and the other end of the third LED lamp are grounded; the other end of the second LED lamp and the other end of the fourth LED lamp are connected with the emitter of the triode Q1, the base electrode of the triode Q1 is connected with one end of the third resistor R2, the collector electrode of the triode Q1 is connected with a first power supply, and the other end of the third resistor R2 is connected with a second power supply.

7. The power supply circuit according to claim 1, wherein the power supply module (2) further comprises a first ground terminal, the power supply chip U1 (1) further comprises an inductor driving terminal SW and a second ground terminal GND, and a first inductor L1 is further arranged between the inductor driving terminal SW and the current output terminal (21); one end of a second capacitor C3 is further connected between the current output end (21) and the power supply input end BAT (11), and the other end of the second capacitor C3, the first grounding end and the second grounding end are grounded.

8. The power supply circuit according to claim 1, wherein a third capacitor C2 is connected in parallel across the host JP.

9. The power supply circuit according to any one of claims 1 to 8, wherein the host JP includes a state of charge determination module and a battery to be charged; the charging state judging module comprises a charging chip U3 and a main chip U4, the charging chip U3 comprises a first power input end VCC, a charging state indicating end CHRG, a charging completion indicating end STDBY and a second boost current output end LX, and the main chip U4 comprises a second power input end DC_IN;

The first boost current output end OUT (12) is connected with the first power input end VCC, the second power input end DC_IN is respectively connected with the charge state indication end CHRG and the charge completion indication end STDBY, and the second boost current output end LX is connected with the battery to be charged.

10. The power supply circuit according to claim 9, characterized in that a second inductance L2 is further provided between the second boost current output terminal LX and the battery to be charged.