CN220934053U - 使用集成电路封装的装置 - Google Patents
使用集成电路封装的装置 Download PDFInfo
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- CN220934053U CN220934053U CN202322390406.2U CN202322390406U CN220934053U CN 220934053 U CN220934053 U CN 220934053U CN 202322390406 U CN202322390406 U CN 202322390406U CN 220934053 U CN220934053 U CN 220934053U
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Classifications
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- H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L25/0652—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next and on each other, i.e. mixed assemblies
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Abstract
本实用新型的实施例提供一种使用集成电路封装的装置包括:集成电路封装,所述集成电路封装包括封装组件及贴合至封装组件的封装加强件;贴合至集成电路封装的散热片,所述散热片的主要部分设置于封装加强件上方,所述散热片的突出部分延伸穿过封装加强件;位于散热片的主要部分与封装加强件之间的弹性粘合材料;以及位于散热片的突出部分与封装组件之间的热界面材料,所述热界面材料与弹性粘合材料不同。
Description
技术领域
本实用新型的实施例涉及一种使用集成电路封装的装置,且特别是涉及一种利用弹性粘合材料连接散热片和封装加强件的使用集成电路封装的装置。
背景技术
由于各种电子组件(例如晶体管、二极管、电阻器、电容器等)的集成密度持续提高,半导体行业已经历快速发展。在很大程度上,集成密度提高起因于最小特征大小(minimum feature size)的不断减小,此使得更多组件能够被整合至给定面积中。随着缩小电子装置需求的增长,已浮现出对更小且更具创造性的半导体管芯封装技术的需求。
实用新型内容
本实用新型的实施例提供一种使用集成电路封装的装置包括集成电路封装、贴合至所述集成电路封装的散热片、弹性粘合材料及热界面材料。集成电路封装包括封装组件及贴合至所述封装组件的封装加强件。散热片的主要部分设置于所述封装加强件上方,所述散热片的突出部分延伸穿过所述封装加强件。弹性粘合材料位于所述散热片的所述主要部分与所述封装加强件之间,热界面材料位于所述散热片的所述突出部分与所述封装组件之间,所述热界面材料与所述弹性粘合材料不同。
本实用新型的实施例提供一种使用集成电路封装的装置包括封装衬底、贴合至所述封装衬底的封装组件、位于所述封装组件上的第一弹性阻隔件、位于所述第一弹性阻隔件上的加强环以及延伸穿过所述加强环及所述第一弹性阻隔件的开口。封装组件包括逻辑设备及内存装置,第一弹性阻隔件与所述内存装置交叠,加强环与所述内存装置交叠,开口在俯视图中设置于所述逻辑设备上方。
基于上述,集成电路封装包括耦合至集成电路封装的封装组件的加强件。加强件有助于减少集成电路封装的翘曲。加强件中的开口在俯视图中设置于封装组件的逻辑设备上方,所述开口使得能够在加强件不处于散热片与逻辑设备之间的热路径中的情况下藉由将散热片耦合至逻辑设备来在装置中实施集成电路封装。因此,可改善集成电路封装的封装组件的散热。
为让本实用新型的实施例的上述特征和优点能更明显易懂,下文特举实施例,并配合附图作详细说明如下。
附图说明
图1是集成电路管芯的剖视图。
图2A至图2B是管芯堆叠的剖视图。
图3至图14是根据一些实施例的制造集成电路封装的中间阶段的视图。
图15是根据一些实施例的实施集成电路封装的装置的剖视图。
图16是根据一些实施例的实施集成电路封装的装置的剖视图。
图17是根据一些实施例的实施集成电路封装的装置的剖视图。
图18是根据一些实施例的实施集成电路封装的装置的剖视图。
图19是根据一些实施例的实施集成电路封装的装置的剖视图。
图20是根据一些实施例的实施集成电路封装的装置的剖视图。
附图标记说明
50:集成电路管芯;50A:第一集成电路管芯;50B:第二集成电路管芯;50F:前侧;52:半导体衬底;54、114:内连线结构;56:管芯连接件;58:介电层;60A、60B:管芯堆叠;62、116:导通孔;100:封装组件;110:晶片;110A:封装区;112:衬底;120A:逻辑设备;120B:内存装置;122、136:导电连接件;124、216:底部填充胶;126、272:包封体;128:载体衬底;132:绝缘层;134:凸块下金属(UBM);140:中介层;200:集成电路封装;200R:区;210:封装衬底;212:衬底芯;214:结合接垫;218:无源装置;220:保护层;230:封装加强件;230A:上部部分;230B:下部部分;232:开口;234、266:粘合剂;236:下部阻隔件;238、306:空隙;240:上部阻隔件;262:虚设金属化体;264:环;268:凹槽;302:散热片;302M:主要部分;302P:突出部分;304:热界面材料;308:芯吸层。
具体实施方式
以下揭露内容提供诸多不同的实施例或实例,用于实施本揭露的不同特征。下文阐述构件及排列的具体实例以简化本揭露。当然,这些仅为范例,其目的不在于限制本揭露范围。举例而言,在以下说明中第一特征形成于第二特征“之上”或形成于第二特征“上”,可包括第一特征与第二特征被形成为直接接触的实施例,亦可包括第一特征与第二特征之间形成有额外特征使得所述第一特征与所述第二特征不直接接触的实施例。另外,本揭露可在各个范例中重复使用组件编号及/或字母。这样的重复是为了简化及清晰描述本揭露,而非用以限定各种实施例及/或配置之间的关系。
此外,为了方便说明,本文中可能使用例如“位于…之下”、“位于…下方”、“下部的”、“位于…上方”、“上部的”等空间相对性用语来描述图中所示的一个组件或特征与另一(其他)组件或特征的关系。除了图中所绘示的定向之外,所述空间相对性用语亦涵盖装置在使用或操作中的不同定向。设备可以具有其他定向(旋转90度或处于其他定向),其所使用的空间相对性描述语亦可用同样的方式解读。
根据各种实施例,集成电路封装包括耦合至集成电路封装的封装组件的加强件。封装组件包括内存装置及逻辑设备。加强件有助于减少集成电路封装的翘曲。加强件中的开口在俯视图中设置于封装组件的逻辑设备上方。所述开口使得能够在加强件不处于散热片与逻辑设备之间的热路径中的情况下藉由将散热片耦合至逻辑设备来在装置中实施集成电路封装。因此,可改善集成电路封装的封装组件的散热。
图1是集成电路管芯50的剖视图。在后续处理中将对多个集成电路管芯50进行封装以形成集成电路封装。每一集成电路管芯50可为逻辑管芯(例如中央处理单元(centralprocessing unit,CPU)、图形处理单元(graphics processing unit,GPU)、系统芯片(system-on-a-chip,SoC)管芯、微控制器等)、内存管芯(例如动态随机存取内存(dynamicrandom access memory,DRAM)管芯、静态随机存取内存(static random access memory,SRAM)管芯等)、电源管理管芯(例如电源管理集成电路(power management integratedcircuit,PMIC)管芯)、射频(radio frequency,RF)管芯、接口管芯、传感器管芯、微机电系统(micro-electro-mechanical-system,MEMS)管芯、信号处理管芯(例如数字信号处理(digital signal processing,DSP)管芯)、前端管芯(例如模拟前端(analog front-end,AFE)管芯)、类似管芯或其组合。集成电路管芯50可形成于晶片中,所述晶片可包括在后续步骤中被单体化以形成多个集成电路管芯50的不同管芯区。集成电路管芯50包括半导体衬底52、内连线结构54、管芯连接件56及介电层58。
半导体衬底52可为经掺杂或未经掺杂的硅衬底或绝缘体上半导体(semiconductor-on-insulator,SOI)衬底的有源层。半导体衬底52可包含其他半导体材料,例如:锗;化合物半导体,包括碳化硅、砷化镓、磷化镓、磷化铟、砷化铟及/或锑化铟;合金半导体,包括硅锗、砷磷化镓、砷化铝铟、砷化铝镓、砷化镓铟、磷化镓铟及/或砷磷化镓铟;或其组合。亦可使用其他衬底,例如多层式衬底或梯度衬底。半导体衬底52具有有源表面(例如图1中面朝上的表面)及非有源表面(例如图1中面朝下的表面)。在半导体衬底52的有源表面处具有装置。所述装置可为有源装置(例如晶体管、二极管等)、电容器、电阻器等。非有源表面可不具有装置。
内连线结构54位于半导体衬底52的有源表面之上且用于对半导体衬底52的装置进行电性连接以形成集成电路。内连线结构54可包括一或多个介电层及位于介电层中的相应金属化层。用于介电层的可接受的介电材料包括:氧化物,例如氧化硅或氧化铝;氮化物,例如氮化硅;碳化物,例如碳化硅;类似材料;或其组合,例如氮氧化硅、碳氧化硅、碳氮化硅、碳氮氧化硅或类似材料。亦可使用其他介电材料,例如聚合物(如聚苯并恶唑(polybenzoxazole,PBO)、聚酰亚胺、苯并环丁烯(benzocyclobuten,BCB)系聚合物或类似聚合物)。金属化层可包括导通孔及/或导电线,以对半导体衬底52的装置进行内连。金属化层可由导电材料(例如金属,如铜、钴、铝、金、其组合或类似金属)形成。可藉由镶嵌工艺(例如单镶嵌工艺、双镶嵌工艺或类似工艺)形成内连线结构54的金属化层。
管芯连接件56位于集成电路管芯50的前侧50F处。管芯连接件56可为进行外部连接的导电柱、接垫或类似连接件。管芯连接件56位于内连线结构54中及/或内连线结构54上。举例而言,管芯连接件56可为内连线结构54的上部金属化层的一部分。管芯连接件56可由金属(例如铜、铝或类似金属)形成且可藉由例如镀覆或类似方法形成。
可选地,在形成集成电路管芯50期间,可在管芯连接件56上设置焊料区(未单独示出)。焊料区可用于对集成电路管芯50执行芯片探针(chip probe,CP)测试。举例而言,焊料区可为用于将芯片探针贴合至管芯连接件56的焊料球、焊料凸块或类似连接件。可对集成电路管芯50执行芯片探针测试以确认集成电路管芯50是否是已知良好管芯(known gooddie,KGD)。因此,只有作为KGD且经受后续处理的集成电路管芯50会被封装且未通过芯片探针测试的管芯不会被封装。在测试之后,可在后续处理步骤中移除焊料区。
介电层58位于集成电路管芯50的前侧50F处。介电层58位于内连线结构54中及/或内连线结构54上。举例而言,介电层58可为内连线结构54的上部介电层。介电层58在侧向上对管芯连接件56进行包封。介电层58可为氧化物、氮化物、碳化物、聚合物、类似材料或其组合。可例如藉由旋转涂布、叠层、化学气相沉积(chemical vapor deposition,CVD)或类似方法来形成介电层58。在开始时,介电层58可隐埋管芯连接件56,使得介电层58的顶表面位于管芯连接件56的顶表面上方。管芯连接件56可经由介电层58被暴露出来。使管芯连接件56暴露出可移除可能存在于管芯连接件56上的任何焊料区。可对各层应用移除工艺,以移除管芯连接件56之上的多余材料。移除工艺可为平坦化工艺,例如化学机械研磨(chemicalmechanical polish,CMP)、回蚀、其组合或类似工艺。在平坦化工艺之后,管芯连接件56的顶表面与介电层58的顶表面共面(在工艺变化内)且在集成电路管芯50的前侧50F处被暴露出来。
图2A至图2B分别是管芯堆叠60A、60B的剖视图。管芯堆叠60A、60B可各自具有单一功能(例如逻辑设备、内存管芯等)或者可具有多种功能。在一些实施例中,管芯堆叠60A是逻辑设备(例如集成芯片上系统(system-on-integrated-chip,SoIC)装置)且管芯堆叠60B是内存装置(例如高带宽内存(high bandwidth memory,HBM)装置)。
如图2A中所示,管芯堆叠60A包括结合于一起的两个集成电路管芯50(例如第一集成电路管芯50A与第二集成电路管芯50B)。在一些实施例中,第一集成电路管芯50A是逻辑管芯且第二集成电路管芯50B是接口管芯。接口管芯将逻辑管芯桥接至内存管芯且在逻辑管芯与内存管芯之间对命令进行转译。在一些实施例中,对第一集成电路管芯50A与第二集成电路管芯50B进行结合,使得有源表面彼此面对(例如「面对面」结合)。可穿过集成电路管芯50中的一者形成导通孔62,使得可对管芯堆叠60A进行外部连接。导通孔62可为衬底穿孔(through-substrate via,TSV),例如硅穿孔或类似穿孔。在所示实施例中,导通孔62形成于第二集成电路管芯50B(例如接口管芯)中。导通孔62延伸穿过相应集成电路管芯50的半导体衬底52,以在实体上连接且电性连接至内连线结构54的金属化层。
如图2B中所示,管芯堆叠60B是包括多个半导体衬底52的堆叠装置。举例而言,管芯堆叠60B可为包括多个内存管芯的内存装置,例如混合内存立方体(hybrid memorycube,HMC)装置、高带宽内存(HBM)装置或类似装置。半导体衬底52中的每一者可具有(或可不具有)单独的内连线结构54。藉由例如TSV等导通孔62对半导体衬底52进行连接。
图3至图14是根据一些实施例的制造集成电路封装200的中间阶段的视图。图3、图4、图6、图7、图8、图9、图10、图11、图12及图13是剖视图。图5A、图5B、图5C及图14是俯视图,其中为使例示清晰起见而省略一些特征。藉由将集成电路装置120结合至晶片110来形成封装组件100。晶片110具有封装区110A,所述封装区110A包括例如中介层140等装置。将在后续处理中对封装区110A进行单体化以形成封装组件100,所述封装组件100包括晶片110的经单体化部分(例如中介层140)及结合至晶片110的所述经单体化部分的集成电路装置120。在实施例中,封装组件100是晶片上芯片(chip-on-wafer,CoW)组件,但应理解,可将实施例应用于其他三维集成电路(three-dimensional integrated circuit,3DIC)封装。然后将封装组件100安装至封装衬底210。另外,在封装组件100周围及封装组件100上将封装加强件230贴合至封装衬底210。在实施例中,所得的集成电路封装200是衬底上晶片上芯片(chip-on-wafer-on-substrate,)封装,但应理解,可将实施例应用于其他3DIC封装。
示出对晶片110的一个封装区110A的处理。应理解,可同时对晶片110的任意数目的封装区110A进行处理及单体化,以自晶片110的经单体化部分形成多个封装组件100。
在图3中,获得或形成晶片110。晶片110包括封装区110A中的装置,所述装置将在后续处理中被单体化以包括于封装组件100中。晶片110中的装置可为中介层、集成电路管芯或类似装置。在一些实施例中,在晶片110中形成中介层140,其中所述中介层140包括衬底112、内连线结构114及导通孔116。
衬底112可为块状半导体衬底、绝缘体上半导体(SOI)衬底、多层式半导体衬底或类似衬底。衬底112可包含半导体材料,例如:硅;锗;化合物半导体,包括碳化硅、砷化镓、磷化镓、磷化铟、砷化铟及/或锑化铟;合金半导体,包括硅锗、砷磷化镓、砷化铝铟、砷化铝镓、砷化镓铟、磷化镓铟及/或砷磷化镓铟;或其组合。亦可使用其他衬底,例如多层式衬底或梯度衬底。衬底112可为经掺杂的或未经掺杂的。在晶片110中形成中介层的实施例中,衬底112中一般不包括有源装置,但中介层可包括形成于衬底112的前表面(例如图3中面朝上的表面)中及/或所述前表面上的无源装置。在晶片110中形成集成电路装置的实施例中,可在衬底112的前表面中及/或所述前表面上形成有源装置(例如晶体管、电容器、电阻器、二极管及类似有源装置)。
内连线结构114位于衬底112的前表面之上且用于对衬底112的装置(若存在)进行电性连接。内连线结构114可包括一或多个介电层及位于介电层中的相应金属化层。用于介电层的可接受的介电材料包括:氧化物,例如氧化硅或氧化铝;氮化物,例如氮化硅;碳化物,例如碳化硅;类似材料;或其组合,例如氮氧化硅、碳氧化硅、碳氮化硅、碳氮氧化硅或类似材料。亦可使用其他介电材料,例如聚合物(例如聚苯并恶唑(PBO)、聚酰亚胺、苯并环丁烯(BCB)系聚合物或类似聚合物)。金属化层可包括导通孔及/或导电线,以将任何装置内连于一起及/或内连至外部装置。金属化层可由导电材料(例如金属,例如铜、钴、铝、金、其组合或类似金属)形成。可藉由镶嵌工艺(例如单镶嵌工艺、双镶嵌工艺或类似工艺)形成内连线结构114的金属化层。
在一些实施例中,在晶片110的前侧处具有管芯连接件及介电层(未单独示出)。具体而言,晶片110可包括与针对图1阐述的集成电路管芯50的管芯连接件及介电层相似的管芯连接件及介电层。举例而言,管芯连接件及介电层可为内连线结构114的上部金属化层的一部分。
导通孔116延伸至内连线结构114及/或衬底112中。导通孔116电性连接至内连线结构114的金属化层。导通孔116可为TSV。作为形成导通孔116的实例,可藉由例如刻蚀、研磨(milling)、激光技术、其组合或类似技术在内连线结构114及/或衬底112中形成凹陷部(recess)。可例如藉由CVD、原子层沉积(atomic layer deposition,ALD)、物理气相沉积(physical vapor deposition,PVD)、热氧化、其组合或类似工艺在开口中共形地沉积薄的障壁层。障壁层可由氧化物、氮化物、碳化物、其组合或类似材料形成。可在障壁层之上及开口中沉积导电材料。可藉由电化学镀覆工艺、CVD、ALD、PVD、其组合或类似工艺形成导电材料。导电材料的实例为铜、钨、铝、银、金、其组合或类似材料。藉由例如CMP自内连线结构114或衬底112的表面移除多余的导电材料及障壁层。障壁层的剩余部分与导电材料的剩余部分形成导通孔116。
在图4中,将集成电路装置120贴合至晶片110的前侧。多个集成电路装置120在封装区110A中彼此相邻地放置。集成电路装置120包括一或多个逻辑设备120A及多个内存装置120B。逻辑设备120A与内存装置120B可在相同技术节点的工艺中形成或可在不同技术节点的工艺中形成。举例而言,逻辑设备120A可藉由相较于内存装置120B更先进的工艺节点形成。
在所示实施例中,使用焊料结合件(例如使用导电连接件122)将集成电路装置120贴合至晶片110。可使用例如拾取及放置工具将集成电路装置120放置于内连线结构114上。导电连接件122可由可回焊的导电材料(例如焊料、铜、铝、金、镍、银、钯、锡、类似材料或其组合)形成。在一些实施例中,藉由在开始时经由例如蒸镀、电镀、印刷、焊料转移、植球或类似方法等方法形成焊料层来形成导电连接件122。一旦已在所述结构上形成焊料层,便可执行回焊,以将导电连接件122塑形成所期望的凸块形状。将集成电路装置120贴合至晶片110可包括将集成电路装置120放置于晶片110上且对导电连接件122进行回焊。导电连接件122在晶片110与集成电路装置120的对应管芯连接件之间形成接头,进而将中介层140电性连接至集成电路装置120。
可在导电连接件122周围以及晶片110与集成电路装置120之间形成底部填充胶124。底部填充胶124可减小应力且对藉由对导电连接件122进行回焊而形成的接头进行保护。底部填充胶124可由底部填充材料(例如模制化合物、环氧树脂或类似材料)形成。可在将集成电路装置120贴合至晶片110之后藉由毛细流动工艺形成底部填充胶124,或可在将集成电路装置120贴合至晶片110之前藉由适合的沉积方法形成底部填充胶124。可以液体或半液体形式施加底部填充胶124,随后使底部填充胶124固化。
在其他实施例(未单独示出)中,使用直接结合件将集成电路装置120贴合至晶片110。举例而言,可在不使用粘合剂或焊料的情况下使用熔融结合、介电质结合、金属结合、其组合(例如,介电质对介电质结合与金属对金属结合的组合)或类似结合来对晶片110与集成电路装置120的对应介电层及/或管芯连接件进行直接结合。当使用直接结合时,可省略底部填充胶124。此外,可使用结合技术的组合,例如可藉由焊料结合件将一些集成电路装置120贴合至晶片110且可藉由直接结合件将其他集成电路装置120贴合至晶片110。
逻辑设备120A中的每一者可为中央处理单元(CPU)、图形处理单元(GPU)、系统芯片(SoC)、微控制器或类似装置。逻辑设备120A中的每一者可为集成电路管芯(与针对图1阐述的集成电路管芯50相似)或可为管芯堆叠(与针对图2A阐述的管芯堆叠60A相似)。在此实施例中,逻辑设备120A是集成电路管芯(例如系统芯片(SoC)管芯)。在其他实施例(未单独示出)中,逻辑设备120A是管芯堆叠(例如SoIC装置)。
内存装置120B中的每一者可为动态随机存取内存(DRAM)管芯、静态随机存取内存(SRAM)管芯、混合内存立方体(HMC)模块、高带宽内存(HBM)模块或类似管芯。内存装置120B中的每一者可为集成电路管芯(与针对图1阐述的集成电路管芯50相似)或可为管芯堆叠(与针对图2B阐述的管芯堆叠60B相似)。在此实施例中,内存装置120B是管芯堆叠(例如高带宽内存(HBM)装置)。
所期望类型及数量的集成电路装置120被贴合于封装区110A中且在俯视图中具有所期望的布局。在一些实施例中,如图5A中所示,集成电路装置120包括逻辑设备120A及多个内存装置120B,其中逻辑设备120A与内存装置120B在俯视图中以对称方式进行布局。在一些实施例中,如图5B中所示,集成电路装置120包括多个逻辑设备120A及多个内存装置120B,其中逻辑设备120A与内存装置120B在俯视图中以非对称方式进行布局。在一些实施例中,如图5C中所示,集成电路装置120包括多个逻辑设备120A及多个内存装置120B,其中逻辑设备120A与内存装置120B在俯视图中以对称方式进行布局。对称布局是其中内存装置120B具有围绕逻辑设备120A的至少一条对称轴的布局。逻辑设备120A在俯视图中可设置于内存装置120B之间。非对称布局是其中内存装置120B不具有围绕逻辑设备120A的对称轴的布局。相对于图5A所示布局示出图4及后续各视图,但是应理解,实施例可同样适用于图5B及图5C所示布局。
在图6中,在各个组件上及各个组件周围形成包封体126。在形成之后,包封体126对底部填充胶124(若存在)及集成电路装置120进行包封。包封体126可为模制化合物、环氧树脂或类似材料。包封体126可藉由压缩模制(compression molding)、转移模制(transfermolding)或类似模制施加且形成于晶片110之上,使得集成电路装置120被隐埋或覆盖。包封体126进一步形成于集成电路装置120之间的间隙区中。可以液体或半液体形式施加包封体126,随后使包封体126固化。
在图7中,对包封体126进行薄化以暴露出集成电路装置120。薄化工艺可为磨削工艺、化学机械研磨(CMP)、回蚀、其组合或类似工艺。在薄化工艺之后,集成电路装置120的顶表面与包封体126的顶表面实质上共面(在工艺变化内)。执行薄化直至已移除所期望量的集成电路装置120及包封体126。
在图8中,对中间结构进行翻转(未单独示出)以准备对晶片110的背侧进行处理。可将中间结构放置于载体衬底128或其他合适的支撑结构上以进行后续处理。举例而言,可将载体衬底128贴合至集成电路装置120及/或包封体126。可藉由离型层将载体衬底128贴合至集成电路装置120及/或包封体126。离型层可由聚合物系材料形成,其可与载体衬底128一起自进行处置之后的结构被移除。在一些实施例中,载体衬底128例如是块状半导体或玻璃衬底等衬底。在一些实施例中,离型层是在受热时会失去其粘合性质的环氧系热离型材料,例如光热转换(light-to-heat-conversion,LTHC)离型涂层。
在图9中,对衬底112进行薄化以暴露出导通孔116。可藉由薄化工艺(例如磨削工艺、化学机械研磨(CMP)、回蚀、其组合或类似工艺)来达成导通孔116的暴露。在所示实施例中,执行凹陷工艺以使衬底112的背侧凹陷,使得导通孔116在晶片110的背侧处突出。凹陷工艺可为例如合适的回蚀工艺、化学机械研磨(CMP)或类似工艺。在一些实施例中,用于使导通孔116暴露出的薄化工艺包括CMP且导通孔116由于在CMP期间出现的下凹而在晶片110的背侧处突出。可选地在衬底112的背面上形成环绕导通孔116的突出部分的绝缘层132。在一些实施例中,绝缘层132由含硅介电材料(例如氮化硅、氧化硅、氮氧化硅或类似材料)形成且可藉由合适的沉积方法(例如CVD或类似方法)形成。在一开始时,绝缘层132可隐埋导通孔116。可对各个层执行移除工艺,以移除导通孔116之上的多余材料。移除工艺可为平坦化工艺,例如化学机械研磨(CMP)、回蚀、其组合或类似工艺。在平坦化之后,导通孔116的被暴露出的表面与绝缘层132的被暴露出的表面实质上共面(在工艺变化内)且在晶片110的背侧处被暴露出。在另一实施例中,省略绝缘层132且衬底112的被暴露出的表面与导通孔116的被暴露出的表面实质上共面(在工艺变化内)。
在图10中,在导通孔116的被暴露出的表面及绝缘层132的被暴露出的表面(或在绝缘层132被省略时在衬底112的被暴露出的表面)上形成凸块下金属(under bumpmetallurgy,UBM)134。作为形成UBM 134的实例,在导通孔116的被暴露出的表面及绝缘层132(若存在)的被暴露出的表面或衬底112的被暴露出的表面之上形成晶种层(未单独示出)。在一些实施例中,晶种层是金属层,可为单层或包括由不同材料形成的多个子层的复合层。在一些实施例中,晶种层包括钛层及位于钛层之上的铜层。可使用例如PVD或类似工艺来形成晶种层。接着,在晶种层上形成光刻胶且对所述光刻胶进行图案化。光刻胶可藉由旋转涂布或类似工艺来形成且可被曝露于光以进行图案化。光刻胶的图案对应于UBM 134。所述图案化形成穿过光刻胶以暴露出晶种层的开口。然后在光刻胶的开口中及晶种层的被暴露出的部分上形成导电材料。可藉由镀覆(例如电镀或无电镀覆或类似镀覆)来形成所述导电材料。所述导电材料可包括金属,例如铜、钛、钨、铝或类似金属。然后,移除光刻胶以及晶种层的上面未形成导电材料的部分。可藉由可接受的灰化工艺或剥除工艺(例如使用氧等离子体或类似等离子体)来移除光刻胶。一旦光刻胶被移除,便例如使用可接受的刻蚀工艺来移除晶种层的被暴露出的部分。晶种层的剩余部分与导电材料形成UBM 134。
此外,在UBM 134上形成导电连接件136。导电连接件136可为球栅阵列(ball gridarray,BGA)连接件、焊料球、金属柱、受控塌陷芯片连接(controlled collapse chipconnection,C4)凸块、微凸块、无电镀镍钯浸金(electroless nickel-electrolesspalladium-immersion gold,ENEPIG)技术所形成的凸块或类似连接件。导电连接件136可由可回焊的导电材料(例如焊料、铜、铝、金、镍、银、钯、锡、类似材料或其组合)形成。在一些实施例中,藉由在一开始时经由蒸镀、电镀、印刷、焊料转移、植球或类似工艺形成焊料层来形成导电连接件136。一旦已在所述结构上形成焊料层,便可执行回焊,以将材料塑形成所期望的凸块形状。在另一实施例中,导电连接件136包括藉由溅镀、印刷、电镀、无电镀覆、CVD或类似工艺形成的金属柱(例如铜柱)。金属柱可不具有焊料且具有实质上垂直的侧壁。在一些实施例中,在金属柱的顶上形成金属顶盖层(metal cap layer)。金属顶盖层可包含可藉由镀覆工艺形成的镍、锡、锡铅、金、银、钯、铟、镍钯金、镍金、类似材料或其组合。
在图11中,执行载体剥离以将载体衬底128自集成电路装置120及/或包封体126拆离(剥离)。在藉由离型层将载体衬底128贴合至集成电路装置120及/或包封体126的实施例中,所述剥离包括向离型层投射例如激光或紫外(ultraviolet,UV)光等光线,使得离型层在光的热作用下分解且可移除载体衬底128。然后对所述结构进行翻转并将其放置于胶带(未单独示出)上。
此外,藉由沿着例如封装区110A周围的切割道区进行切割来执行单体化工艺。所述单体化工艺可包括锯切、切割或类似工艺。举例而言,单体化工艺可包括对绝缘层132、包封体126、内连线结构114及衬底112进行锯切。单体化工艺使封装区110A自相邻的封装区单体化。所得的经单体化的封装组件100是来自封装区110A。单体化工艺自晶片110的经单体化部分形成中介层140。中介层140亦包括绝缘层132的一些部分及UBM 134的一些部分。作为单体化工艺的结果,中介层140的外侧壁与包封体126的外侧壁在侧向上相接(在工艺变化内)。
在图12中,将封装组件100贴合至封装衬底210。封装衬底210包括衬底芯212,所述衬底芯212可由半导体材料(例如硅、锗、金刚石或类似材料)制成。作为另外一种选择,亦可使用化合物材料,例如硅锗、碳化硅、砷化镓、砷化铟、磷化铟、碳化硅锗、砷磷化镓、磷化镓铟、其组合或类似材料。另外,衬底芯212可为SOI衬底。一般而言,SOI衬底包括例如外延硅、锗、硅锗、SOI、绝缘体上硅锗(silicon germanium on insulator,SGOI)或其组合等半导体材料形成的层。在一替代实施例中,衬底芯212例如是玻璃纤维加强树脂芯等绝缘芯。一实例性芯材料是玻璃纤维树脂(例如弗朗克功能调节剂(Frankle’s functional regulator-4,FR4))。所述芯材料的替代材料包括双马来酰亚胺三嗪(bismaleimide-triazine,BT)树脂,或者作为另外一种选择而为其他印刷电路板(printed circuit board,PCB)材料或膜。可对衬底芯212使用例如味之素增层膜(Ajinomoto build-up film,ABF)等增层膜或者其他叠层体。
衬底芯212可包括有源装置及无源装置(未单独示出)。可使用例如晶体管、电容器、电阻器、其组合及类似装置等装置来产生系统设计的结构要求及功能要求。可使用任何合适的方法来形成所述装置。
衬底芯212亦可包括金属化层及通孔(未单独示出)以及位于所述金属化层及通孔之上的结合接垫214。金属化层可形成于有源装置及无源装置之上且被设计成对各种装置进行连接以形成功能电路系统。金属化层可由介电材料(例如低介电常数介电材料)与导电材料(例如铜)构成的交替层形成,其中通孔对导电材料层进行内连且可藉由任何合适的工艺(例如沉积、镶嵌、双镶嵌或类似工艺)形成所述金属化层。在一些实施例中,衬底芯212实质上不具有有源装置及无源装置。
将封装组件100贴合至封装衬底210可包括将封装组件100放置于封装衬底210上且对导电连接件136进行回焊。对导电连接件136进行回焊以将UBM 134贴合至结合接垫214。导电连接件136将包括中介层140的金属化层的封装组件100连接至包括衬底芯212中的金属化层的封装衬底210。因此,封装衬底210电性连接至集成电路装置120。在一些实施例中,将无源装置(例如表面安装组件(surface mount device,SMD),未单独示出)在安装于封装衬底210上之前贴合至封装组件100(例如贴合至UBM 134)。在此类实施例中,可将无源装置贴合至封装组件100的与导电连接件136相同的表面。
在一些实施例中,在封装组件100与封装衬底210之间形成环绕导电连接件136及UBM 134的底部填充胶216。可在对封装组件100进行贴合之后藉由毛细流动工艺形成底部填充胶216,或可在对封装组件100进行贴合之前藉由合适的沉积方法形成底部填充胶216。底部填充胶216可为自封装衬底210延伸至中介层140的连续材料。
另外,将无源装置218贴合至封装衬底210。将无源装置218贴合至封装衬底210的与导电连接件136相同的表面。可在将封装组件100贴合至封装衬底210之前或之后将无源装置218贴合至封装衬底210。无源装置218可包括电容器、电阻器、电感器、类似装置或其组合。无源装置218可为表面安装组件(SMD)、2个端子的集成无源组件(integrated passivedevice,IPD)、多个端子的IPD或类似装置。
可选地,在无源装置218上及无源装置218周围形成保护层220。每一保护层220位于相应的无源装置218之上。保护层220对无源装置218与封装衬底210的接口进行密封,使得随后形成的热界面材料不会使无源装置218短路。可藉由形成绝缘材料且对所述绝缘材料进行图案化来形成保护层220。绝缘材料可为基于聚对二甲苯(parylene)的涂层,所述涂层具有高电阻及/或抵抗湿气渗透。绝缘材料可为硅酮系绝缘材料,例如硅酮胶、硅酮粘合剂、硅酮弹性体、硅酮橡胶或类似材料;聚合物材料,例如聚苯并恶唑(PBO)、聚酰亚胺、苯并环丁烯(BCB)系聚合物或类似材料;叠层材料,例如味之素增层膜(ABF)或类似叠层材料;其组合;或类似材料。可例如藉由沉积、旋转涂布、叠层或类似方法形成绝缘材料。
在图13中,将封装加强件230贴合至封装衬底210及封装组件100。封装加强件230是有助于减少封装衬底210及封装组件100的翘曲的加强环。封装加强件230由例如以下刚性材料形成:铜、铝、钴、经镍涂覆的铜、不锈钢、钨、铜钨合金、铜钼合金、银金刚石、铜金刚石、金属金刚石复合材料、氮化铝、碳化铝硅、铁镍合金(例如合金42)、类似材料或其组合。在一些实施例中,封装加强件230包括由第一金属形成的主体且所述主体局部或完全涂覆有第二金属,例如金、镍、钛金合金、铅、锡、镍钒合金或类似材料。在一些实施例中,封装加强件230由例如以下超导材料形成:银金刚石、类金刚石碳、银-金刚石复合材料、铜金刚石复合材料、铝金刚石复合材料、合金42金刚石复合材料、碳金属复合材料、类似材料或其组合。在一些实施例中,封装加强件230的材料具有介于145×103MPa至200×103MPa的范围内的杨氏模量且具有介于1.3ppm/℃至17.8ppm/℃的范围内的热膨胀系数。
可使用粘合剂234将封装加强件230贴合至封装衬底210。粘合剂234可为任何合适的粘合剂、环氧树脂、贴合膜或类似粘合剂。可将粘合剂234施加至封装加强件230或可将粘合剂234施加至封装衬底210的上表面。
在此实施例中,封装加强件230包括上部部分230A及下部部分230B。上部部分230A位于封装组件100的周边上方且耦合至封装组件100。下部部分230B位于封装组件100的周边周围且耦合至封装衬底210。上部部分230A的宽度大于下部部分230B的宽度。封装加强件230的高度大于封装组件100的高度。
使用下部阻隔件236将封装加强件230贴合至封装组件100。下部阻隔件236对其中封装加强件230与封装组件100交叠的区200R进行完全填充,进而对封装衬底210与封装加强件230之间的区域进行密封以形成空隙238。空隙238在俯视图中围绕封装组件100。封装加强件230与无源装置218交叠,因此无源装置218处于空隙238中。藉由使用下部阻隔件236对空隙238进行密封,即使在热界面材料是液态金属时,随后形成于封装组件100上的热界面材料仍可降低流动至无源装置218并使无源装置218短路的风险。在一些实施例中,下部阻隔件236具有介于0.02毫米至0.5毫米的范围内的厚度。
下部阻隔件236由弹性粘合材料形成。下部阻隔件236是弹性阻隔件。可接受的弹性粘合材料包括石墨、硅酮系粘合剂、环氧树脂系粘合剂及类似粘合剂。如随后所阐述,可使用其他可接受的弹性粘合材料。下部阻隔件236的材料可与粘合剂234的材料不同。在一些实施例中,下部阻隔件236由包含固化促进剂的橡胶材料形成。
在一些实施例中,下部阻隔件236由相变材料(phase-change material,PCM)及填料形成。填料可为金属,例如铝。相变材料能够在所期望温度以上自固态相变至软态(例如粘性液态)。在一些实施例中,相变材料在介于40℃至60℃的范围内的温度下自固体变成粘性液体。更一般而言,相变材料的粘度随着温度升高而降低。相变材料可包括在两种状态下为所述填料提供良好热稳定性的长聚合物链。相变材料可作为接垫来施加或者作为弹性体来分配。在一些实施例中,相变材料是包括聚合物成分、无定形聚合物基质、硅酮-有机嵌段共聚物、导热填料、处理剂及抗氧化剂的基质。在一些实施例中,相变材料包括石蜡(paraffin wax)、烷烃(alkyl hydrocarbon)或无定形乙烯丙烯橡胶(ethylenepropylene)。在一些实施例中,相变材料包括锡铟铋合金。有利地,相变材料可具有良好的散热性、良好的间隙填充能力(此可有助于确保区200R被填充)、良好的润湿性、低热阻、低杨氏模量(此可降低破裂的风险)以及良好的延展性(此可降低分层的风险)。在一些实施例中,相变材料具有介于30Pa·s至1000Pa·s的范围内的粘度、介于2至5的范围内的比重、介于2W/m·k至100W/m·k的范围内的k值、介于20ppm/℃至80ppm/℃的范围内的热膨胀系数以及介于20kPa至100kPa的范围内的杨氏模量。
下部阻隔件236可被预成型为具有所期望形状的膜或接垫,所述膜或接垫被施加至封装加强件230或封装组件100。下部阻隔件236位于封装组件100的周边周围,其中封装组件100的中心不与下部阻隔件236接触。下部阻隔件236局部或完全覆盖内存装置120B。
另外,可在封装加强件230上形成上部阻隔件240。上部阻隔件240将对封装加强件230与随后贴合的散热片之间的区进行完全填充,进而对随后贴合的散热片与封装组件100之间的区域进行密封以形成空隙。因此,即使在热界面材料是液态金属时,随后形成于封装组件100上的热界面材料仍可降低泄漏的风险。在一些实施例中,上部阻隔件240可具有介于0.05毫米至0.5毫米的范围内的厚度。上部阻隔件240的厚度可与下部阻隔件236的厚度不同。举例而言,上部阻隔件240可厚于下部阻隔件236。
上部阻隔件240可由下部阻隔件236的候选材料中的任意者形成。上部阻隔件240的材料可(或可不)与下部阻隔件236的材料相同。举例而言,下部阻隔件236与上部阻隔件240二者可由相同的相变材料形成。上部阻隔件240可被预成形为具有所期望形状的膜或接垫,所述膜或接垫被施加于封装加强件230。上部阻隔件240是弹性阻隔件。
开口232延伸穿过上部阻隔件240、封装加强件230及下部阻隔件236。因此,上部阻隔件240、封装加强件230及下部阻隔件236分别是环,其中开口232延伸穿过每一环的中间。因此,如图14中所示,上部阻隔件240、封装加强件230及下部阻隔件236在俯视图中各自具有环形轮廓。环形组件的宽度是指环形组件的外径与内径之间的差。上部阻隔件240与封装加强件230可具有相同的环形轮廓,而下部阻隔件236具有与上部阻隔件240及封装加强件230不同的环形轮廓。封装加强件230在俯视图中可为由封装加强件230的直的水平部分及垂直部分进行界定的矩形环。开口232在俯视图中设置于逻辑设备120A上方且在此实施例中暴露出逻辑设备120A。开口232的宽度小于封装组件100的宽度且可大于逻辑设备120A的宽度。
逻辑设备120A可具有大的功率密度。举例而言,CPU或GPU可具有高达4W/mm2的功率密度且具有此种逻辑设备120A的封装组件100可具有介于400瓦特至600瓦特的范围内的总功耗。当逻辑设备120A具有大的功率密度时,可在封装组件100中形成热点。开口232暴露出封装组件100的一部分,具体而言,至少局部地暴露出逻辑设备120A中的每一者。在集成电路装置120以对称方式进行布局的一些实施例中,开口232完全暴露出逻辑设备120A中的每一者。在集成电路装置120以非对称方式进行布局的一些实施例中,开口232局部地暴露出逻辑设备120A中的每一者。上部阻隔件240、封装加强件230及下部阻隔件236中的每一者至少局部地与内存装置120B交叠,使得开口232不完全暴露出内存装置120B。开口232为随后设置的散热片提供区域,使得散热片可直接贴合至逻辑设备120A。因此散热片可直接热耦合至逻辑设备120A(在封装加强件230不处于散热片与逻辑设备120A之间的热路径中的情况下),以有助于减少封装组件100中热点的形成。
图15是根据一些实施例的实施图13至图14所示集成电路封装200的装置的剖视图。所述装置可为例如高效能计算(high-performance computing,HPC)系统、人工智能(artificial intelligence,AI)加速器或类似装置。
将散热片302贴合至集成电路封装200(例如贴合至封装加强件230及封装组件100)。散热片302可为热盖(thermal lid)、散热器、水冷却块或类似者。散热片302可由具有高热导率的材料(例如金属,如铜、钢、铁或类似金属)形成。可使用例如镍及/或金等涂层对散热片302进行金属化。散热片302保护封装组件100且形成热路径以自封装组件100的各个组件传导热量。散热片302具有主要部分302M及突出部分302P。主要部分302M设置于封装加强件230上方且藉由上部阻隔件240贴合至封装加强件230。突出部分302P插置于开口232(参见图13)中且直接耦合至逻辑设备120A。如此一来,突出部分302P延伸穿过上部阻隔件240、封装加强件230及下部阻隔件236。有利地,封装加强件230不处于散热片302与逻辑设备120A之间的热路径中。
使用热界面材料304将散热片302粘合至封装组件100。热界面材料304具有高热导率。在一些实施例中,热界面材料304是具有导热填料的聚合物。可接受的导热填料可包括氧化铝、氮化硼、氮化铝、铝、铜、银、铟、其组合或类似材料。在一些实施例中,热界面材料304是基于膜或基于片材的材料,例如具有整合至片材中的合成奈米碳管结构的片材、具有垂直定向的石墨填料的导热片材或类似片材。在一些实施例中,热界面材料304是液态金属、金属接垫、另一金属材料、其组合或类似材料。可接受的液态金属可包括焊料、铟、铜、铋、锡、铑、钯、铂、银、金、镓、其组合或类似材料,所述液态金属以膜形式或液体形式被施加。热界面材料304与下部阻隔件236及上部阻隔件240的材料不同。可将热界面材料304分配于开口232(参见图13)中及封装组件100上(例如逻辑设备120A的背侧表面上)及/或散热片302的突出部分302P上。亦可藉由其他技术将散热片302贴合至封装组件100。
使用上部阻隔件240将散热片302贴合至封装加强件230。上部阻隔件240对其中散热片302与封装加强件230交叠的区进行完全填充,进而对散热片302与封装组件100之间的区域进行密封以形成空隙306。空隙306在俯视图中围绕散热片302的突出部分302P且热界面材料304位于空隙306中。空隙306是开口232(参见图13)的剩余且被密封的部分。藉由使用上部阻隔件240对空隙306进行密封,热界面材料304可降低流动至无源装置218且使无源装置218短路的风险。空隙306中的热界面材料304可沿着封装组件100的顶表面、散热片302的突出部分302P的底表面、下部阻隔件236的侧壁、封装加强件230的侧壁及/或散热片302的突出部分302P的侧壁延伸。空隙306中的热界面材料304亦可沿着上部阻隔件240的侧壁延伸。
实施例可达成优点。利用封装加强件230有助于减少封装衬底210及封装组件100的翘曲。封装加强件230中的开口232(参见图13)使得散热片302的突出部分302P能够直接贴合至逻辑设备120A。如前面所述,逻辑设备120A可具有大的功率密度。将散热片302直接热耦合至逻辑设备120A(在封装加强件230不处于散热片302与逻辑设备120A之间的热路径中的情况下)可改善散热且有助于减少封装组件100中热点的形成。此外,将散热片302直接贴合至逻辑设备120A(而非在逻辑设备120A之上形成封装加强件230)使得来自封装组件100的散热能够较少地依赖于翘曲,此在封装组件100包括多个大的装置(例如多个SoC)时尤其有利。
亦可包括其他特征及工艺。举例而言,可包括测试结构以帮助对3D封装或3DIC装置进行验证测试。所述测试结构可例如包括在重布线层中或在衬底上形成的测试接垫(test pad),以便能够对3D封装或3DIC进行测试、对探针及/或探针卡(probe card)进行使用以及进行类似操作。可对中间结构以及最终结构执行验证测试。另外,可将本文中所揭露的结构及方法与包括对已知良好管芯进行中间验证的测试方法结合使用,以提高良率并降低成本。
图16是根据一些实施例的实施集成电路封装200的装置的剖视图。此实施例与图15所示实施例相似,不同的是封装组件100包括位于集成电路装置120的背侧表面上的虚设金属化体262。在封装组件100之前或之后对虚设金属化体262进行单体化。因此下部阻隔件236及热界面材料304设置于虚设金属化体262的表面上,而非直接设置于逻辑设备120A的背侧表面上。虚设金属化体262为热界面材料304提供具有良好润湿能力的表面。当形成虚设金属化体262时,开口232(参见图13)暴露出虚设金属化体262而非逻辑设备120A。
虚设金属化体262可由导电材料(例如铜、钛、镍、金、类似材料或其组合)形成。可藉由在包封体126及集成电路装置120之上沉积晶种层,然后将导电材料电镀至晶种层上来形成虚设金属化体262。亦可藉由对导电材料进行溅镀来形成虚设金属化体262。虚设金属化体262与集成电路封装200的有源装置及/或无源装置电性隔离。在一些实施例中,虚设金属化体262包括铜层、位于铜层上的钛层、位于钛层上的镍钒层以及位于镍钒层上的金层,其中铜层具有约0.15微米的厚度,钛层具有约0.1微米的厚度,镍钒层具有约0.3微米的厚度且金层具有约0.1微米的厚度。亦可利用其他金属层。举例而言,虚设金属化体262亦可包括钛/镍/银结构、钛/镍/钛/银结构、钛/镍/银/镍结构、钛/镍/银/锡结构或类似结构。在一些实施例中,虚设金属化体262具有约0.65微米的总厚度。
图17是根据一些实施例的实施集成电路封装200的装置的剖视图。此实施例与图16所示实施例相似,不同的是封装加强件230不直接贴合至封装衬底210。相反,使用粘合剂234将环264贴合至封装衬底210。将封装加强件230贴合至环264。可使用粘合剂266将封装加强件230贴合至环264。环264可由封装加强件230的候选材料中的任意者形成。粘合剂266可由粘合剂234的候选材料中的任意者形成。环264由与封装加强件230不同的材料形成。可将封装加强件230及环264的材料选择成获得所期望的热膨胀系数。封装加强件230位于环264上方且耦合至环264以及封装组件100的周边。环264围绕封装组件100的周边且耦合至封装衬底210。封装加强件230的宽度大于环264的宽度。在此实施例中,封装加强件230的高度小于封装组件100的高度。
图18是根据一些实施例的实施集成电路封装200的装置的剖视图。此实施例与图16所示实施例相似,不同的是封装加强件230具有面对封装衬底210的凹槽268。凹槽268位于比没有凹槽的封装加强件230的区域更薄的封装加强件230的区域中。形成具有薄的区域的封装加强件230使得封装加强件230能够具有可变形的结构,此可有助于在将封装加强件230安装至封装组件100期间减小施加于封装组件100上的应力。空隙238延伸至凹槽268中。
图19是根据一些实施例的实施集成电路封装200的装置的剖视图。此实施例与图18所示实施例相似,不同的是利用芯吸层(wicking layer)308代替虚设金属化体262。在芯吸层308上分配热界面材料304,使得芯吸层308位于热界面材料304与封装组件100的至少一部分之间。芯吸层308是经图案化的片材,其具有能够阻止热界面材料304流动的图案。因此,热界面材料304在封装加强件230之下流动的风险降低,尤其是当热界面材料304是液态金属时。芯吸层308可为金属网或金属多孔层,例如铜、金或类似材料。举例而言,芯吸层308可为开槽铜层、铜网层或烧结铜层。芯吸层308被预成型为所期望的形状,然后被贴合至封装组件100。可在将封装加强件230贴合至封装组件100之后将芯吸层308设置于开口232(参见图13)中,或可在将封装加强件230贴合至封装组件100之前将芯吸层308设置于封装组件100上。
图20是根据一些实施例的实施集成电路封装200的装置的剖视图。此实施例与图19所示实施例相似,不同的是利用包封体272代替下部阻隔件236及粘合剂234。包封体272形成于封装加强件230与封装衬底210、无源装置218及封装组件100之间。因此,包封体272对其中封装加强件230与封装组件100交叠的区进行完全填充。包封体272可为模制化合物、环氧树脂或类似材料。可藉由压缩模制、转移模制或类似模制来施加包封体272。可以液体或半液体形式施加包封体272,随后使包封体272固化。作为使用包封体272对封装加强件230与封装衬底210之间的区域进行填充的结果,热界面材料304可降低流动至无源装置218且使无源装置218短路的风险。另外,当利用包封体272时,可省略保护层220。
应理解,在适当的情况下,一些实施例可包括或省略一些特征。举例而言,可自图17及图18所示实施例省略虚设金属化体262。相似地,可自图19所示实施例省略凹槽268。
在实施例中,一种装置包括:集成电路封装,包括封装组件及贴合至所述封装组件的封装加强件;贴合至所述集成电路封装的散热片,所述散热片的主要部分设置于所述封装加强件上方,所述散热片的突出部分延伸穿过所述封装加强件;位于所述散热片的所述主要部分与所述封装加强件之间的弹性粘合材料;以及位于所述散热片的所述突出部分与所述封装组件之间的热界面材料,所述热界面材料与所述弹性粘合材料不同。在所述装置的一些实施例中,所述热界面材料是液态金属。在所述装置的一些实施例中,所述热界面材料是金属接垫。在所述装置的一些实施例中,所述弹性粘合材料是石墨。在所述装置的一些实施例中,所述弹性粘合材料是相变材料。在所述装置的一些实施例中,所述热界面材料沿着所述散热片的所述突出部分的底表面、沿着所述散热片的所述突出部分的侧壁、沿着所述封装组件的顶表面且沿着所述封装加强件的侧壁延伸。在一些实施例中,所述装置更包括位于所述热界面材料与所述封装组件之间的芯吸层。在所述装置的一些实施例中,所述芯吸层包括开槽铜层、铜网层或烧结铜层。
在实施例中,一种装置包括:封装衬底;贴合至所述封装衬底的封装组件,所述封装组件包括逻辑设备及内存装置;位于所述封装组件上的第一弹性阻隔件,所述第一弹性阻隔件与所述内存装置交叠;位于所述第一弹性阻隔件上的加强环,所述加强环与所述内存装置交叠;以及延伸穿过所述加强环及所述第一弹性阻隔件的开口,所述开口在俯视图中设置于所述逻辑设备上方。在所述装置的一些实施例中,所述第一弹性阻隔件对其中所述加强环与所述封装组件交叠的区进行完全填充。在一些实施例中,所述装置更包括位于所述加强环上的第二弹性阻隔件,所述开口延伸穿过所述第二弹性阻隔件。在一些实施例中,所述装置更包括贴合至所述封装衬底的无源装置,所述加强环与所述无源装置交叠。在所述装置的一些实施例中,所述开口暴露出所述逻辑设备。在一些实施例中,所述装置更包括位于所述封装组件上的虚设金属化体,所述开口暴露出所述虚设金属化体。在所述装置的一些实施例中,所述加强环包括面对所述封装衬底的凹槽。
在实施例中,一种方法包括:接收集成电路封装,所述集成电路封装包括封装组件及贴合至所述封装组件的封装加强件,其中所述封装加强件中的开口暴露出所述封装组件的一部分;在所述开口中分配热界面材料;以及使用第一弹性粘合材料将散热片的主要部分粘合至所述封装加强件,所述散热片的突出部分设置于所述开口中且接触所述热界面材料,所述第一弹性粘合材料对所述开口进行密封以在所述散热片的所述突出部分周围形成第一空隙。在一些实施例中,所述方法更包括:将所述封装组件贴合至封装衬底,所述封装组件包括逻辑设备及内存装置;以及使用第二弹性粘合材料将所述封装加强件粘合至所述封装组件,所述第二弹性粘合材料及所述封装加强件与所述内存装置交叠,所述开口在俯视图中设置于所述逻辑设备上方。在所述方法的一些实施例中,所述第二弹性粘合材料对所述封装衬底与所述封装加强件之间的区域进行密封,以在所述封装组件周围形成第二空隙。在一些实施例中,所述方法更包括:在所述开口中设置芯吸层,所述热界面材料被分配于所述芯吸层上。在所述方法的一些实施例中,在所述开口中分配所述热界面材料包括在所述开口中分配液态金属。
最后应说明的是:以上各实施例仅用以说明本实用新型的实施例的技术方案,而非对其限制;尽管参照前述各实施例对本实用新型的实施例进行了详细的说明,本领域的普通技术人员应当理解:其依然可以对前述各实施例所记载的技术方案进行修改,或者对其中部分或者全部技术特征进行等同替换;而这些修改或者替换,并不使相应技术方案的本质脱离本实用新型的实施例各实施例技术方案的范围。
Claims (10)
1.一种使用集成电路封装的装置,其特征在于,包括:
集成电路封装,包括:
封装组件;以及
封装加强件,贴合至所述封装组件;
散热片,贴合至所述集成电路封装,所述散热片的主要部分设置于所述封装加强件上方,所述散热片的突出部分延伸穿过所述封装加强件;
弹性粘合材料,位于所述散热片的所述主要部分与所述封装加强件之间;以及
热界面材料,位于所述散热片的所述突出部分与所述封装组件之间,所述热界面材料与所述弹性粘合材料不同。
2.根据权利要求1所述的使用集成电路封装的装置,其特征在于,其中所述热界面材料是液态金属或是金属接垫。
3.根据权利要求1所述的使用集成电路封装的装置,其特征在于,其中所述弹性粘合材料是石墨或是相变材料。
4.根据权利要求1所述的使用集成电路封装的装置,其特征在于,其中所述热界面材料沿着所述散热片的所述突出部分的底表面、沿着所述散热片的所述突出部分的侧壁、沿着所述封装组件的顶表面且沿着所述封装加强件的侧壁延伸。
5.根据权利要求1所述的使用集成电路封装的装置,其特征在于,更包括:
芯吸层,位于所述热界面材料与所述封装组件之间。
6.一种使用集成电路封装的装置,其特征在于,包括:
封装衬底;
封装组件,贴合至所述封装衬底,所述封装组件包括逻辑设备及内存装置;
第一弹性阻隔件,位于所述封装组件上,所述第一弹性阻隔件与所述内存装置交叠;
加强环,位于所述第一弹性阻隔件上,所述加强环与所述内存装置交叠;以及
开口,延伸穿过所述加强环及所述第一弹性阻隔件,所述开口在俯视图中设置于所述逻辑设备上方。
7.根据权利要求6所述的使用集成电路封装的装置,其特征在于,其中所述第一弹性阻隔件对其中所述加强环与所述封装组件交叠的区进行完全填充。
8.根据权利要求6所述的使用集成电路封装的装置,其特征在于,更包括:
第二弹性阻隔件,位于所述加强环上,所述开口延伸穿过所述第二弹性阻隔件。
9.根据权利要求6所述的使用集成电路封装的装置,其特征在于,更包括:
虚设金属化体,位于所述封装组件上,所述开口暴露出所述虚设金属化体。
10.根据权利要求6所述的使用集成电路封装的装置,其特征在于,其中所述加强环包括面对所述封装衬底的凹槽。
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