CN220933379U - Interlocking circuit and forklift control system - Google Patents
Interlocking circuit and forklift control system Download PDFInfo
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- CN220933379U CN220933379U CN202322927220.6U CN202322927220U CN220933379U CN 220933379 U CN220933379 U CN 220933379U CN 202322927220 U CN202322927220 U CN 202322927220U CN 220933379 U CN220933379 U CN 220933379U
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Abstract
The application discloses an interlocking circuit and a forklift control system, wherein the interlocking circuit is positioned in the control circuit and connected with an interlocking switch outside the control circuit, and is used for matching with the interlocking switch to lock the control circuit; the interlocking circuit specifically comprises a first transistor, a second transistor, a charging capacitor and four resistors; by adding the interlocking circuit in the control circuit, the control circuit is related to an external interlocking structure, so that the whole machine can be locked, the singlechip in the controller can be locked, and the motor error operation caused by the abnormality of the singlechip is effectively avoided.
Description
Technical Field
The application relates to the field of circuit design, in particular to an interlocking circuit and a forklift control system.
Background
In the existing forklift controller field, the interlock structure is typically only external to the controller. The controller is in a standby state, and the controller is in a standby state. If the singlechip is faulty, the controller may have a risk of malfunction.
Disclosure of utility model
In order to solve the technical problems, the application provides the interlocking circuit and the forklift control system, and the interlocking circuit is added in the control circuit to be related with an external interlocking structure, so that the whole machine can be locked, the singlechip in the controller can be locked, and the motor error operation caused by the abnormality of the singlechip is effectively avoided.
Specifically, the technical scheme of the application is as follows:
The application discloses an interlocking circuit, which is characterized in that the interlocking circuit is positioned in a control circuit and is connected with an interlocking switch outside the control circuit, and the interlocking circuit is used for matching with the interlocking switch to lock the control circuit;
The interlocking circuit specifically comprises a first transistor, a second transistor, a charging capacitor and four resistors;
the first end of the first transistor is connected with one end of a first resistor, the second end of the first transistor is connected with one end of a third resistor, and the third end of the first transistor is grounded;
The other end of the third resistor is connected with the first end of the second transistor, the second end of the second transistor is connected with an input power supply, and the third end of the second transistor is connected with the anode of the charging capacitor;
The positive electrode of the charging capacitor is also connected with the voltage input end of the working circuit, and the negative electrode of the charging capacitor is grounded;
One end of the second resistor is connected with the first end of the first transistor; the other end is grounded;
A fourth resistor is connected in parallel between the first end and the second end of the second transistor;
A first end of the interlocking switch is connected with the other end of the first resistor; a second terminal of the interlock switch is connected to a second terminal of the second transistor.
In some embodiments, the first transistor is an NPN transistor, the first transistor has a first terminal that is a base of the transistor, a second terminal that is a collector of the transistor, and a third terminal that is an emitter of the transistor;
or, the first transistor is an N-type field effect transistor, the first end of the first transistor is a field effect transistor gate, the second end is a field effect transistor drain, and the third end is a field effect transistor source.
In some embodiments, the second transistor is a PNP transistor, the first end of the second transistor is a transistor base, the second end is a transistor emitter, and the third end is a transistor collector;
Or the second transistor is a P-type field effect transistor, the first end of the second transistor is a field effect transistor grid electrode, the second end of the second transistor is a field effect transistor source electrode, and the third end of the second transistor is a field effect transistor drain electrode.
In some embodiments, when the interlock switch is in a closed state, an input power source passes through the first resistor through the interlock switch so that the first transistor is turned on with the second transistor;
After the second transistor is conducted, the input power supply charges the charging capacitor through the second transistor;
After the charging capacitor is charged, the voltage of the voltage input end of the working circuit rises, so that the working circuit works normally.
In some embodiments, the first transistor and the second transistor are turned off when the interlock switch is in an off state; the charging capacitor is not charged; and if the voltage input end of the working circuit is not provided with voltage, the working circuit is in a power-off state.
In some embodiments, the input power source has a voltage of 12V.
In some embodiments, the method comprises: interlocking the switch and the control circuit;
The interlocking switch is used for realizing the opening and locking of forklift equipment by switching on/off two states;
The control circuit comprises the interlock circuit of any of the embodiments described above; the control circuit is used for controlling the forklift equipment to enable the forklift equipment to normally operate;
the interlocking circuit is connected with the interlocking switch and is used for matching with the interlocking switch to lock the control circuit.
In some embodiments, the control circuit further comprises a working circuit; the voltage input end of the working circuit is connected with the interlocking circuit.
In some embodiments, the working circuit comprises a single chip microcomputer.
Compared with the prior art, the application has at least one of the following beneficial effects:
1. According to the application, the interlocking circuit is added in the controller circuit to be related with the external interlocking structure, so that the whole machine can be locked, the singlechip in the controller can be locked, and the motor error operation caused by the abnormality of the singlechip is effectively avoided. The potential of potential safety hazard caused by abnormal faults of the singlechip is avoided.
Drawings
The above features, technical features, advantages and implementation of the present application will be further described in the following description of preferred embodiments with reference to the accompanying drawings in a clear and easily understood manner.
FIG. 1 is a circuit diagram of one embodiment of an interlock circuit of the present application;
Fig. 2 is a circuit diagram of another embodiment of an interlock circuit of the present application.
Detailed Description
In the following description, for purposes of explanation and not limitation, specific details are set forth such as the particular system architecture, techniques, etc., in order to provide a thorough understanding of the embodiments of the present application. It will be apparent, however, to one skilled in the art that the present application may be practiced in other embodiments that depart from these specific details. In other instances, detailed descriptions of well-known systems, devices, and circuits are omitted so as not to obscure the description of the present application with unnecessary detail.
It should be understood that the terms "comprises" and/or "comprising," when used in this specification and the appended claims, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.
For simplicity of the drawing, only the parts relevant to the utility model are schematically shown in each drawing, and they do not represent the actual structure thereof as a product. Additionally, in order to simplify the drawing for ease of understanding, components having the same structure or function in some of the drawings are shown schematically with only one of them, or only one of them is labeled. Herein, "a" means not only "only this one" but also "more than one" case.
It should be further understood that the term "and/or" as used in the present specification and the appended claims refers to any and all possible combinations of one or more of the associated listed items, and includes such combinations.
In this context, it should be noted that the terms "mounted," "connected," and "connected" are to be construed broadly, and may be, for example, fixedly connected, detachably connected, or integrally connected, unless explicitly stated or limited otherwise; can be mechanically or electrically connected; can be directly connected or indirectly connected through an intermediate medium, and can be communication between two elements. The specific meaning of the above terms in the present application will be understood in specific cases by those of ordinary skill in the art.
In addition, in the description of the present application, the terms "first," "second," and the like are used merely to distinguish between descriptions and are not to be construed as indicating or implying relative importance.
In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the following description will explain the specific embodiments of the present application with reference to the accompanying drawings. It is evident that the drawings in the following description are only examples of the application, from which other drawings and other embodiments can be obtained by a person skilled in the art without inventive effort.
An interlock circuit is an electronic circuit that can interlock and unlock the circuit by a change in a control signal in the circuit. In the existing forklift controller field, the interlock structure is typically only external to the controller. The controller is in a standby state, and the controller is in a standby state. If the singlechip is faulty, the controller may have a risk of malfunction.
According to the interlocking circuit and the forklift control system disclosed by the application, the interlocking circuit is added in the control circuit to be related with the external interlocking structure, so that the whole forklift can be locked, the singlechip in the controller can be locked, and the motor error operation caused by the abnormality of the singlechip is effectively avoided.
More preferably, the interlocking circuit is positioned in the control circuit and is connected with the interlocking switch outside the control circuit, and is used for matching with the interlocking switch to lock the control circuit. The interlocking in the electrical control is mainly arranged for ensuring the safe operation of the electrical appliance.
The application provides an embodiment of an interlocking circuit, which specifically comprises a first transistor, a second transistor, a charging capacitor and four resistors.
The first end of the first transistor is connected with one end of the first resistor, the second end of the first transistor is connected with one end of the third resistor, and the third end of the first transistor is grounded.
The other end of the third resistor is connected with the first end of the second transistor, the second end of the second transistor is connected with an input power supply, and the third end of the second transistor is connected with the anode of the charging capacitor.
The positive pole of charging capacitor still connects working circuit voltage input, charging capacitor's negative pole ground connection.
One end of the second resistor is connected with the first end of the first transistor. The other end is grounded.
A fourth resistor is connected in parallel between the first and second terminals of the second transistor.
The first end of the interlocking switch is connected with the other end of the first resistor. A second terminal of the interlock switch is connected to a second terminal of the second transistor.
The first implementation manner of the interlock circuit provided in this embodiment is as follows: referring to fig. 1 of the specification, the first transistor is an NPN transistor, a first end of the first transistor is a base of the transistor, a second end of the first transistor is a collector of the transistor, and a third end of the first transistor is an emitter of the transistor.
The second transistor is a PNP triode, the first end of the second transistor is a triode base electrode, the second end of the second transistor is a triode emitter electrode, and the third end of the second transistor is a triode collector electrode.
Specifically, the interlocking circuit specifically includes an NPN triode Q1, a PNP triode Q2, a charging capacitor C1, and resistors R1, R2, R3, and R4.
The base of NPN type triode Q1 connects one end of first resistance R1, NPN type triode Q1's collecting electrode connects one end of third resistance R3, NPN type triode Q1's projecting pole ground.
The other end of the third resistor R3 is connected with the base electrode of the PNP type triode Q2, the emitter electrode of the PNP type triode Q2 is connected with an input power supply, and the collector electrode of the PNP type triode Q2 is connected with the positive electrode of the charging capacitor C1.
The positive electrode of the charging capacitor C1 is also connected with the voltage input end PVDD of the working circuit, and the negative electrode of the charging capacitor C1 is grounded.
One end of the second resistor R2 is connected with the base electrode of the NPN triode Q1. The other end is grounded.
The fourth resistor R4 is connected in parallel between the base and the emitter of the PNP triode Q2.
The first end of the interlocking switch is connected with the other end of the first resistor R1. And a second end of the interlocking switch is connected with the emitter of the PNP triode Q2.
More preferably, when the interlock switch is in a closed state, the input power passes through the first resistor R1 by the interlock switch, so that the NPN transistor Q1 and the PNP transistor Q2 are turned on. After the PNP transistor Q2 is turned on, the input power source charges the charging capacitor C1 through the PNP transistor Q2. After the charging capacitor C1 is charged, the voltage of the voltage input end PVDD of the working circuit rises, so that the working circuit works normally.
When the interlock switch is in an off state, the NPN transistor Q1 and the PNP transistor Q2 are turned off. The charging capacitor C1 is not charged. And if the voltage input end PVDD of the working circuit is not provided with voltage, the working circuit is in a power-off state.
Referring to fig. 2 of the specification, the first transistor is an N-type field effect transistor, the first end of the first transistor is a field effect transistor gate, the second end is a field effect transistor drain, and the third end is a field effect transistor source.
The second transistor is a P-type field effect transistor, the first end of the second transistor is a field effect transistor grid electrode, the second end of the second transistor is a field effect transistor source electrode, and the third end of the second transistor is a field effect transistor drain electrode.
Specifically, the interlocking circuit specifically includes an N-type field effect transistor Q1, a P-type field effect transistor Q2, a charging capacitor C1, and resistors R1, R2, R3, and R4.
The grid electrode of the N-type field effect tube Q1 is connected with one end of the first resistor R1, the drain electrode of the N-type field effect tube Q1 is connected with one end of the third resistor R3, and the source electrode of the N-type field effect tube Q1 is grounded.
The other end of the third resistor R3 is connected with the grid electrode of the P-type field effect tube Q2, the source electrode of the P-type field effect tube Q2 is connected with an input power supply, and the drain electrode of the P-type field effect tube Q2 is connected with the positive electrode of the charging capacitor C1.
The positive electrode of the charging capacitor C1 is also connected with the voltage input end PVDD of the working circuit, and the negative electrode of the charging capacitor C1 is grounded.
One end of the second resistor R2 is connected with the grid electrode of the N-type field effect transistor Q1. The other end is grounded.
The fourth resistor R4 is connected in parallel between the gate and the source of the P-type field effect transistor Q2.
The first end of the interlocking switch is connected with the other end of the first resistor R1. And the second end of the interlocking switch is connected with the source electrode of the P-type field effect transistor Q2.
Specifically, body diodes (parasitic diodes) are present in the N-type field effect transistor Q1 and the P-type field effect transistor Q2.
More preferably, when the interlock switch is in a closed state, the input power passes through the first resistor through the interlock switch, so that the N-type field effect transistor Q1 and the P-type field effect transistor Q2 are conducted. After the P-type field effect transistor Q2 is turned on, the input power source charges the charging capacitor C1 through the P-type field effect transistor Q2. After the charging capacitor C1 is charged, the voltage of the voltage input end PVDD of the working circuit rises, so that the working circuit works normally.
When the interlocking switch is in an off state, the N-type field effect transistor Q1 and the P-type field effect transistor Q2 are cut off. The charging capacitor C1 is not charged. And if the voltage input end PVDD of the working circuit is not provided with voltage, the working circuit is in a power-off state.
In a third implementation manner of the interlock circuit provided in this embodiment, the first transistor is an NPN transistor, a first end of the first transistor is a base of the transistor, a second end of the first transistor is a collector of the transistor, and a third end of the first transistor is an emitter of the transistor.
The second transistor is a P-type field effect transistor, the first end of the second transistor is a field effect transistor grid electrode, the second end of the second transistor is a field effect transistor source electrode, and the third end of the second transistor is a field effect transistor drain electrode.
Specifically, the interlocking circuit specifically comprises an NPN triode, a P-type field effect transistor, a charging capacitor and four resistors.
The base electrode of the NPN type triode is connected with one end of the first resistor, the collector electrode of the NPN type triode is connected with one end of the third resistor, and the emitter electrode of the NPN type triode is grounded.
The other end of the third resistor is connected with the grid electrode of the P-type field effect transistor, the source electrode of the P-type field effect transistor is connected with an input power supply, and the drain electrode of the P-type field effect transistor is connected with the anode of the charging capacitor.
The positive pole of charging capacitor still connects working circuit voltage input, charging capacitor's negative pole ground connection.
One end of the second resistor is connected with the base electrode of the NPN triode. The other end is grounded.
And the fourth resistor is connected in parallel between the grid electrode and the source electrode of the P-type field effect transistor.
The first end of the interlocking switch is connected with the other end of the first resistor. And the second end of the interlocking switch is connected with the source electrode of the P-type field effect transistor.
More preferably, when the interlock switch is in a closed state, the input power passes through the first resistor through the interlock switch, so that the NPN triode and the P-type field effect tube are conducted. After the P-type field effect transistor is conducted, the input power supply charges the charging capacitor through the P-type field effect transistor. After the charging capacitor is charged, the voltage of the voltage input end of the working circuit rises, so that the working circuit works normally.
And when the interlocking switch is in an off state, the NPN triode and the P-type field effect tube are cut off. The charging capacitor is not charged. And if the voltage input end of the working circuit is not provided with voltage, the working circuit is in a power-off state.
In a fourth implementation manner of the interlock circuit provided in this embodiment, the first transistor is an N-type field effect transistor, a first end of the first transistor is a field effect transistor gate, a second end is a field effect transistor drain, and a third end is a field effect transistor source.
The second transistor is a PNP triode, the first end of the second transistor is a triode base electrode, the second end of the second transistor is a triode emitter electrode, and the third end of the second transistor is a triode collector electrode.
Specifically, the interlocking circuit specifically comprises an N-type field effect transistor, a PNP triode, a charging capacitor and four resistors.
The grid electrode of the N-type field effect tube is connected with one end of the first resistor, the drain electrode of the N-type field effect tube is connected with one end of the third resistor, and the source electrode of the N-type field effect tube is grounded.
The other end of the third resistor is connected with the base electrode of the PNP type triode, the emitting electrode of the PNP type triode is connected with an input power supply, and the collecting electrode of the PNP type triode is connected with the anode of the charging capacitor.
The positive pole of charging capacitor still connects working circuit voltage input, charging capacitor's negative pole ground connection.
One end of the second resistor is connected with the grid electrode of the N-type field effect transistor. The other end is grounded.
And the fourth resistor is connected in parallel between the base electrode and the emitter electrode of the PNP triode.
The first end of the interlocking switch is connected with the other end of the first resistor. And the second end of the interlocking switch is connected with the emitter of the PNP triode.
More preferably, when the interlock switch is in a closed state, the input power passes through the first resistor through the interlock switch, so that the N-type field effect transistor and the PNP triode are conducted. After the PNP triode is conducted, the input power supply charges the charging capacitor through the PNP triode. After the charging capacitor is charged, the voltage of the voltage input end of the working circuit rises, so that the working circuit works normally.
And when the interlocking switch is in an off state, the N-type field effect transistor and the PNP triode are cut off. The charging capacitor is not charged. And if the voltage input end of the working circuit is not provided with voltage, the working circuit is in a power-off state.
In another embodiment of the interlock circuit provided by the present application, on the basis of any one of the foregoing embodiments, the voltage of the input power source is 12V. Specifically, taking the first implementation manner in the foregoing embodiment as an example, reference is made to fig. 1 of the specification, as shown in fig. 1: the interlock circuit is composed of two transistors, a capacitor and four resistors.
Wherein 12V is the power supply voltage, PVDD is the input voltage of the singlechip power supply chip, Q1 is an NPN triode, Q2 is a PNP triode, and the interlocking switch is in interlocking connection with the outside. The 12V power supply voltage is important, and the general interlocking circuit cannot be used in a low-voltage circuit, but only in the forklift control scene.
The working principle is as follows: when the interlock switch is in an off state, current passes through R1, and Q1 and Q2 are conducted. C1 is charged by 12V power supply current through Q2, PVDD voltage rises, a singlechip power supply chip works, and a circuit operates normally. When the external interlocking function of the forklift is started, the internal interlocking switch is disconnected, Q1 and Q2 are cut off, therefore, C1 is not charged, PVDD has no voltage, and the singlechip is in a power-off state.
Specifically, the 12V power supply voltage is obtained empirically by the relevant staff, and only this specific voltage data is set in the present embodiment. In other implementations of this embodiment, the magnitude of the voltage of the input power source may be set autonomously and may vary with the power level of the circuit. The interlocking circuit can be applied to other industrial fields.
Based on the same technical conception, the application also discloses a forklift control system, which comprises: interlocking the switch and the control circuit.
The interlocking switch is used for realizing the opening and locking of the forklift equipment by switching the on/off states.
The control circuit includes an interlock circuit as described in any of the embodiments above. The control circuit is used for controlling the forklift equipment to enable the forklift equipment to normally operate.
The interlocking circuit is connected with the interlocking switch and is used for matching with the interlocking switch to lock the control circuit.
The other embodiment of the forklift control system provided by the application is characterized in that the control circuit further comprises a working circuit. The voltage input end of the working circuit is connected with the interlocking circuit. In one implementation of this embodiment, the working circuit includes a single-chip microcomputer.
In another implementation of this embodiment, the working circuit includes an enabling chip or a micro control unit.
The interlocking circuit and the forklift control system have the same technical conception, and the technical details of the two embodiments are mutually applicable, so that repetition is reduced, and the description is omitted.
It will be apparent to those skilled in the art that the above-described program modules are only illustrated in the division of the above-described program modules for convenience and brevity, and that in practical applications, the above-described functional allocation may be performed by different program modules, i.e., the internal structure of the apparatus is divided into different program units or modules, to perform all or part of the above-described functions. The program modules in the embodiments may be integrated in one processing unit, or each unit may exist alone physically, or two or more units may be integrated in one processing unit, where the integrated units may be implemented in a form of hardware or in a form of a software program unit. In addition, the specific names of the program modules are also only for distinguishing from each other, and are not used to limit the protection scope of the present application.
In the foregoing embodiments, the descriptions of the embodiments are focused on, and the parts of a certain embodiment that are not described or depicted in detail may be referred to in the related descriptions of other embodiments.
Those of ordinary skill in the art will appreciate that the various illustrative elements and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware, or combinations of computer software and electronic hardware. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the solution. Those skilled in the art may use different implementations of the described functionality for each particular application, but such implementations should not be considered to be beyond the scope of the present application.
In the embodiments provided in the present application, it should be understood that the disclosed apparatus and method may be implemented in other manners. The above-described embodiments of the apparatus are exemplary only, and exemplary, the division of the modules or units is merely a logical function division, and there may be additional divisions in actual implementation, exemplary, multiple units or components may be combined or integrated into another system, or some features may be omitted, or not performed. Alternatively, the coupling or direct coupling or communication connection shown or discussed may be an indirect coupling or communication connection via interfaces, devices or units, which may be in electrical, mechanical or other forms.
The units described as separate units may or may not be physically separate, and units shown as units may or may not be physical units, may be located in one place, or may be distributed over a plurality of network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.
In addition, each functional unit in the embodiments of the present application may be integrated in one processing unit, or each unit may exist alone physically, or two or more units may be integrated in one unit. The integrated units may be implemented in hardware or in software functional units.
While preferred embodiments of the present application have been described, additional variations and modifications in those embodiments may occur to those skilled in the art once they learn of the basic inventive concepts. It is therefore intended that the following claims be interpreted as including the preferred embodiments and all such alterations and modifications as fall within the scope of the application.
It will be apparent to those skilled in the art that various modifications and variations can be made to the present application without departing from the spirit or scope of the application. Thus, it is intended that the present application also include such modifications and alterations insofar as they come within the scope of the appended claims or the equivalents thereof.
Claims (9)
1. An interlocking circuit is characterized in that the interlocking circuit is positioned in a control circuit and connected with an interlocking switch outside the control circuit, and is used for matching with the interlocking switch to lock the control circuit;
The interlocking circuit specifically comprises a first transistor, a second transistor, a charging capacitor and four resistors;
the first end of the first transistor is connected with one end of a first resistor, the second end of the first transistor is connected with one end of a third resistor, and the third end of the first transistor is grounded;
The other end of the third resistor is connected with the first end of the second transistor, the second end of the second transistor is connected with an input power supply, and the third end of the second transistor is connected with the anode of the charging capacitor;
The positive electrode of the charging capacitor is also connected with the voltage input end of the working circuit, and the negative electrode of the charging capacitor is grounded;
One end of the second resistor is connected with the first end of the first transistor; the other end is grounded;
A fourth resistor is connected in parallel between the first end and the second end of the second transistor;
A first end of the interlocking switch is connected with the other end of the first resistor; a second terminal of the interlock switch is connected to a second terminal of the second transistor.
2. An interlock circuit as recited in claim 1 wherein:
The first transistor is an NPN triode, the first end of the first transistor is a triode base electrode, the second end of the first transistor is a triode collector electrode, and the third end of the first transistor is a triode emitter electrode;
or, the first transistor is an N-type field effect transistor, the first end of the first transistor is a field effect transistor gate, the second end is a field effect transistor drain, and the third end is a field effect transistor source.
3. An interlock circuit as recited in claim 1 wherein:
the second transistor is a PNP triode, the first end of the second transistor is a triode base electrode, the second end of the second transistor is a triode emitter electrode, and the third end of the second transistor is a triode collector electrode;
Or the second transistor is a P-type field effect transistor, the first end of the second transistor is a field effect transistor grid electrode, the second end of the second transistor is a field effect transistor source electrode, and the third end of the second transistor is a field effect transistor drain electrode.
4. An interlock circuit as recited in claim 1 wherein: when the interlocking switch is in a closed state, an input power supply passes through the first resistor through the interlocking switch, so that the first transistor and the second transistor are conducted;
After the second transistor is conducted, the input power supply charges the charging capacitor through the second transistor;
After the charging capacitor is charged, the voltage of the voltage input end of the working circuit rises, so that the working circuit works normally.
5. An interlock circuit as recited in claim 1 wherein: when the interlock switch is in an off state, the first transistor and the second transistor are turned off; the charging capacitor is not charged; and if the voltage input end of the working circuit is not provided with voltage, the working circuit is in a power-off state.
6. An interlock circuit as recited in claim 1 wherein: the voltage of the input power supply is 12V.
7. A forklift control system, comprising: interlocking the switch and the control circuit;
The interlocking switch is used for realizing the opening and locking of forklift equipment by switching on/off two states;
The control circuit comprising the interlock circuit of any one of claims 1-6; the control circuit is used for controlling the forklift equipment to enable the forklift equipment to normally operate;
the interlocking circuit is connected with the interlocking switch and is used for matching with the interlocking switch to lock the control circuit.
8. The forklift control system of claim 7, wherein said control circuit further comprises an operating circuit; the voltage input end of the working circuit is connected with the interlocking circuit.
9. The forklift control system of claim 8, wherein said operating circuit comprises a single chip microcomputer.
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| Application Number | Priority Date | Filing Date | Title |
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| CN202322927220.6U CN220933379U (en) | 2023-10-31 | 2023-10-31 | Interlocking circuit and forklift control system |
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| CN202322927220.6U CN220933379U (en) | 2023-10-31 | 2023-10-31 | Interlocking circuit and forklift control system |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN118487492A (en) * | 2024-07-15 | 2024-08-13 | 深圳市格睿德电气有限公司 | Current sampling circuit applied to bidirectional converter and bidirectional converter |
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- 2023-10-31 CN CN202322927220.6U patent/CN220933379U/en active Active
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN118487492A (en) * | 2024-07-15 | 2024-08-13 | 深圳市格睿德电气有限公司 | Current sampling circuit applied to bidirectional converter and bidirectional converter |
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