CN220914217U

CN220914217U - Chip packaging structure and substrate thereof

Info

Publication number: CN220914217U
Application number: CN202322412638.3U
Authority: CN
Inventors: 刘焱
Original assignee: Lianhe Storage Technology Jiangsu Co ltd
Current assignee: Lianhe Storage Technology Jiangsu Co ltd
Priority date: 2023-09-05
Filing date: 2023-09-05
Publication date: 2024-05-07
Anticipated expiration: 2033-09-05

Abstract

The utility model discloses a substrate for a chip packaging structure, wherein a plurality of first signal wires are arranged on the substrate, and a grounding surface is arranged between two adjacent first signal wires. The utility model also discloses a chip packaging structure adopting the substrate. The utility model has the beneficial effects that the grounding surface is arranged among the plurality of first signal wires arranged on the substrate, and the grounding surface can shield electromagnetic interference between two adjacent first signal wires, so that the arrangement compactness of each electronic component arranged on the substrate is ensured, and the signal transmission quality of the signal wires is ensured.

Description

Chip packaging structure and substrate thereof

Technical Field

The present utility model relates to the field of chip packaging technologies, and in particular, to a chip packaging structure and a substrate thereof.

Background

Chips are important components for manufacturing electronic products. The chip is susceptible to external interference, and is thus generally constructed as a package structure. In general, the size of the chip package structure cannot be too large, so that a certain requirement is made on the compactness between each component in the chip package structure, and therefore, the space between the signal lines arranged on the substrate of the package structure is relatively close, and electromagnetic interference is easily generated between two adjacent signal lines.

Disclosure of utility model

The utility model mainly aims to provide a chip packaging structure and a substrate thereof, which aim to solve the problem of electromagnetic interference generated between adjacent signal wires.

In order to achieve the above objective, an aspect of the present utility model provides a substrate for a chip package structure, wherein a plurality of first signal lines are disposed on the substrate, a ground plane is disposed between two adjacent first signal lines, a plurality of wafer bumps are disposed on a side of the substrate, on which the first signal lines and the ground plane are disposed, the number of the plurality of wafer bumps corresponds to the plurality of first signal lines, and one wafer bump is electrically connected to one first signal line.

In some embodiments, a plurality of signal balls are disposed on a side of the substrate facing away from the wafer bumps, the number of the plurality of signal balls corresponds to the plurality of wafer bumps, and vias for electrical connection between the signal balls and the wafer bumps are formed on the substrate.

In some embodiments, a second signal line is further disposed on the substrate and connects the wafer bump and the signal ball through the hole.

In some embodiments, the linewidth of the first signal line is greater than 0.1mm and less than 0.3mm.

Another aspect of the present utility model provides a chip package structure, including a substrate and a sealing cover as described above, where the sealing cover is used to wrap a side of the substrate where the first signal line and the ground plane are disposed.

In some embodiments, the chip package structure further includes a chip disposed on the substrate, the chip being located on a side of the substrate where the first signal line and the ground plane are disposed, the chip being electrically connected to the first signal line and the ground plane, respectively.

The technical scheme of the utility model has the beneficial effects that:

The grounding surface is arranged among the plurality of first signal wires arranged on the substrate, and can shield electromagnetic interference between two adjacent first signal wires, so that the arrangement compactness of each electronic component arranged on the substrate is ensured, and the signal transmission quality of the signal wires is ensured.

Drawings

Fig. 1 is a schematic structural diagram of a chip package structure according to an embodiment of the utility model;

FIG. 2 is an exploded view of a chip package structure according to an embodiment of the present utility model;

Fig. 3 is a schematic diagram illustrating connection between a chip and a substrate according to an embodiment of the present utility model.

Reference numerals illustrate:

A substrate 100; a first signal line 110; a ground plane 120; wafer bumps 130; a signal ball 140; a sealing cap 200; chip 300.

The achievement of the objects, functional features and advantages of the present utility model will be further described with reference to the accompanying drawings, in conjunction with the embodiments.

Detailed Description

The following description of the embodiments of the present utility model will be made more clearly and fully with reference to the accompanying drawings, in which it is evident that the embodiments described are only some, but not all embodiments of the utility model. All other embodiments, which can be made by those skilled in the art based on the embodiments of the utility model without making any inventive effort, are intended to be within the scope of the utility model. Furthermore, the description of "first," "second," etc. in this disclosure is for descriptive purposes only and is not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated.

In view of the technical drawbacks of the related art, the present embodiment provides a chip package structure, as shown in fig. 1 and 2, which includes a substrate 100 and a sealing cover 200, wherein, as shown in fig. 3, a plurality of first signal lines 110 are disposed on the substrate 100, a ground plane 120 is disposed between two adjacent first signal lines 110, and the ground plane 120 is formed by copper plating or exposing a copper layer of the substrate 100. The sealing cover 200 is used to wrap one side of the substrate 100 where the first signal line 110 and the ground plane 120 are disposed, so as to form a package structure.

With continued reference to fig. 2, the chip package structure of the present embodiment further includes a chip 300 disposed on the substrate 100, where the chip 300 is one of a memory chip, a communication chip, a CPU chip, an analog chip, a computer chip, and a digital chip, but is not limited thereto. The chip 300 is located on one side of the substrate 100 where the first signal line 110 and the ground plane 120 are located, and the chip 300 is electrically connected to the first signal line 110 and the ground plane 120, respectively.

The beneficial effects of the present embodiment are that the ground plane 120 is disposed between the plurality of first signal lines 110 disposed on the substrate 100, and the ground plane 120 can shield electromagnetic interference between two adjacent first signal lines 110, so as to ensure the compactness of arrangement of each electronic component disposed on the substrate 100 and ensure the signal transmission quality of the signal lines.

Referring to fig. 2, a plurality of wafer bumps 130 are disposed on a side of the substrate 100 having the first signal lines 110 and the ground plane 120, the number of the plurality of wafer bumps 130 corresponds to the number of the plurality of first signal lines 110, and one wafer bump 130 is electrically connected to one first signal line 110, so as to form an electrical connection between the wafer bump 130 and the first signal line 110.

With continued reference to fig. 2, a plurality of signal balls 140 are disposed on a side of the substrate 100 facing away from the wafer bumps 130, the number of the plurality of signal balls 140 corresponds to the number of the plurality of wafer bumps 130, vias (not shown) for electrically connecting the signal balls 140 and the wafer bumps 130 are formed on the substrate 100, and second signal lines (not shown) for electrically connecting the wafer bumps 130 and the signal balls 140 through the vias are further disposed on the substrate 100, so that after the signal balls 140 are electrically connected with the electronic device, the electronic device is electrically connected with the chip 300, and the electronic device is controlled by the chip 300.

In some alternative examples, the line width of the first signal line 110 is greater than 0.1mm and less than 0.3mm. It should be noted that, if the line width of the first signal line 110 is smaller than 0.1mm, the impedance of the first signal line 110 is larger, which results in poor signal transmission, and the line width of the first signal line 110 is larger than 0.3mm, which requires a larger space for arrangement of the first signal line 110, thereby being unfavorable for miniaturization of the chip package structure.

The above description of the preferred embodiments of the present utility model should not be taken as limiting the scope of the utility model, but rather should be understood to cover all modifications, variations and adaptations of the present utility model using its general principles and the following detailed description and the accompanying drawings, or the direct/indirect application of the present utility model to other relevant arts and technologies.

Claims

1. The substrate for the chip packaging structure is characterized in that a plurality of first signal wires are arranged on the substrate, a grounding surface is arranged between two adjacent first signal wires, a plurality of wafer bumps are arranged on one side of the substrate, provided with the first signal wires and the grounding surface, of the substrate, the number of the wafer bumps corresponds to the first signal wires, and one wafer bump is electrically connected with one first signal wire.

2. The substrate of claim 1, wherein a plurality of signal balls are disposed on a side of the substrate facing away from the wafer bumps, the plurality of signal balls correspond to the plurality of wafer bumps, and a via hole for electrically connecting the signal balls and the wafer bumps is formed in the substrate.

3. The substrate of claim 2, further comprising a second signal line on the substrate connecting the wafer bump and the signal ball via the via.

4. A substrate according to any one of claims 1 to 3, wherein the line width of the first signal line is greater than 0.1mm and less than 0.3mm.

5. A chip package structure comprising the substrate according to any one of claims 1 to 4 and a sealing cover for wrapping a side of the substrate where the first signal line and the ground plane are provided.

6. The chip package structure of claim 5, further comprising a chip disposed on the substrate, the chip being located on a side of the substrate where the first signal line and the ground plane are disposed, the chip being electrically connected to the first signal line and the ground plane, respectively.