CN220913216U - Device electricity consumption monitoring circuit and chip testing system - Google Patents
Device electricity consumption monitoring circuit and chip testing system Download PDFInfo
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- CN220913216U CN220913216U CN202321088011.0U CN202321088011U CN220913216U CN 220913216 U CN220913216 U CN 220913216U CN 202321088011 U CN202321088011 U CN 202321088011U CN 220913216 U CN220913216 U CN 220913216U
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- 238000012544 monitoring process Methods 0.000 title claims abstract description 86
- 238000012360 testing method Methods 0.000 title claims abstract description 62
- 230000005611 electricity Effects 0.000 title claims abstract description 35
- 238000005070 sampling Methods 0.000 claims abstract description 61
- 238000001514 detection method Methods 0.000 claims abstract description 39
- 239000003990 capacitor Substances 0.000 claims description 13
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Abstract
The utility model discloses a device electricity consumption monitoring circuit and a chip testing system, wherein the device electricity consumption monitoring circuit comprises a main control unit and at least one detection unit, each detection unit is used for independently detecting a device, and the detection unit comprises a sampling load and a monitoring subunit; the sampling load is used for being connected in series with the power input end of the device; the monitoring subunit is electrically connected with the sampling load and the main control unit, and the monitoring subunit determines the power consumption data of the device by monitoring the voltages at two ends of the sampling load and combining the resistance value of the sampling load and sends the determined power consumption data to the main control unit. According to the technical scheme, the power consumption data of the chip is monitored in the chip testing process, so that the power consumption condition of the chip is obtained through testing, and the application grade of the chip can be distinguished according to the power consumption of the chip.
Description
Technical Field
The utility model relates to the field of chip testing equipment, in particular to a device electricity consumption monitoring circuit and a chip testing system.
Background
In the production of chips, after the packaging of the chips is completed, the chips are sent to a testing procedure for testing and verification so as to determine whether the chips are qualified or not.
Currently, a chip test scheme generally places a chip in a test socket to test whether each function of the chip is normal. Because different fields have different levels of power consumption requirements on the adopted chips, the current chip test scheme cannot acquire the power consumption data of the chips in real time and cannot acquire the power consumption condition of the chips in the test process, so that the application levels of the chips cannot be distinguished according to the power consumption of the chips.
Disclosure of utility model
The utility model provides a device electricity consumption monitoring circuit and a chip testing system, which aim to monitor the electricity consumption data of a chip in the chip testing process so as to obtain the power consumption condition of the chip by testing.
In order to achieve the above object, the device electricity consumption monitoring circuit provided by the present utility model includes a main control unit and at least one detection unit, each detection unit is used for separately detecting a device, and the detection unit includes:
the sampling load is used for being connected in series with the power input end of the device;
The monitoring subunit is electrically connected with the sampling load and the main control unit, and the monitoring subunit determines the electricity consumption data of the device by monitoring the voltage at two ends of the sampling load and combining the resistance value of the sampling load and sends the determined electricity consumption data to the main control unit.
In some embodiments, the master control unit includes at least one I2C bus, each of the I2C buses electrically connecting a plurality of the monitoring subunits.
In some embodiments, the monitor subunits have address pin sets, each of which has a different wiring.
In some embodiments, the monitoring subunit has a first differential input and a second differential input, the first differential input and the second differential input being electrically connected across the sampling load, respectively.
In some embodiments, the detection unit further comprises a filtering subunit electrically connecting the first differential input and the second differential input.
In some embodiments, the filtering subunit includes a first capacitor, a first resistor, and a second resistor, where one end of the first resistor is electrically connected to one end of the sampling load, the other end of the first resistor is electrically connected to one end of the first capacitor and the first differential input terminal, one end of the second resistor is electrically connected to the other end of the sampling load, and the other end of the second resistor is electrically connected to the other end of the first capacitor and the second differential input terminal.
In some embodiments, the monitoring subunit is a current detection chip, and a power supply pin of the current detection chip is connected to a power supply and grounded via a second capacitor.
The utility model also provides a chip test system which comprises at least one chip test seat and the device electricity monitoring circuit, wherein the sampling resistor of each detection unit is correspondingly connected in series with the power input end of one chip test seat.
In some embodiments, the main control unit is electrically connected to the corresponding chip test seat through signal interfaces corresponding to the chip test seats one by one, and each signal interface is used for receiving a test result signal output by the chip test seat.
When the technical scheme of the device electricity consumption monitoring circuit is applied to a chip test system, the sampling load of each detection unit is only required to be correspondingly connected in series with the power input end of each chip or chip test seat (namely, the sampling load of each detection unit is correspondingly connected in series with the power input end of one chip or chip test seat), so that the chip function test of the chip test system is not affected; when the chip test system starts the test, the chip test system monitors the power consumption data of the chip through the device power consumption monitoring circuit while performing the chip function test, so as to obtain the power consumption condition of the chip, and further, the application grade of the chip can be distinguished according to the power consumption condition of the chip.
Drawings
FIG. 1 is a schematic block diagram of an embodiment of an electrical monitoring circuit for a device according to the present utility model;
FIG. 2 is a schematic block diagram of a second embodiment of the device power consumption monitoring circuit of the present utility model;
FIG. 3 is a schematic diagram of a device power consumption monitoring circuit according to a third embodiment of the present utility model;
Fig. 4 is a circuit diagram of a fourth embodiment of the device power consumption monitoring circuit of the present utility model.
Detailed Description
The following description of the embodiments of the present utility model will be made clearly and fully with reference to the accompanying drawings, in which it is evident that the embodiments described are only some, but not all embodiments of the utility model. All other embodiments, which can be made by those skilled in the art based on the embodiments of the utility model without making any inventive effort, are intended to be within the scope of the utility model.
It should be noted that all directional indicators (such as up, down, left, right, front, and rear … …) in the embodiments of the present utility model are merely used to explain the relative positional relationship, movement, etc. between the components in a particular posture (as shown in the drawings), and if the particular posture is changed, the directional indicator is changed accordingly.
It will also be understood that when an element is referred to as being "mounted" or "disposed" on another element, it can be directly on the other element or intervening elements may also be present. When an element is referred to as being "connected" to another element, it can be directly connected to the other element or intervening elements may also be present.
Furthermore, the description of "first," "second," etc. in this disclosure is for descriptive purposes only and is not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include at least one such feature. In addition, the technical solutions of the embodiments may be combined with each other, but it is necessary to base that the technical solutions can be realized by those skilled in the art, and when the technical solutions are contradictory or cannot be realized, the combination of the technical solutions should be considered to be absent and not within the scope of protection claimed in the present utility model.
The utility model provides a device electricity consumption monitoring circuit which can be used for monitoring the electricity consumption data of a device in the device testing process so as to obtain the power consumption condition of the device. The device may be a chip, a chip test socket, a chip test device, or other types of electrical devices or products.
Referring to fig. 1, in the present embodiment, the device electricity monitoring circuit includes a main control unit 10 and at least one detection unit 20 (4 are taken as an example in fig. 1), each detection unit 20 being used to individually detect one device 30.
Wherein the detection unit 20 includes:
a sampling load 21 (e.g. a resistor), wherein the sampling load 21 is connected in series to the power input terminal Vin of the device 30, i.e. the power supply is electrically connected to the power input terminal Vin of the device 30 via the sampling load 21;
The monitoring subunit 22 is electrically connected with the sampling load 21 and the main control unit 10, and the monitoring subunit 22 determines the electricity consumption data of the device 30 by combining the resistance value of the sampling load 21 through monitoring the voltages at two ends of the sampling load 21 and sends the determined electricity consumption data to the main control unit 10.
In some embodiments, the power consumption data may include a power supply current of the device 30, i.e., a current at the power input Vin of the device 30 (equal to a current flowing through the sampling load 21), a power supply voltage of the device 30, i.e., a voltage at a terminal of the sampling load 21 connected to the device 30, and a power consumption of the device 30, and the monitoring subunit 22 may calculate the power consumption of the device 30.
In some embodiments, the power consumption data may also be a power supply current of the device 30 and a power supply voltage of the device 30, so that the main control unit 10 calculates the power consumption of the device 30 according to the power supply current and the power supply voltage of the device 30.
In some embodiments, the power consumption data may also be power consumption including only device 30.
In some embodiments, the power consumption data may also include only the voltages at two ends of the sampling load 21 and the resistance value of the sampling load 21, that is, the monitoring subunit 22 directly sends the voltages and the resistance values at two ends of the sampling load 21 collected by monitoring to the main control unit 10, so that the main control unit 10 calculates the power consumption of the monitoring subunit 22 according to the voltages and the resistance values at two ends of the sampling load 21.
The device electricity consumption monitoring circuit of this embodiment may be that the monitoring subunit 22 actively sends the determined electricity consumption data to the main control unit 10 in real time, or that the main control unit 10 actively acquires the real-time electricity consumption data from the monitoring subunit 22.
The device electricity consumption monitoring circuit of the embodiment can configure the number of the detection units 20 according to the number of the devices 30 to be detected, thereby meeting the requirements of different numbers of the devices 30 to be detected.
When the device electricity consumption monitoring circuit of the embodiment is applied to a chip test system, the sampling load 21 of each detection unit 20 is only required to be correspondingly connected in series with the power input end Vin of each chip or chip test seat (namely, the sampling load 21 of each detection unit 20 is correspondingly connected in series with the power input end Vin of one chip or chip test seat), so that no influence is generated on the chip function test of the chip test system; when the chip test system starts the test, the chip test system monitors the power consumption data of the chip through the device power consumption monitoring circuit while performing the chip function test, so as to obtain the power consumption condition of the chip, and further, the application grade of the chip can be distinguished according to the power consumption condition of the chip.
In some embodiments, the monitoring subunit 22 in combination with the resistance value of the sampling load 21 determines the power usage data of the device 30, including:
Step S1, calculating the current flowing through the sampling load 21 according to the voltage difference between two ends of the sampling load 21 and the resistance value of the sampling load 21;
In step S2, the power consumption of the device 30 is calculated based on the voltage at the end of the sampling load 21 connected to the device 30 and the current flowing through the sampling load 21.
After the monitoring subunit 22 obtains the voltages at the two ends of the sampling load 21, the voltages at the two ends of the sampling load 21 are subtracted to obtain the voltage difference at the two ends of the load, and then the voltage difference at the two ends of the load is divided by the resistance value of the sampling load 21, so that the current flowing through the sampling load 21, namely the supply current of the device 30, is obtained. Then, the voltage at the end of the load connected to the device 30 (i.e., the supply voltage of the device 30) is multiplied by the current flowing through the sampling load 21, thereby obtaining the power consumption (i.e., the power) of the device 30.
In some embodiments, the master unit 10 includes at least one I2C bus 11, each I2C bus 11 being electrically connected to a plurality of monitoring subunits 22 (e.g., 4 monitoring subunits 22 are electrically connected to each I2C bus 11), i.e., each monitoring subunit 22 communicates with the master unit 10 via the I2C bus 11 and transmits electricity data to the master unit 10 via the I2C bus 11. The main control unit 10 of the present embodiment communicates with a plurality of monitoring subunits 22 through one I2C bus 11, so that the number of interfaces and the number of lines of the main control unit 10 are reduced, and the complexity of wiring lines is simplified.
In some embodiments, the IDs of the monitoring subunits 22 are different, so as to distinguish the monitoring subunits 22, and the master control unit 10 distinguishes the electricity consumption data of the monitoring subunits 22 according to the different IDs, so as to realize electricity consumption monitoring of the devices 30.
Referring to fig. 2, alternatively, the ID may be the address of the monitoring subunit 22, the monitoring subunit 22 has an address pin set D, and the connections of the address pin set D of each monitoring subunit 22 are different, so that the addresses (i.e., IDs) of the respective monitoring subunits 22 are different. For example, the monitor subunit 22 has two address pins, the wiring combination of which has: 1. both address pins are connected with high level; 2. both address pins are connected with low level; 3. the first address pin is connected with a high level, and the second address pin is connected with a low level; 4, the first address pin is connected with a low level, and the second address pin is connected with a high level; i.e. two address pins may form 4 different addresses, which may be distributed to 4 monitoring subunits 22 for use.
Of course, in some embodiments, the main control unit 10 may be separately wired corresponding to each monitoring subunit 22, that is, each monitoring subunit 22 is connected to the main control unit 10 through a separate communication line.
Referring to fig. 2 and 3 (which illustrate one detection unit 20), in some embodiments, the monitoring subunit 22 has a first differential input v+ and a second differential input V-, where the first differential input v+ and the second differential input V-are electrically connected to two ends of the sampling load 21, respectively. The monitoring subunit 22 obtains the voltage across the sampling load 21 and the difference between the voltages across the sampling load 21 through the first differential input terminal v+ and the second differential input terminal V-, respectively. In the embodiment, the monitoring subunit 22 monitors the voltages at two ends of the sampling load 21 respectively by adopting a differential signal mode, so that the immunity of the monitoring subunit 22 to external electromagnetic interference is greatly reduced, the influence of the external electromagnetic interference on the monitoring signal is reduced, and the electricity consumption data obtained by the monitoring subunit 22 is more accurate.
In some embodiments, the detection unit 20 further comprises a filtering subunit 23, the filtering subunit 23 being electrically connected to the first differential input v+ and the second differential input V-. The interference noise signals of the first differential input end V+ and the second differential input end V-are filtered by the filtering sub-unit 23, so that the accuracy of the detection of the voltage at the two ends of the sampling load 21 by the monitoring sub-unit 22 is further improved, the accuracy of the power consumption data obtained by the detection sub-unit is further improved, and the power consumption condition of the device 30 is more accurately measured.
Referring to fig. 3, in some embodiments, the filtering subunit 23 includes a first capacitor C1, a first resistor R1, and a second resistor R2, where one end of the first resistor R1 is electrically connected to one end of the sampling load 21, the other end of the first resistor R1 is electrically connected to one end of the first capacitor C1 and the first differential input terminal v+, one end of the second resistor R2 is electrically connected to the other end of the sampling load 21, and the other end of the second resistor R2 is electrically connected to the other end of the first capacitor C1 and the second differential input terminal V-. The first resistor R1, the first capacitor C1 and the second resistor R2 form a filter circuit for filtering interference noise, wherein the resistance values of the first resistor R1 and the second resistor R2 are equal.
In some embodiments, the monitoring subunit 22 is a current detection chip U1, the power pin VS of the current detection chip U1 is connected to a power source, and is grounded via a second capacitor C2, so as to maintain the stability of the power source of the current detection chip U1.
Referring to fig. 4, IN a specific embodiment, the current detecting chip U1 may be a current management chip (e.g., INA219 BIDR), the first differential input terminal v+ and the second differential input terminal V-are in+ and IN-input pins of the current detecting chip U1, respectively, and the main control unit 10 may be a single chip microcomputer. The current passes through the sampling load 21, a voltage drop is formed at two ends of the sampling load 21, the current detection chip U1 simultaneously measures the differential voltage between the IN+ and IN-input pins and the voltage of the IN-input pin, the resistance value of the sampling load 21 is known, the current detection chip U1 calculates the current actually flowing through the sampling resistor, calculates power consumption and other power consumption data of the device 30, and stores the power consumption data of the device 30 into an internal register. The current detection chip U1 uses an I2C communication protocol, two data lines (SDA and SCL) control communication with the singlechip, and electricity consumption data are output to the singlechip through an SDA serial data bus to realize communication with the singlechip. The current detection chip U1 is provided with two groups of address pins A0 and A1, each current detection chip U1 can be defined as different ICs by setting different values (namely electrically connecting different level signals), and the singlechip is communicated with 4 current detection chips U1 through one I2C bus 11 according to different addresses, so that the power consumption monitoring of 4 groups of devices 30 is realized.
In some embodiments, the sampling load 21 may have a resistance of 0.25Ω, the first and second capacitances C1 and C2 may be capacitances of 0.1uF, and the first and second resistances R1 and R2 may be resistances of 0 Ω.
The utility model further provides a chip test system, which comprises at least one chip test seat and a device electricity consumption monitoring circuit, wherein the specific structure of the device electricity consumption monitoring circuit refers to the embodiment, and the chip test system adopts all the technical schemes of all the embodiments of the device electricity consumption monitoring circuit, so that the chip test system at least has all the beneficial effects brought by the technical schemes of the embodiments, and the detailed description is omitted. The sampling resistor of each detection unit of the device electricity consumption monitoring circuit is correspondingly connected in series with the power input end of one chip test seat.
In some embodiments, the main control unit is electrically connected to the corresponding chip test seat through signal interfaces corresponding to the chip test seat one by one, and each signal interface is used for receiving the test result signal output by the chip test seat. Therefore, the main control unit also acquires a plurality of chip test results, and the test result of each chip and the power consumption condition can be fed back to the server or the upper computer.
The above description of the preferred embodiments of the present utility model should not be taken as limiting the scope of the utility model, but rather should be understood to cover all modifications, variations and adaptations of the present utility model using its general principles and the following detailed description and the accompanying drawings, or the direct/indirect application of the present utility model to other relevant arts and technologies.
Claims (9)
1. A device electricity consumption monitoring circuit, comprising a main control unit and at least one detection unit, each detection unit being used for individually detecting a device, the detection unit comprising:
the sampling load is used for being connected in series with the power input end of the device;
The monitoring subunit is electrically connected with the sampling load and the main control unit, and the monitoring subunit determines the electricity consumption data of the device by monitoring the voltage at two ends of the sampling load and combining the resistance value of the sampling load and sends the determined electricity consumption data to the main control unit.
2. The device power consumption monitoring circuit of claim 1, wherein the master control unit comprises at least one I2C bus, each of the I2C buses electrically connecting a plurality of the monitoring subunits.
3. The device power up monitoring circuit of claim 2, wherein the monitoring subunits have address pin sets, and wherein the connections of the address pin sets of each monitoring subunit are different.
4. The device power consumption monitoring circuit of claim 1, wherein the monitoring subunit has a first differential input and a second differential input, the first differential input and the second differential input being electrically connected to two ends of the sampling load, respectively.
5. The device power usage monitoring circuit of claim 4, wherein the detection unit further comprises a filtering subunit electrically connecting the first differential input and the second differential input.
6. The electrical device monitoring circuit of claim 5, wherein the filter subunit comprises a first capacitor, a first resistor, and a second resistor, one end of the first resistor is electrically connected to one end of the sampling load, the other end of the first resistor is electrically connected to one end of the first capacitor and the first differential input terminal, one end of the second resistor is electrically connected to the other end of the sampling load, and the other end of the second resistor is electrically connected to the other end of the first capacitor and the second differential input terminal.
7. The device power consumption monitoring circuit of claim 6, wherein the monitoring subunit is a current detection chip, and a power supply pin of the current detection chip is connected to a power supply and is grounded via a second capacitor.
8. A chip testing system, comprising at least one chip testing seat and the device electricity monitoring circuit according to any one of claims 1-7, wherein the sampling resistor of each detection unit is correspondingly connected in series with the power input end of one chip testing seat.
9. The system of claim 8, wherein the main control unit is in one-to-one correspondence with the chip test sockets, and each signal interface is electrically connected with the corresponding chip test socket and is configured to receive a test result signal output by the chip test socket.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202321088011.0U CN220913216U (en) | 2023-05-08 | 2023-05-08 | Device electricity consumption monitoring circuit and chip testing system |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202321088011.0U CN220913216U (en) | 2023-05-08 | 2023-05-08 | Device electricity consumption monitoring circuit and chip testing system |
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| Publication Number | Publication Date |
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| CN220913216U true CN220913216U (en) | 2024-05-07 |
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| CN202321088011.0U Active CN220913216U (en) | 2023-05-08 | 2023-05-08 | Device electricity consumption monitoring circuit and chip testing system |
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| CN (1) | CN220913216U (en) |
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- 2023-05-08 CN CN202321088011.0U patent/CN220913216U/en active Active
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