CN220894696U

CN220894696U - Display panel and display device

Info

Publication number: CN220894696U
Application number: CN202321986062.5U
Authority: CN
Inventors: 陈盈惠; 史欣坪; 陈岗; 朱伟; 李喻
Original assignee: BOE Technology Group Co Ltd; Beijing BOE Technology Development Co Ltd; Chengdu BOE Display Technology Co Ltd
Current assignee: BOE Technology Group Co Ltd; Beijing BOE Technology Development Co Ltd; Chengdu BOE Display Technology Co Ltd
Priority date: 2023-07-26
Filing date: 2023-07-26
Publication date: 2024-05-03
Anticipated expiration: 2033-07-26

Abstract

The present disclosure provides a display panel and a display device, including: the array substrate includes: the first substrate comprises a common line arranged on the first substrate, an insulating layer arranged on one side of the common line away from the first substrate, and a switching layer arranged on one side of the insulating layer away from the first substrate; the array substrate is provided with a display area and a frame glue area surrounding the display area, the orthographic projection of the common line on the first substrate and the orthographic projection of the switching layer on the first substrate are arranged in the frame glue area, the insulating layer in the frame glue area is provided with a plurality of first via hole groups surrounding the display area, each of the plurality of first via holes comprises a plurality of first via holes arranged at intervals, and the first via holes in the two adjacent first via hole groups are arranged in a staggered manner; the switching layer is connected with the common line through a plurality of first via groups; the opposite substrate disposed opposite to the array substrate includes: the second substrate is arranged on the transparent public electrode on the side, facing the first substrate, of the second substrate, and the transparent public electrode is connected with the switching layer.

Description

Display panel and display device

Technical Field

The disclosure relates to the field of display technologies, and in particular, to a display panel and a display device.

Background

In displays such as Liquid crystal displays (Liquid CRYSTAL DISPLAY, LCD) and Organic Light-Emitting diodes (OLEDs), a plurality of pixel cells are generally included. Each pixel unit may include: a plurality of subpixels of different colors. The color image is displayed by mixing the colors to be displayed by controlling the brightness corresponding to each sub-pixel.

Disclosure of utility model

The display panel provided by the embodiment of the disclosure comprises:

An array substrate, comprising: a first substrate, a common line arranged on the first substrate, an insulating layer arranged on one side of the common line away from the first substrate, and a switching layer arranged on one side of the insulating layer away from the first substrate; the array substrate is provided with a display area and a frame glue area surrounding the display area, the orthographic projection of the common line on the first substrate and the orthographic projection of the transfer layer on the first substrate are arranged in the frame glue area, the insulating layer in the frame glue area is provided with a plurality of first via hole groups surrounding the display area, each of the plurality of first via hole groups comprises a plurality of first via holes arranged at intervals, and the first via holes in two adjacent first via hole groups are arranged in a staggered manner; the switching layer is connected with the common line through the first via groups;

An opposite substrate disposed opposite to the array substrate, the opposite substrate comprising: the second substrate is arranged on the transparent common electrode on one side of the second substrate facing the first substrate, and the transparent common electrode is connected with the switching layer.

In some possible embodiments, the frame glue area includes: the first sub-frame glue area and the second sub-frame glue area are oppositely arranged along the first direction, and the third sub-frame glue area and the fourth sub-frame glue area are oppositely arranged along the second direction; the fourth sub-frame glue area is provided with a fan-out area;

The common line comprises a first common line, and the orthographic projection of the first common line on the first substrate extends from one side of the fourth sub-frame glue area close to the first sub-frame glue area to one side of the third sub-frame glue area close to the first sub-frame glue area; and/or, the orthographic projection of the first common line on the first substrate extends from one side of the fourth sub-frame glue area close to the first sub-frame glue area to one side of the fourth sub-frame glue area close to the second sub-frame glue area;

The transfer layer comprises: the first sub-transfer layer, wherein, the first sub-frame glue area, the second sub-frame glue area and at least one sub-frame glue area in the third sub-frame glue area are provided with the first sub-transfer layer and the plurality of first via groups, and the first sub-transfer layer is connected with the first common line through the plurality of first via groups.

In some possible embodiments, the first sub-switching layer includes a plurality of first switching portions connected in sequence, the plurality of first switching portions extend along the second direction, and two adjacent first switching portions are arranged in a staggered manner; or alternatively

The first sub-switching layer comprises an elongated shape extending along the second direction.

In some possible embodiments, the fourth subframe glue area includes: the fan-out areas and the non-fan-out areas are arranged between two adjacent fan-out areas;

the common line includes a plurality of second common lines, and the transfer layer includes: the second common lines, the second sub-switching layers and the non-fan-out areas are in one-to-one correspondence, and the orthographic projection of the second common lines on the first substrate and the orthographic projection of the second sub-switching layers on the first substrate are arranged in the corresponding non-fan-out areas;

the non-fan-out region comprises a plurality of first via groups, wherein in the same non-fan-out region, the second sub-switching layer is connected with the second common line through the plurality of first via groups.

In some possible embodiments, the second sub-switching layer includes a plurality of second switching parts connected in sequence, where the plurality of second switching parts extend along the first direction, and two adjacent second switching parts are arranged in a staggered manner; or alternatively

The second sub-switching layer comprises an elongated shape extending along the first direction.

In some possible embodiments, the shape of the orthographic projection of the first via on the first substrate board includes a strip shape, and a long edge of the strip shape extends near an edge of the display area.

In some possible embodiments, when the plurality of first via groups are disposed in the first subframe glue area, the long strip extends along the second direction; and/or the number of the groups of groups,

When the plurality of first via groups are arranged in the second subframe glue area, the long edges of the strip extend in the second direction; and/or the number of the groups of groups,

When the plurality of first via groups are arranged in the third subframe glue area, the long edges of the strip extend along the first direction; and/or the number of the groups of groups,

When the plurality of first via groups are arranged in the fourth subframe glue area, the long edges of the strip extend in the first direction.

In some possible embodiments, the frame glue area further includes: the first frame glue corner region is arranged between the first sub frame glue region and the third sub frame glue region, and the second frame glue corner region is arranged between the second sub frame glue region and the third sub frame glue region;

the first frame glue corner region and at least one frame glue corner region of the second frame glue corner region are provided with the third sub-switching layer and a plurality of second through holes arranged at intervals, and the third sub-switching layer is connected with the first common line through the second through holes.

In some possible implementations, the plurality of second vias are arranged around the display area; and/or the number of the groups of groups,

The shape of the orthographic projection of the second via hole on the first substrate comprises: at least one of rectangular, circular, elliptical, and polygonal.

In some possible implementations, a plurality of third vias are further disposed in the subframe glue area where the plurality of first via groups are disposed, the plurality of third vias are disposed at intervals with the plurality of first vias, and the first sub-switching layer is further connected with the first common line through the plurality of third vias.

In some possible embodiments, the plurality of third vias is divided into a plurality of third via groups, each of the third via groups including a plurality of third vias; the plurality of third via groups are disposed around the display area.

In some possible embodiments, at least one third via group is disposed between two adjacent first via groups; and/or the number of the groups of groups,

At least one third via hole group is arranged on one side, away from the display area, of the first via hole groups; and/or the number of the groups of groups,

At least one third via group is arranged between the first via groups and the display area.

In some possible embodiments, one of the first via groups corresponds to one of the third via groups one by one, and at least one end of a first via in the first via group is provided with a corresponding one of the third via groups.

In some possible embodiments, the shape of the orthographic projection of the third via on the first substrate includes: at least one of rectangular, circular, elliptical, and polygonal.

The display device provided by the embodiment of the disclosure comprises the display panel.

Drawings

FIG. 1a is a schematic diagram of some structures of a display panel according to an embodiment of the disclosure;

FIG. 1b is a schematic view of another structure of a display panel according to an embodiment of the disclosure;

FIG. 1c is a schematic view of still other structures of a display panel according to an embodiment of the present disclosure;

FIG. 2a is a schematic view of another structure of a display panel according to an embodiment of the disclosure;

FIG. 2b is a schematic view of another structure of a display panel according to an embodiment of the disclosure;

FIG. 3 is a schematic view of still other structures of a display panel according to an embodiment of the disclosure;

FIG. 4 is a schematic view of still other structures of a display panel according to an embodiment of the present disclosure;

FIG. 5 is a schematic view of still other structures of a display panel according to an embodiment of the disclosure;

FIG. 6a is a schematic view of another structure of a display panel according to an embodiment of the disclosure;

Fig. 6b is a schematic cross-sectional structure view of the display panel shown in fig. 6a in the HH' direction;

FIG. 7 is a schematic view of still other structures of a display panel according to an embodiment of the present disclosure;

FIG. 8 is a schematic view of still other structures of a display panel according to an embodiment of the present disclosure;

FIG. 9a is a schematic view of still other structures of a display panel according to an embodiment of the present disclosure;

FIG. 9b is a schematic cross-sectional view of the display panel shown in FIG. 9a along the ZZ' direction;

FIG. 10 is a schematic view of still other structures of a display panel according to an embodiment of the present disclosure;

FIG. 11 is a schematic view of still other structures of a display panel according to an embodiment of the present disclosure;

FIG. 12 is a schematic view of still other structures of a display panel according to an embodiment of the present disclosure;

FIG. 13 is a schematic view of still other structures of a display panel according to an embodiment of the present disclosure;

FIG. 14 is a schematic view of still other structures of a display panel according to an embodiment of the present disclosure;

FIG. 15 is a schematic view of still other structures of a display panel according to an embodiment of the present disclosure;

FIG. 16 is a schematic view of still other structures of a display panel according to an embodiment of the present disclosure;

FIG. 17 is a schematic view of still other structures of a display panel according to an embodiment of the present disclosure;

FIG. 18 is a schematic view of still other structures of a display panel according to an embodiment of the present disclosure;

Fig. 19 is a schematic view of still another structure of a display panel in an embodiment of the disclosure.

Detailed Description

For the purpose of making the objects, technical solutions and advantages of the embodiments of the present disclosure more apparent, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present disclosure. It will be apparent that the described embodiments are some, but not all, of the embodiments of the present disclosure. And embodiments of the disclosure and features of embodiments may be combined with each other without conflict. All other embodiments, which can be made by one of ordinary skill in the art without the need for inventive faculty, are within the scope of the present disclosure, based on the described embodiments of the present disclosure.

Unless defined otherwise, technical or scientific terms used in this disclosure should be given the ordinary meaning as understood by one of ordinary skill in the art to which this disclosure belongs. The terms "first," "second," and the like, as used in this disclosure, do not denote any order, quantity, or importance, but rather are used to distinguish one element from another. The word "comprising" or "comprises", and the like, means that elements or items preceding the word are included in the element or item listed after the word and equivalents thereof, but does not exclude other elements or items. The terms "connected" or "connected," and the like, are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect.

It should be noted that the dimensions and shapes of the various figures in the drawings do not reflect true proportions, and are intended to illustrate the present disclosure only. And the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout.

In some embodiments of the present disclosure, a display device may include a display panel, a timing controller. The display panel may include an array substrate, and the array substrate may include a display area and a non-display area (i.e., an area other than an area surrounded by the display area, such as a sealant area). The display area may include a plurality of pixel units arranged in an array. Illustratively, each pixel cell includes a plurality of differently colored sub-pixels. For example, the pixel unit may include red, green, and blue sub-pixels, so that color mixing can be performed by red, green, and blue to realize color display. Alternatively, the pixel unit may include a red sub-pixel, a green sub-pixel, a blue sub-pixel, and a white sub-pixel, so that color mixing can be performed by red, green, blue, and white to realize color display. Of course, in practical application, the emission color of the sub-pixels in the pixel unit may be designed and determined according to the practical application environment, which is not limited herein.

In some embodiments of the present disclosure, the display region may further include a plurality of gate lines and a plurality of data lines. A transistor and a pixel electrode may be included in each sub-pixel. Wherein, a row of sub-pixels corresponds to a gate line, and a column of sub-pixels corresponds to a data line. The grid electrode of the transistor is coupled with the corresponding grid line, the source electrode of the transistor is coupled with the corresponding data line, and the drain electrode of the transistor is coupled with the pixel electrode. It should be noted that, the pixel array structure of the present disclosure may also be a dual-gate structure, that is, two gate lines are disposed between two adjacent rows of pixels, and the arrangement manner of the two gate lines is not limited, and may be reduced by half, that is, the two adjacent rows of pixels include data lines between two adjacent columns of pixels, and the two adjacent columns of pixels do not include data lines, which are specific to the pixel arrangement structure and the data lines.

In some embodiments of the present disclosure, the non-display region may include a gate driving circuit and a source driving circuit. The grid driving circuits are respectively coupled with the grid lines, and the source driving circuits are respectively coupled with the data lines. And, the timing controller may be coupled with the gate driving circuit and the source driving circuit, respectively. The general gate driving circuits are disposed in non-display regions on both left and right sides of the display panel. The common data lines are coupled to source driving circuits disposed On a Chip On Film (COF) through fan-out regions in the display panel. For example, the timing controller may acquire display data of a frame to be displayed in a current display frame, and the timing controller may input a control signal to the gate driving circuit, so that the gate driving circuit may output a gate scan signal to each gate line according to the input control signal, thereby driving each gate line to control the transistors in the coupled sub-pixels to be turned on. And the time schedule controller inputs the acquired display data to the source electrode driving circuit, so that the source electrode driving circuit can input data voltage to the coupled data line according to the input display data, and the voltage on the data line is input to the sub-pixel through the on transistor so as to charge the sub-pixel, and each sub-pixel is further charged with the corresponding data voltage, thereby realizing the picture display function.

It should be noted that the display panel in the embodiments of the present disclosure may be a liquid crystal display panel. Illustratively, the liquid crystal display panel generally includes upper and lower substrates of a pair of cells, and liquid crystal molecules encapsulated between the upper and lower substrates. When a picture is displayed, since a voltage difference exists between the data voltage applied to the pixel electrode of each sub-pixel and the common electrode voltage applied to the common electrode, the voltage difference can form an electric field, so that the liquid crystal molecules are deflected by the electric field. The different electric fields with different intensities lead the deflection degrees of the liquid crystal molecules to be different, so that the transmittance of the sub-pixels is different, the sub-pixels realize the brightness with different gray scales, and further the picture display is realized. Of course, the display panel in the embodiments of the present disclosure may be an OLED display panel, which is not limited herein.

In the display panel, especially for VA display panel (vertical alignment display panel), the common electrical signal On one side of the opposite substrate is transferred from the driving circuit to the common line in the frame glue area On the array substrate via the Chip On Film (COF), that is, the conductive particles (such as gold balls) disposed in the frame glue are transferred to the common electrode On one side of the opposite substrate through the transfer layer in the frame glue area, and the common line at the transfer position is generally required to be provided with an insulating layer via hole, and the via hole is required to be covered with the transfer layer. Unlike amorphous silicon process insulating layer which is silicon nitride only, oxide thin film transistor (Oxide Thin Film Transistor) process insulating layer is a composite film of silicon nitride and silicon oxide, or a composite film of silicon nitride, silicon oxide and organic insulating layer, or a composite film of silicon nitride, silicon oxide, color layer and organic insulating layer; however, the insulating layer having silicon oxide has poor film quality and poor adhesion to the switching layer over the insulating layer as compared with the film layer made of silicon nitride alone, and if external static electricity is too large, since the display panel currently on the market has via holes arranged at four frames at equal intervals and is not arranged at the corners of the display panel, external static electricity may accumulate at the corners of the display panel, and the switching layer may be easily peeled off (peeling) from the insulating layer.

The opposite substrate is provided with a transparent common electrode, if the edge of the display panel is provided with large-charge static electricity, the static electricity possibly enters the box through the transparent common electrode on the opposite substrate, and if the static electricity is near the through hole, the static electricity can be transferred into a common line in the frame glue area on the array substrate through the through hole through the transfer layer in the frame glue area, so that static electricity injury is avoided; if the static electricity is not near the through hole or at the corner of the display panel, the static electricity may directly enter the display area in the box through the transparent common electrode on the opposite substrate, and is coupled to the pixel electrode on the lower array substrate through the liquid crystal capacitor, so that the display panel has bad broken bright spots, especially on the display panel without the through hole or with a narrow frame design, the static electricity is easy to damage, the broken bright spots are bad, and the display quality is reduced.

Based on the above-mentioned problems, the display panel provided by the embodiments of the present disclosure, as shown in fig. 1a to 1c, includes:

an array substrate, comprising: a first substrate 10, a common line 11 disposed on the first substrate 10, an insulating layer 12 disposed on a side of the common line 11 facing away from the first substrate 10, and a transfer layer 13 disposed on a side of the insulating layer 12 facing away from the first substrate 10;

An opposite substrate disposed opposite to the array substrate, the opposite substrate comprising: a second substrate 20, a transparent common electrode 21 disposed on a side of the second substrate 20 facing the first substrate 10, the transparent common electrode 21 being electrically connected to the transfer layer 13;

As shown in fig. 2a and fig. 2b, the array substrate has a display area AA and a sealant area BB surrounding the display area AA, the front projection of the common line 11 on the first substrate 10 and the front projection of the switching layer 13 on the first substrate 10 are disposed in the sealant area BB, the insulating layer 12 in the sealant area BB has a plurality of first via groups 010 surrounding the display area AA, the plurality of first via groups 010 respectively include a plurality of first vias 01 disposed at intervals, and the first vias 01 in two adjacent first via groups 010 are disposed in a staggered manner; the transfer layer 13 is connected to the common line 11 through a plurality of first via groups 010.

As shown in fig. 2a and fig. 2b, in the embodiment of the disclosure, a plurality of first via groups surrounding a display area are disposed through an insulating layer in a frame glue area BB, each of the plurality of first via groups includes a plurality of first vias disposed at intervals, and first vias in two adjacent first via groups are disposed in a staggered manner; the switching layer 13 is connected to the common line 11 through a plurality of first via groups; when external static electricity (Electro-STATIC DISCHARGE, ESD) of the display panel enters the box through the edge of the display panel, the switching layer 13 can be connected with the common line 11 through a plurality of first through holes, so that the external static electricity is quickly dissipated to the common line, a large amount of static electricity is effectively prevented from being gathered to cause a breakdown, the static electricity is prevented from being damaged, broken bright spots are prevented from being caused, and the display quality is improved.

The first through holes in the two adjacent first through hole groups are arranged in a staggered mode, so that the effective contact area between the first through holes and the switching layer can be increased, electrostatic damage can be avoided, and the switching layer is prevented from being stripped (peeling) from the insulating layer. And is favorable for charge dissipation and avoids a large amount of charge accumulation.

Illustratively, as shown in fig. 1a, the array substrate further includes: the first conductive layer 110 is located on the first substrate 10, the gate insulating layer 121 is located on the side, away from the first substrate 10, of the first conductive layer 110, the semiconductor layer 150 is located on the side, away from the first substrate 10, of the gate insulating layer 121, the second conductive layer 160 is located on the side, away from the first substrate 10, of the semiconductor layer 150, the interlayer insulating layer 122 is located on the side, away from the first substrate 10, of the second conductive layer 160, the electrode layer 130 is located on the side, away from the first substrate 10, of the interlayer insulating layer 122, the electrode layer 130 is located on the side, away from the first substrate 10, wherein the first conductive layer 110 comprises a plurality of common lines 11, the second conductive layer 160 comprises a plurality of signal lines 16, and the electrode layer 130 comprises a pixel electrode 14 and a switching layer 13. Based on this structure, the insulating layer 12 includes: the gate insulating layer 121 and the interlayer insulating layer 122 are formed, and the first via 01 penetrates the gate insulating layer 121 and the interlayer insulating layer 122.

By way of example, the material of the semiconductor layer may include an oxide, amorphous silicon, or low temperature polysilicon, etc., without limitation.

For example, the gate insulating layer 121 and the interlayer insulating layer 122 are each formed using an insulating material, and an organic insulating material, such as polyimide, a resin material, or an inorganic insulating material, such as silicon oxide, silicon nitride, or silicon oxynitride, may be selected as needed.

Illustratively, as shown in fig. 1b, the array substrate further includes: a first conductive layer 110 (e.g., the first conductive layer may be disposed on the gate line layer) disposed on the first substrate 10, a gate insulating layer 121 disposed on a side of the first conductive layer 110 facing away from the first substrate 10, a semiconductor layer 150 disposed on a side of the gate insulating layer 121 facing away from the first substrate 10, a second conductive layer 160 (e.g., the second conductive layer may be disposed on the source-drain metal layer) disposed on a side of the semiconductor layer 150 facing away from the first substrate 10, an interlayer insulating layer 122 disposed on a side of the second conductive layer 160 facing away from the first substrate 10, a planarization layer 123 disposed on a side of the interlayer insulating layer 122 facing away from the first substrate 10, and an electrode layer 130 disposed on a side of the planarization layer 123 facing away from the first substrate 10, wherein the first conductive layer 110 includes the plurality of common lines 11, the second conductive layer 160 includes the plurality of signal lines 16, and the electrode layer 130 includes the pixel electrode 14 and the transfer layer 13. The first conductive layer 110 includes a plurality of common lines 11, the second conductive layer 160 includes a plurality of signal lines 16, and the electrode layer 130 includes a pixel electrode 14 and a switching layer 13. Based on this structure, the insulating layer 12 includes: the gate insulating layer 121, the interlayer insulating layer 12 and the planarization layer 123 are formed, and the first via 01 penetrates the gate insulating layer 121, the interlayer insulating layer 122 and the planarization layer 123.

For example, the gate insulating layer 121, the interlayer insulating layer 12, and the planarization layer 123 are each formed using an insulating material, and an organic insulating material such as polyimide, a resin material, or an inorganic insulating material such as silicon oxide, silicon nitride, or silicon oxynitride may be selected as necessary.

As shown in fig. 1a and 1b, the frame glue area BB is provided with a frame glue 220, and has conductive balls 22, wherein the conductive balls 22 may be gold balls, and one end of each conductive ball 22 is connected to the interposer 13, and the other end is connected to the common electrode 21, so that the common electrode 21 is connected to the interposer 13. The transfer layer 13 is connected to the common line 11 through the first via 01, and a common signal can be transferred from the array substrate side to the common electrode 21 on the opposite substrate side.

As shown in fig. 2a, the common line 11 may be connected to an integrated circuit (INTEGRATED CIRCUIT, IC) disposed on the flip chip film COF, and the integrated circuit inputs a common electrode voltage to the transparent common electrode 21 through the common line 11. Further, static electricity on the transparent common electrode 21 is discharged through the common line 11.

Illustratively, as shown in fig. 2a, the array substrate further includes: a ground line GND; the ground line GND is disposed around the common line 11 on a side facing away from the display area AA, and the integrated circuit on the flip chip film COF is connected to the ground terminal through the ground line GND. The grounding wire is used for protecting the integrated circuit.

Illustratively, the material of the transparent common electrode includes a transparent conductive material, which may include, but is not limited to, indium Tin Oxide (ITO), indium Zinc Oxide (IZO), for example.

Illustratively, the common line is composed of a conductive material, e.g., the conductive material is a metal, e.g.,: titanium (Ti), gold (Au), silver (Ag), molybdenum (Mo), copper (Cu), and the like, are not limited herein.

In some embodiments of the present disclosure, as shown in fig. 2a and 3, the frame glue area BB includes: a first sub-frame glue area BB1 and a second sub-frame glue area BB2 which are oppositely arranged along a first direction F1, and a third sub-frame glue area BB3 and a fourth sub-frame glue area BB4 which are oppositely arranged along a second direction F2; the fourth sub-frame glue area BB4 has a fan-out area FO.

In some embodiments of the present disclosure, as shown in fig. 4 and 6b, the common line 11 includes a first common line 111, and the orthographic projection of the first common line 111 on the first substrate 10 extends from one side of the fourth sub-frame glue area BB4 near the first sub-frame glue area BB1 to one side of the third sub-frame glue area BB3 near the first sub-frame glue area BB 1.

In some embodiments of the present disclosure, as shown in fig. 4 and 6b, the orthographic projection of the first common line 111 on the first substrate 10 extends from a side of the fourth sub-frame glue area BB4 near the first sub-frame glue area BB1 to a side of the fourth sub-frame glue area BB4 near the second sub-frame glue area BB 2.

In some embodiments of the present disclosure, as shown in fig. 5, the transit layer 13 includes: the first sub-switching layer 131, wherein at least one of the first sub-frame glue area BB1, the second sub-frame glue area BB2 and the third sub-frame glue area BB3 is provided with a first sub-switching layer 13 and a plurality of first via groups 010, and the first sub-switching layer 131 is connected to the first common line 111 through the plurality of first via groups 010.

Illustratively, the orthographic projection of the first common line 111 on the first substrate is in a grid shape, which is beneficial to curing the sealant. The first common lines can be arranged as much as possible, the first sub-transfer layer and the plurality of first via hole groups are arranged in the first sub-frame glue area, the second sub-frame glue area and the third sub-frame glue area, and if external static electricity enters from the area covered by the first sub-frame glue area, the second sub-frame glue area and the third sub-frame glue area, the external static electricity can be quickly transferred to the first common lines through the first sub-transfer layer and the plurality of first via hole groups, so that static electricity is prevented from being damaged.

For example, the first sub-frame glue area, the second sub-frame glue area and the third sub-frame glue area may include: a first sub-switching layer and a plurality of first via groups; of course, the first sub-frame glue area and the second sub-frame glue area may also include: a first sub-switching layer and a plurality of first via groups; of course, the first sub-frame glue area and the third sub-frame glue area may also include: a first sub-switching layer and a plurality of first via groups; of course, the second sub-frame glue area and the third sub-frame glue area may also include: a first sub-switching layer and a plurality of first via groups; and the like are not limited herein.

In some embodiments of the present disclosure, as shown in fig. 5, 6a, and 7, the first sub-switching layer 131 includes a plurality of first switching portions 1311 sequentially connected, the plurality of first switching portions 1311 extend along the second direction F2, and two adjacent first switching portions 1311 are disposed in a staggered manner.

For example, the orthographic projection of the first transfer portion on the first substrate base plate may include: at least one of rectangular, diamond-shaped, oval, circular, polygonal, etc. For example, the front projection of the first transfer portion on the first substrate may be made rectangular; or the orthographic projection of the first transfer part on the first substrate base plate can be diamond; or the orthographic projection of the first transfer part on the first substrate base plate can be elliptical; or the orthographic projection of the first transfer part on the first substrate base plate can be made into a round shape; alternatively, the orthographic projection of the first transfer portion on the first substrate may be made polygonal, or the like; and are not limited thereto.

As illustrated in fig. 6a, 6b, and 7, the array substrate is further provided with one, two, three, or more trenches GC penetrating the insulating layer 12 (e.g., the gate insulating layer 121, the interlayer insulating layer 12, the planarization layer 123), and each of the trenches GC is disposed in the frame glue region BB.

For example, as shown in fig. 6a, 6b and 7, two trenches GC are disposed between the first common line 111 and the display region, and one trench GC is disposed on a side of the first common line 111 away from the display region. In practical application, after the frame sealing glue is arranged on the array substrate, the frame sealing glue can fill the grooves GC, so that the sealing property of the frame sealing glue is improved.

As shown in fig. 6a and 7, a plurality of elongated first vias 01 and a plurality of square vias are disposed in the first, second and third frame glue areas BB1, BB2 and BB 3.

In some embodiments of the present disclosure, as shown in fig. 8, 9a, and 9b, the fourth sub-frame glue area BB4 includes: a plurality of fan-out areas FO and a non-fan-out area disposed between two adjacent fan-out areas; the common line 11 includes a plurality of second common lines 112, and the switching layer 13 includes: the second sub-switching layers 132, the second common lines 112, the second sub-switching layers 132 and the non-fanout areas are in one-to-one correspondence, and the orthographic projection of the second common lines 112 on the first substrate 10 and the orthographic projection of the second sub-switching layers 132 on the first substrate 10 are both arranged in the corresponding non-fanout areas; the non-fanout area includes a plurality of first via groups 010, wherein in the same non-fanout area, the second sub-switching layer 132 is connected to the second common line 112 through the plurality of first via groups 010.

As shown in fig. 8 and 9b, the common line 11 includes a second common line 112, and the orthographic projection of the second common line 112 on the first substrate 10 extends from one side of the fourth sub-frame glue area BB4 near the first sub-frame glue area BB1 to one side of the third sub-frame glue area BB3 near the first sub-frame glue area BB 1.

As shown in fig. 8 and 9b, the orthographic projection of the second common line 112 on the first substrate 10 extends from a side of the fourth sub-frame glue area BB4 near the first sub-frame glue area BB1 to a side of the fourth sub-frame glue area BB4 near the second sub-frame glue area BB 2.

Illustratively, the orthographic projection of the second common line on the first substrate is in a grid shape. The second common lines can be arranged as much as possible, a plurality of second sub-switching layers and a plurality of first via groups are arranged in the fourth sub-frame glue area, and if external static electricity enters from the area covered by the fourth sub-frame glue area, the external static electricity can be quickly transferred onto the second common lines through the second sub-switching layers and the plurality of first via groups, so that static electricity is prevented from being damaged.

In some embodiments of the present disclosure, as shown in fig. 8 and 9a, the second sub-switching layer 132 includes a plurality of second switching portions 1321 connected in sequence, the plurality of second switching portions 1321 extend along the first direction F1, and two adjacent second switching portions 1321 are arranged in a staggered manner.

For example, the orthographic projection of the second adapter on the first substrate base plate may include: at least one of rectangular, diamond-shaped, oval, circular, polygonal, etc. For example, the second transfer portion may be orthographic projected on the first substrate as a rectangle; or the orthographic projection of the second switching part on the first substrate base plate can be diamond; or the orthographic projection of the second switching part on the first substrate base plate can be elliptical; or the orthographic projection of the second adapter part on the first substrate base plate can be made into a round shape; or the orthographic projection of the second switching part on the first substrate base plate can be polygonal; and are not limited thereto.

For example, as shown in fig. 9a and 9b, two trenches GC are provided between the first common line 111 and the display region. In practical application, after the frame sealing glue is arranged on the array substrate, the frame sealing glue can fill the grooves GC, so that the sealing property of the frame sealing glue is improved.

In some embodiments of the present disclosure, as shown in fig. 10, the orthographic projection of the first via 01 on the first substrate 10 includes a stripe shape, and a long edge of the stripe shape extends near an edge of the display area AA.

In some embodiments of the present disclosure, as shown in fig. 10, when a plurality of first via groups 010 are disposed in the first subframe glue area BB1, the long strip extends along the second direction F2.

In some embodiments of the present disclosure, as shown in fig. 10, when a plurality of first via groups 010 are disposed in the second subframe glue area BB2, the long strip extends along the second direction F2.

In some embodiments of the present disclosure, as shown in fig. 10, when a plurality of first via groups 010 are disposed in the third subframe glue area BB3, the long strip extends along the first direction F1.

In some embodiments of the present disclosure, as shown in fig. 10, when a plurality of first via groups 010 are disposed in the fourth subframe glue area BB4, the long strip extends along the first direction F1.

In some embodiments of the present disclosure, as shown in fig. 11, the frame glue area BB further includes: the first frame glue corner area BBG1 and the second frame glue corner area BBG2, the first frame glue corner area BBG1 is arranged between the first sub frame glue area BB1 and the BB3 of the third sub frame glue area, and the second frame glue corner area BBG2 is arranged between the second sub frame glue area BB2 and the BB3 of the third sub frame glue area.

As shown in fig. 3, 4, and 11. A plurality of first common lines 111 are also provided in the first and second frame glue corner regions BBG1 and BBG 2.

In some embodiments of the present disclosure, as shown in fig. 11 to 16, at least one of the first and second sealant corner regions BBG1 and BBG2 is provided with a third sub-interposer 133 and a plurality of second vias 02 disposed at intervals therein, and the third sub-interposer 133 is connected to the first common line through the plurality of second vias 02. Wherein the second via group 020 includes a plurality of second vias 02.

The first frame glue corner region and the second frame glue corner region are provided with a first sub-switching layer and a plurality of first through holes, and if external static electricity enters from the area covered by the first frame glue corner region and the second frame glue corner region, the external static electricity can be quickly transferred to the first common line through the first sub-switching layer and the plurality of first through holes, so that static electricity damage is avoided.

In some embodiments of the present disclosure, as shown in fig. 12, a plurality of second vias 02 are arranged around the display area AA.

In some embodiments of the present disclosure, the shape of the orthographic projection of the second via on the first substrate includes: at least one of rectangular, circular, elliptical, and polygonal.

For example, the shape of the orthographic projection of the second via on the first substrate may be rectangular, or the shape of the orthographic projection of the second via on the first substrate may be circular, or the shape of the orthographic projection of the second via on the first substrate may be elliptical; the shape of the orthographic projection of the second via hole on the first substrate may be polygonal, or the shape of the orthographic projection of the second via hole on the first substrate may be a combination of the above shapes, or the like, and is not limited herein.

As illustrated in fig. 13 and 14, the shape of the orthographic projection of the second via 02 on the first substrate is a circle.

For example, as shown in fig. 13 and 14, two trenches GC are provided on the side of the first common line 111 away from the display area. In practical application, after the frame sealing glue is arranged on the array substrate, the frame sealing glue can fill the grooves GC, so that the sealing property of the frame sealing glue is improved.

As illustrated in fig. 15 and 16, the second via 02 is rectangular in shape in orthographic projection on the first substrate.

For example, as shown in fig. 15 and 16, two trenches GC are provided between the first common line 111 and the display region. In practical application, after the frame sealing glue is arranged on the array substrate, the frame sealing glue can fill the grooves GC, so that the sealing property of the frame sealing glue is improved.

In some embodiments of the present disclosure, as shown in fig. 10, a plurality of third vias 03 are further disposed in the subframe glue areas (BB 1, BB2, BB3, BB 4) where the plurality of first via groups 010 are disposed, where the plurality of third vias 03 are disposed at intervals from the plurality of first vias 01, and the first sub-switching layer 131 is further connected to the first common line through the plurality of third vias 03.

In some embodiments of the present disclosure, as shown in fig. 10, the plurality of third vias 03 is divided into a plurality of third via groups 030, each third via group 030 including the plurality of third vias 03; the plurality of third via groups 030 are disposed around the display area AA.

In some embodiments of the present disclosure, as shown in fig. 17, at least one third via group 030 is disposed between two adjacent first via groups 010.

For example, one third via group, two third via groups, three third via groups, five third via groups, ten third via groups, and the like may be disposed between two adjacent first via groups, which are not limited herein.

In some embodiments of the present disclosure, as shown in fig. 17, at least one third via group 030 is disposed on a side of the plurality of first via groups 010 facing away from the display area AA.

For example, one third via group, two third via groups, three third via groups, five third via groups, ten third via groups, and the like may be disposed on a side of the first via group facing away from the display area, which is not limited herein.

In some embodiments of the present disclosure, as shown in fig. 17, at least one third via group 030 is disposed between the plurality of first via groups 010 and the display area AA.

For example, one third via group, two third via groups, three third via groups, five third via groups, ten third via groups, and the like may be disposed between the first via group and the display area AA, which is not limited herein.

In some embodiments of the present disclosure, as shown in fig. 17, one first via group 010 corresponds to one third via group 030 one by one, and at least one end of a first via 01 in the first via group 010 is provided with one third via 03 in the corresponding third via group 030.

For example, one third via group, two third via groups, three third via groups, five third via groups, ten third via groups, etc. may be disposed at one end of the first via in the first via group, which is not limited herein; one third via group, two third via groups, three third via groups, five third via groups, ten third via groups, and the like may be provided at both ends of the first via in the first via group, which is not limited herein.

In some embodiments of the present disclosure, the shape of the orthographic projection of the third via on the first substrate includes: at least one of rectangular, circular, elliptical, and polygonal.

For example, the shape of the orthographic projection of the third via hole on the first substrate may be rectangular, or the shape of the orthographic projection of the third via hole on the first substrate may be circular, or the shape of the orthographic projection of the third via hole on the first substrate may be elliptical; the shape of the orthographic projection of the third via hole on the first substrate may be polygonal, or the shape of the orthographic projection of the third via hole on the first substrate may be a combination of the above shapes, and the like, and is not limited herein.

The present disclosure provides other embodiments of the array substrate, as shown in fig. 18, which are modified from the embodiments described above. Only the differences between the present embodiment and the above-described embodiments are described below, and their details are not repeated here.

In some embodiments of the present disclosure, as shown in fig. 18, the first sub-switching layer 131 is elongated and extends along the second direction F2.

In some embodiments of the present disclosure, as shown in fig. 19, the second sub-switching layer 132 is elongated and extends along the first direction F1.

Based on the same disclosure concept, the embodiment of the disclosure also provides a display device, which comprises the display panel provided by the embodiment of the disclosure. The principle of the display device for solving the problems is similar to that of the display panel, so that the implementation of the display device can be referred to the implementation of the display panel, and the repetition is omitted herein.

In specific implementation, in the embodiment of the disclosure, the display device may be: any product or component with display function such as a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator and the like. Other essential components of the display device are those of ordinary skill in the art and will not be described in detail herein, nor should they be considered as limiting the present disclosure.

While the preferred embodiments of the present disclosure have been described, additional variations and modifications in those embodiments may occur to those skilled in the art once they learn of the basic inventive concepts. It is therefore intended that the following claims be interpreted as including the preferred embodiments and all such alterations and modifications as fall within the scope of the disclosure.

It will be apparent to those skilled in the art that various modifications and variations can be made to the disclosed embodiments without departing from the spirit and scope of the disclosed embodiments. Thus, given that such modifications and variations of the disclosed embodiments fall within the scope of the claims of the present disclosure and their equivalents, the present disclosure is also intended to encompass such modifications and variations.

Claims

1. A display panel, comprising:

An opposite substrate disposed opposite to the array substrate, the opposite substrate comprising: the second substrate is arranged on the public electrode on one side of the second substrate facing the first substrate, and the public electrode is connected with the switching layer.

2. The display panel of claim 1, wherein the frame glue area comprises: the first sub-frame glue area and the second sub-frame glue area are oppositely arranged along the first direction, and the third sub-frame glue area and the fourth sub-frame glue area are oppositely arranged along the second direction; the fourth sub-frame glue area is provided with a fan-out area;

3. The display panel according to claim 2, wherein the first sub-switching layer includes a plurality of first switching portions connected in sequence, the plurality of first switching portions extend along the second direction, and two adjacent first switching portions are arranged in a staggered manner; or alternatively

4. The display panel of claim 2, wherein the fourth subframe glue zone comprises: the fan-out areas and the non-fan-out areas are arranged between two adjacent fan-out areas;

5. The display panel according to claim 4, wherein the second sub-switching layer includes a plurality of second switching parts sequentially connected, the plurality of second switching parts extend along the first direction, and two adjacent second switching parts are arranged in a staggered manner; or alternatively

6. The display panel of any one of claims 2-5, wherein the shape of the orthographic projection of the first via on the first substrate includes a stripe shape, and a long edge of the stripe shape extends near an edge of the display area.

7. The display panel of claim 6, wherein the elongated long edge extends in the second direction when the plurality of first via groups are disposed in the first subframe glue zone; and/or the number of the groups of groups,

8. The display panel of any one of claims 2-5, wherein the frame glue area further comprises: the first frame glue corner region is arranged between the first sub frame glue region and the third sub frame glue region, and the second frame glue corner region is arranged between the second sub frame glue region and the third sub frame glue region;

And a third sub-switching layer and a plurality of second through holes arranged at intervals are arranged in at least one frame glue corner region of the first frame glue corner region and the second frame glue corner region, and the third sub-switching layer is connected with the first common line through the plurality of second through holes.

9. The display panel of claim 8, wherein the plurality of second vias are arranged around the display area; and/or the number of the groups of groups,

10. The display panel of any one of claims 2-5, wherein a plurality of third vias are further disposed in the subframe glue region in which the plurality of first via groups are disposed, the plurality of third vias being disposed at intervals from the plurality of first vias, the first sub-switching layer being further connected to the first common line through the plurality of third vias.

11. The display panel of claim 10, wherein the plurality of third vias are divided into a plurality of third via groups, each third via group including a plurality of third vias; the plurality of third via groups are disposed around the display area.

12. The display panel of claim 11, wherein at least one third via group is disposed between two adjacent first via groups; and/or the number of the groups of groups,

13. The display panel of claim 11 or 12, wherein one of the first via groups corresponds one-to-one to one with one of the third via groups, at least one end of a first via in the first via group being provided with a corresponding one of the third via groups.

14. The display panel of claim 10, wherein the shape of the orthographic projection of the third via on the first substrate comprises: at least one of rectangular, circular, elliptical, and polygonal.

15. A display device comprising a display panel according to any one of claims 1-14.