CN220855147U - High-voltage interlocking circuit, device and high-voltage loop detection system - Google Patents
High-voltage interlocking circuit, device and high-voltage loop detection system Download PDFInfo
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- CN220855147U CN220855147U CN202322157379.4U CN202322157379U CN220855147U CN 220855147 U CN220855147 U CN 220855147U CN 202322157379 U CN202322157379 U CN 202322157379U CN 220855147 U CN220855147 U CN 220855147U
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Abstract
The utility model provides a high-voltage interlocking circuit, a device and a high-voltage loop detection system, wherein the high-voltage interlocking circuit comprises a constant current circuit, a mirror image current source circuit, a first voltage dividing circuit, a second voltage dividing circuit, a circuit output end, a circuit input end, a first sampling end and a second sampling end; the constant current circuit is used for receiving the first power supply signal and generating constant current with constant current value; the first sampling end is used for being connected with a data acquisition end of the external processor so that the external processor can acquire the first voltage output by the first voltage dividing circuit through the first sampling end; the second sampling end is used for being connected with a data acquisition end of the external processor, so that the external processor acquires second voltage output by the second voltage dividing circuit through the second sampling end, and whether the high-voltage loop to be detected fails or not is determined based on the first voltage and the second voltage. By the mode, the high-voltage loop fault detection precision can be improved.
Description
Technical Field
The utility model relates to the technical field of high-voltage loop detection, in particular to a high-voltage interlocking circuit, a high-voltage interlocking device and a high-voltage loop detection system.
Background
The High Voltage Interlock (HVIL) is an essential function of a vehicle-mounted Battery management system (Battery MANAGEMENT SYSTEM, BMS), which is to detect the integrity of a high voltage circuit by using a low voltage signal, and detect whether the high voltage circuit has a connection fault, so as to timely disconnect a high voltage relay to protect the BMS safety when the high voltage connection fault occurs.
However, most BMS at present sends PWM waves to the high-voltage interlocking circuit, and then detects signals fed back by the high-voltage interlocking circuit to judge whether the high-voltage loop is normally connected, so that the mode has weak anti-interference capability, and the problem of low precision of fault detection of the high-voltage loop exists.
Disclosure of utility model
In view of the above, the present utility model provides a high-voltage interlock circuit, a high-voltage interlock device, and a high-voltage loop detection system, which can improve the accuracy of high-voltage loop fault detection.
In order to solve the technical problems, in one aspect, the utility model provides a high-voltage interlocking circuit, which comprises a constant current circuit, a mirror current source circuit, a first voltage dividing circuit, a second voltage dividing circuit, a circuit output end, a circuit input end, a first sampling end and a second sampling end. The constant current circuit is used for receiving the first power supply signal and generating constant current with constant current value; the mirror current source circuit comprises a first mos tube and a second mos tube, wherein grid electrodes of the first mos tube are connected with each other, a source electrode of the first mos tube receives a second power supply signal through a first resistor, a source electrode of the second mos tube receives the second power supply signal through a second resistor, a drain electrode of the first mos tube is connected with the constant current circuit and the grid electrode of the first mos tube, and is used for receiving constant current, and mapping the constant current to the second mos tube so that the constant current flows through the second mos tube; the circuit output end and the circuit input end are respectively connected with the high-voltage loop to be detected so as to realize electric connection through the high-voltage loop to be detected, and the circuit output end is connected with the drain electrode of the second mos tube; the first sampling end is connected with the drain electrode of the second mos tube through a first voltage dividing circuit and is used for being connected with the data acquisition end of the external processor, so that the external processor acquires the first voltage output by the first voltage dividing circuit through the first sampling end; the second sampling end is connected with the circuit input end through the second voltage dividing circuit and is used for being connected with the data acquisition end of the external processor, so that the external processor acquires the second voltage output by the second voltage dividing circuit through the second sampling end, and whether the high-voltage loop to be detected fails or not is determined based on the first voltage and the second voltage.
According to some embodiments of the utility model, a constant current circuit includes: the collector of the first triode is connected with the drain electrode of the first mos tube; one end of the third resistor is connected with the emitter of the first triode, and the other end of the third resistor is grounded; one end of the fourth resistor receives the first power supply signal, and the other end of the fourth resistor is connected with the base electrode of the first triode; one end of the fifth resistor is connected with the other end of the fourth resistor and the base electrode of the first triode, and the other end of the fifth resistor is grounded; and one end of the first filter capacitor is connected with the base electrode of the first triode and the other end of the fourth resistor, and the other end of the first filter capacitor is grounded.
According to some embodiments of the utility model, the first voltage divider circuit comprises: one end of the sixth resistor is connected with the drain electrode of the second mos tube and the output end of the circuit, and the other end of the sixth resistor is connected with the first sampling end; one end of the seventh resistor is connected with the other end of the sixth resistor and the first sampling end, and the other end of the seventh resistor is grounded; the second voltage dividing circuit includes: one end of the eighth resistor is connected with the input end of the circuit, and the other end of the eighth resistor is connected with the second sampling end; and one end of the ninth resistor is connected with the other end of the eighth resistor and the second sampling end, and the other end of the ninth resistor is grounded.
According to some embodiments of the utility model, the high voltage interlock circuit further comprises a switch circuit, wherein the switch circuit is connected with the second power supply signal, the control end of the external processor and the mirror current source circuit, and is used for conducting a passage between the second power supply signal and the mirror current source circuit after receiving a starting control signal output by the external processor;
Wherein the switching circuit comprises: the emitter of the second triode receives a second power supply signal, and the collector of the second triode is connected with the source of the second mos tube and the source of the first mos tube through a second resistor and a first resistor respectively; and the collector electrode of the third triode is connected with the base electrode of the second triode, the emitter electrode of the third triode is grounded, and the base electrode of the third triode is connected with the control end of the external processor.
According to some embodiments of the utility model, the high voltage interlock circuit further comprises a short circuit protection circuit, wherein the short circuit protection circuit comprises: the collector of the fourth triode is connected with the second voltage dividing circuit and the circuit input end; one end of the tenth resistor is connected with the emitter of the fourth triode, and the other end of the tenth resistor is grounded; the base electrode of the fifth triode is connected with one end of the tenth resistor and the emitter electrode of the fourth triode, the collector electrode of the fifth triode is connected with the base electrode of the fourth triode, and the emitter electrode of the fifth triode is grounded; and one end of the eleventh resistor is connected with the collector electrode of the fifth triode and the base electrode of the fourth triode, and the other end of the eleventh resistor is connected with the control end of the external controller.
According to some embodiments of the utility model, the high voltage interlock circuit further comprises a current limiting resistor, one end of the current limiting resistor is connected with the second voltage dividing circuit and the circuit input end, and the other end of the current limiting resistor is connected with the collector electrode of the fourth triode.
According to some embodiments of the utility model, the high voltage interlock circuit further comprises: one end of the second filter capacitor is connected with the drain electrode of the second mos tube and the output end of the circuit, and the other end of the second filter capacitor is grounded; one end of the third filter capacitor is connected with the first sampling end and the first voltage dividing circuit, and the other end of the third filter capacitor is grounded; one end of the fourth filter capacitor is connected with the power input end and the second voltage dividing circuit, and the other end of the fourth filter capacitor is grounded; and one end of the fifth filter capacitor is connected with the second sampling end and the second voltage dividing circuit, and the other end of the fifth filter capacitor is grounded.
In a second aspect, an embodiment of the present utility model provides a high voltage interlock device, including a high voltage interlock circuit, where the high voltage interlock circuit is the high voltage interlock circuit in the foregoing embodiment.
In a third aspect, an embodiment of the present utility model provides a high voltage loop detection system, including a high voltage interlock device and a processor; the high-voltage interlocking device is the high-voltage interlocking device in the embodiment, and is used for detecting a high-voltage loop to be detected and outputting a first voltage and a second voltage; the processor is connected with the high-voltage interlocking device and is used for collecting the first voltage and the second voltage and determining whether the high-voltage loop to be detected fails or not based on the first voltage and the second voltage.
According to some embodiments of the utility model, the processor is configured to determine that the high voltage loop to be detected is faulty when the difference between the first voltage and the second voltage does not fall within a preset difference range.
The technical scheme of the utility model has at least one of the following beneficial effects: the constant current circuit and the mirror current source circuit are arranged, so that the current in the high-voltage interlocking circuit is constant, the high-voltage interlocking circuit has the characteristics of high output current precision, high stability and strong anti-interference capability, and the problems of low identification degree and poor anti-interference capability of the high-voltage interlocking circuit in the current market are solved. On the basis, the first voltage and the second voltage are utilized to carry out fault judgment of the high-voltage loop, so that the reference precision of the voltage value can be ensured, and the precision of fault detection of the high-voltage loop is improved. And the external processor can directly acquire fault parameters (namely the first voltage and the second voltage) of the high-voltage loop through the sampling port, and can realize continuous and efficient high-voltage loop state monitoring, so that the high-voltage relay can be disconnected in time to protect the system safety when the high-voltage loop fails in connection, and the real-time performance is higher and the safety is higher. In addition, the high-voltage interlock circuit in this embodiment is lower in cost than the conventional way of outputting PWM waves to detect the high-voltage interlock circuit.
Further, by arranging the switching circuit, the autonomous switching control of the high-voltage interlocking circuit can be realized by using an external controller, and the effect of low power consumption is realized.
Furthermore, through setting up a plurality of filter capacitors, can utilize each filter capacitor external interference signal of filtering, further improve the interference killing feature of circuit to improve the precision of high-voltage circuit fault detection.
Further, by arranging the short-circuit protection circuit and the current limiting resistor, the safety and stability of the circuit can be further ensured.
Drawings
FIG. 1 is a schematic diagram of a high-voltage loop detection system according to an embodiment of the present utility model;
FIG. 2 is a schematic illustration of a high pressure interlock according to an embodiment of the present utility model;
FIG. 3 is a schematic diagram of a high voltage interlock circuit according to an embodiment of the present utility model;
FIG. 4 is a schematic diagram of a high voltage interlock circuit according to another embodiment of the present utility model;
FIG. 5 is a schematic diagram of a high voltage interlock circuit according to yet another embodiment of the present utility model;
FIG. 6 is a schematic diagram of a high voltage interlock circuit according to yet another embodiment of the present utility model;
FIG. 7 is a schematic diagram of a high voltage interlock circuit according to yet another embodiment of the present utility model;
fig. 8 is a schematic diagram of a high voltage interlock circuit according to yet another embodiment of the present utility model.
Detailed Description
The following describes in further detail the embodiments of the present utility model with reference to the drawings and examples. The following examples are illustrative of the utility model and are not intended to limit the scope of the utility model.
As shown in fig. 1, a high voltage loop detection system 1000 of an embodiment of the present utility model includes a high voltage interlock 1001 and a processor 1002 that are interconnected. The high-voltage interlock device 1001 is a high-voltage interlock device in the following embodiment, and is configured to detect a high-voltage circuit (not shown in the figure) to be detected and output a first voltage and a second voltage; the processor 1002 is configured to collect the first voltage and the second voltage, and determine whether the high voltage circuit to be detected is faulty based on the first voltage and the second voltage.
In an embodiment, the processor 1002 may be configured to determine that the high voltage circuit to be detected is faulty when the difference between the first voltage and the second voltage does not fall within a preset difference range; and when the difference value of the first voltage and the second voltage falls within a preset difference value range, determining that the high-voltage loop to be detected has no fault. It will be appreciated that the preset difference range may be set according to actual requirements, which is not limited herein.
As shown in fig. 2, the high voltage interlock device 1001 according to the embodiment of the present utility model includes a high voltage interlock circuit 10, wherein the high voltage interlock circuit 10 is a high voltage interlock circuit in the following embodiment, which will not be described in detail herein.
The high voltage interlock device 1001 can improve the accuracy of high voltage loop fault detection by the high voltage interlock circuit 10, and the high voltage interlock circuit 10 will be described in detail below.
As shown IN fig. 3, the high voltage interlock circuit 10 according to the embodiment of the present utility model includes a constant current circuit 11, a mirrored current source circuit 12, a first voltage dividing circuit 13, a second voltage dividing circuit 14, a circuit output terminal HVIL-OUT, a circuit input terminal HVIL-IN, a first sampling terminal AD1, and a second sampling terminal AD2.
The constant current circuit 11 is configured to receive the first power supply signal VCC1 and generate a constant current having a constant current value. In an embodiment, the first power signal VCC1 may provide a stable 3.3V power supply voltage for the constant current circuit 11, and it is understood that in other embodiments, the first power signal VCC1 with different power supply voltages may be selected according to actual requirements, which is not limited herein.
The mirror current source circuit 12 includes a first mos transistor Q1 and a second mos transistor Q2, the gates of the first mos transistor Q1 are connected to each other, the source of the first mos transistor Q1 receives the second power supply signal VCC2 through the first resistor R1, the source of the second mos transistor Q2 receives the second power supply signal VCC2 through the second resistor R2, and the drain of the first mos transistor Q1 is connected to the constant current circuit 11 and the gates of the second mos transistor Q2. The first mos transistor Q1 is configured to receive a constant current and map the constant current to the second mos transistor Q2 such that the constant current flows through the second mos transistor Q2. The hardware parameters of the first mos transistor Q1 and the second mos transistor Q2 are the same, in an embodiment, the second power signal VCC2 may be used to provide a stable 12V supply voltage for the mirror current source circuit 12, and it is understood that in other embodiments, the second power signal VCC2 with different supply voltages may be selected according to actual requirements, which is not limited herein.
The circuit output end HVIL-OUT and the circuit input end HVIL-IN are used for being respectively connected with a high-voltage loop to be detected (not shown IN the figure) so as to realize electric connection through the high-voltage loop to be detected, and the circuit output end HVIL-OUT is connected with the drain electrode of the second mos tube Q2.
The first sampling terminal AD1 is connected to the drain of the second mos transistor Q2 through the first voltage dividing circuit 13, and is configured to be connected to a data collecting terminal of an external processor (not shown in the drawing), so that the external processor collects the first voltage output by the first voltage dividing circuit 13 through the first sampling terminal AD 1.
The second sampling end AD2 is connected to the circuit input end HVIL-IN through the second voltage dividing circuit 14, and is configured to be connected to a data collecting end of the external processor, so that the external processor collects the second voltage output by the second voltage dividing circuit 14 through the second sampling end AD2, and determines whether the high voltage loop to be detected has a fault based on the first voltage and the second voltage.
The constant current circuit and the mirror current source circuit are arranged, so that the current in the high-voltage interlocking circuit is constant, the characteristics of high output current precision, high stability and strong anti-interference capability are achieved, and the problems of low identification degree and poor anti-interference capability of the high-voltage interlocking circuit in the current market are solved. On the basis, the first voltage and the second voltage are utilized to carry out fault judgment of the high-voltage loop, so that the reference precision of the voltage value can be ensured, and the precision of fault detection of the high-voltage loop is improved. And the external processor can directly acquire fault parameters (namely the first voltage and the second voltage) of the high-voltage loop through the sampling port, and can realize continuous and efficient high-voltage loop state monitoring, so that the high-voltage relay can be disconnected in time to protect the system safety when the high-voltage loop fails in connection, and the real-time performance is higher and the safety is higher. In addition, the high-voltage interlock circuit in this embodiment is lower in cost than the conventional way of outputting PWM waves to detect the high-voltage interlock circuit.
In one embodiment, as shown in fig. 4, the constant current circuit 11 includes a first triode V1, a third resistor R3, a fourth resistor R4, a fifth resistor R5, and a first filter capacitor C1. The collector of the first triode V1 is connected with the drain of the first mos tube Q1; one end of the third resistor R3 is connected with the emitter of the first triode V1, and the other end of the third resistor R3 is grounded; one end of a fourth resistor R4 receives a first power supply signal VCC1, and the other end of the fourth resistor R4 is connected with the base electrode of the first triode V1; one end of the fifth resistor R5 is connected with the other end of the fourth resistor R4 and the base electrode of the first triode V1, and the other end of the fifth resistor R5 is grounded; one end of the first filter capacitor C1 is connected with the base electrode of the first triode V1 and the other end of the fourth resistor R4, and the other end of the first filter capacitor C1 is grounded.
Taking the first power supply signal VCC1 as 3.3V, the resistance of the third resistor R3 as 210 Ω, the resistance of the fourth resistor R4 as 3.3kΩ, and the resistance of the fifth resistor R5 as 10kΩ as an example, the voltage of 3.3V is divided by the fourth resistor R4 and the fifth resistor R5 to provide the bias voltage for the first triode V1, so that the current value of the collector current of the first triode V1 is stabilized at 10mA, i.e. a constant current with a current value of 10mA is generated.
In an embodiment, as shown in fig. 5, the first voltage dividing circuit 13 may include a sixth resistor R6 and a seventh resistor R7, wherein one end of the sixth resistor R6 is connected to the drain of the second mos transistor Q2 and the circuit output terminal HVIL-OUT, and the other end of the sixth resistor R6 is connected to the first sampling terminal AD 1; one end of the seventh resistor R7 is connected to the other end of the sixth resistor R6 and the first sampling end AD1, and the other end of the seventh resistor R7 is grounded. The second voltage dividing circuit 14 may include an eighth resistor R8 and a ninth resistor R9, wherein one end of the eighth resistor R8 is connected to the circuit input HVIL-IN, and the other end of the eighth resistor R8 is connected to the second sampling terminal AD 2; one end of the ninth resistor R9 is connected to the other end of the eighth resistor R8 and the second sampling end AD2, and the other end of the ninth resistor R9 is grounded.
In an embodiment, the voltage dividing ratio of the first voltage dividing circuit 13 and the second voltage dividing circuit 14 may be the same, that is, the resistance values of the sixth resistor R6 and the eighth resistor R8 are the same, the resistance values of the seventh resistor R7 and the ninth resistor R9 are the same, and the voltage values of the first voltage and the second voltage obtained by dividing the first voltage dividing circuit 13 and the second voltage dividing circuit 14 are also the same. At this time, the processor may be configured to perform fault judgment by using a difference value between the first voltage and the second voltage, and determine that the high-voltage loop to be detected has a fault when the difference value between the first voltage and the second voltage does not fall within a preset difference value range; and when the difference value of the first voltage and the second voltage falls within a preset difference value range, determining that the high-voltage loop to be detected has no fault. It will be appreciated that the value of the preset difference range may be set smaller to indicate that the first voltage and the second voltage are similar, and the specific value is set according to the actual requirement, which is not limited herein.
Taking the constant current as 10mA, the resistances of the sixth resistor R6 and the eighth resistor R8 as 33kΩ, the resistances of the seventh resistor R7 and the ninth resistor R9 as 7.5kΩ as an example, the current flowing through the sources of the first mos transistor Q1 and the second mos transistor Q2 is substantially constant at 10mA, at this time, the output current of the circuit output terminal HVIL-OUT is 10mA, and the sixth resistor R6 and the seventh resistor R7 in the first voltage dividing circuit 13 form 7.5:40.5, and the first voltage obtained by dividing is 2.15V. Similarly, the second voltage divided by the second voltage dividing circuit 14 is also 2.15V, so that when the difference between the second voltages of the first voltage is detected to be too large, it is indicated that the connection fault may occur IN the high voltage circuit to be detected between the circuit output terminal HVIL-OUT and the circuit input terminal HVIL-IN; and when the difference value falls within a preset difference value range, indicating that the high-voltage circuit to be detected has no fault.
In an embodiment, as shown in fig. 6, the high voltage interlock circuit 10 further includes a switch circuit 15, where the switch circuit 15 is connected to the second power signal VCC2, the control terminal EN of the external processor, and the mirror current source circuit 12, and is configured to turn on a path between the second power signal VCC2 and the mirror current source circuit 12 after receiving the start control signal output by the external processor, so as to turn on the high voltage interlock circuit 10 to detect a to-be-detected high voltage loop.
The switching circuit 15 includes a second triode V2 and a third triode V3, wherein an emitter of the second triode V2 receives a second power supply signal VCC2, and a collector of the second triode V2 is connected with a source of the second mos transistor Q2 and a source of the first mos transistor Q1 through a second resistor R2 and a first resistor R1, respectively; the collector of the third triode V3 is connected with the base electrode of the second triode V2, the emitter electrode of the third triode V3 is grounded, and the base electrode of the third triode V3 is connected with the control end EN of the external processor. The external controller can control the conduction of the second triode V2 and the third triode V3 by outputting a high-level start control signal, and can not output the start control signal when the high-voltage interlocking circuit 10 is not required to be started, so that the aim of low power consumption is fulfilled.
It will be appreciated that the resistors connected at the base and collector of the second transistor V2 and the third transistor V3 shown in fig. 6 are collector resistors and pull-down resistors corresponding to the transistors, respectively, and the second transistor V2 and the third transistor V3 are assisted to realize a switching function, which may be integrated inside the transistor or connected outside the transistor, and are not limited herein.
In an embodiment, as shown in fig. 7, the high voltage interlock circuit 10 further includes a second filter capacitor C2, a third filter capacitor C3, a fourth filter capacitor C4 and a fifth filter capacitor C5, so as to utilize each filter capacitor to filter out an external interference signal, thereby further improving the anti-interference capability of the circuit and further improving the accuracy of high voltage loop fault detection.
One end of the second filter capacitor C2 is connected with the drain electrode of the second mos tube Q2 and the circuit output end HVIL-OUT, and the other end of the second filter capacitor C2 is grounded; one end of the third filter capacitor C3 is connected with the first sampling end AD1 and the first voltage dividing circuit 13, and the other end of the third filter capacitor C3 is grounded; one end of the fourth filter capacitor C4 is connected with the power input end and the second voltage dividing circuit 14, and the other end of the fourth filter capacitor C4 is grounded; one end of the fifth filter capacitor C5 is connected to the second sampling end AD2 and the second voltage dividing circuit 14, and the other end of the fifth filter capacitor C5 is grounded.
In an embodiment, as shown in fig. 8, the high voltage interlock circuit 10 may further include a short circuit protection circuit 16, wherein the short circuit protection circuit 16 may include a fourth transistor V4, a tenth resistor R10, a fifth transistor V5, and an eleventh resistor R11. The collector of the fourth triode V4 is connected with the second voltage dividing circuit 14 and the circuit input end HVIL-IN; one end of the tenth resistor R10 is connected with the emitter of the fourth triode V4, and the other end of the tenth resistor R10 is grounded; the base electrode of the fifth triode V5 is connected with one end of a tenth resistor R10 and the emitter electrode of the fourth triode V4, the collector electrode of the fifth triode V5 is connected with the base electrode of the fourth triode V4, and the emitter electrode of the fifth triode V5 is grounded; one end of the eleventh resistor R11 is connected to the collector of the fifth triode V5 and the base of the fourth triode V4, and the other end of the eleventh resistor R11 is connected to the control end EN of the external controller.
IN one embodiment, as shown IN fig. 8, the high voltage interlock circuit 10 may further include a current limiting resistor R12, where one end of the current limiting resistor R12 is connected to the second voltage dividing circuit 14 and the circuit input HVIL-IN, and the other end of the current limiting resistor R12 is connected to the collector of the fourth triode V4. In an embodiment, the resistance of the tenth resistor R10 may be 40.2Ω, the resistance of the eleventh resistor R11 may be 10kΩ, and the resistance of the current limiting resistor R12 may be 200Ω, so as to perform the current limiting function.
In an embodiment, as shown in fig. 8, the high voltage interlock circuit 10 may further include a diode D1, wherein one end of the diode D1 is connected to the drain of the second mos transistor Q2, and the other end of the diode D1 is connected to the first voltage dividing circuit 13 and the circuit output terminal HVIL-OUT, so as to achieve a reverse connection preventing function by using the reverse cut-off function of the diode D1, thereby further improving the safety of the circuit.
In an embodiment, the resistors set in the high-voltage interlocking circuit 10 may be metal film resistors with 0.1% precision, and the resistors have the characteristics of high thermal stability and high reliability, so that the stability of the circuit can be improved, and the service life of the circuit can be prolonged.
According to the embodiment, the switch circuit is arranged, so that the autonomous switch control of the high-voltage interlocking circuit can be realized by using the external controller, and the effect of low power consumption is realized. And through setting up a plurality of filter capacitors, can utilize each filter capacitor to filter external interference signal, further improve the interference killing feature of circuit to improve the precision of high-voltage circuit fault detection. In addition, by arranging the short-circuit protection circuit and the current limiting resistor, the safety and stability of the circuit can be further ensured.
The foregoing is a preferred embodiment of the present utility model and it should be noted that modifications and adaptations to those skilled in the art may be made without departing from the principles of the present utility model and are intended to be comprehended within the scope of the present utility model.
Claims (10)
1. A high voltage interlock circuit comprising:
the constant current circuit is used for receiving the first power supply signal and generating constant current with constant current value;
The mirror current source circuit comprises a first mos tube and a second mos tube, wherein grid electrodes of the first mos tube are connected with each other, a source electrode of the first mos tube receives a second power supply signal through a first resistor, a source electrode of the second mos tube receives the second power supply signal through a second resistor, a drain electrode of the first mos tube is connected with the constant current circuit and a grid electrode of the first mos tube, and is used for receiving the constant current and mapping the constant current to the second mos tube so that the constant current flows through the second mos tube;
The circuit output end and the circuit input end are respectively connected with the to-be-detected high-voltage loop so as to realize electric connection through the to-be-detected high-voltage loop, and the circuit output end is connected with the drain electrode of the second mos tube;
The first sampling end is connected with the drain electrode of the second mos tube through a first voltage dividing circuit and is used for being connected with the data acquisition end of an external processor, so that the external processor acquires the first voltage output by the first voltage dividing circuit through the first sampling end;
The second sampling end is connected with the circuit input end through a second voltage dividing circuit and is used for being connected with the data acquisition end of the external processor, so that the external processor acquires second voltage output by the second voltage dividing circuit through the second sampling end, and whether the to-be-detected high-voltage loop fails or not is determined based on the first voltage and the second voltage.
2. The high voltage interlock circuit of claim 1 wherein the constant current circuit comprises:
The collector of the first triode is connected with the drain electrode of the first mos tube;
One end of the third resistor is connected with the emitter of the first triode, and the other end of the third resistor is grounded;
One end of the fourth resistor receives the first power supply signal, and the other end of the fourth resistor is connected with the base electrode of the first triode;
One end of the fifth resistor is connected with the other end of the fourth resistor and the base electrode of the first triode, and the other end of the fifth resistor is grounded;
And one end of the first filter capacitor is connected with the base electrode of the first triode and the other end of the fourth resistor, and the other end of the first filter capacitor is grounded.
3. The high voltage interlock circuit of claim 1 wherein the first voltage divider circuit comprises:
One end of the sixth resistor is connected with the drain electrode of the second mos tube and the output end of the circuit, and the other end of the sixth resistor is connected with the first sampling end;
One end of the seventh resistor is connected with the other end of the sixth resistor and the first sampling end, and the other end of the seventh resistor is grounded;
the second voltage dividing circuit includes:
One end of the eighth resistor is connected with the circuit input end, and the other end of the eighth resistor is connected with the second sampling end;
And one end of the ninth resistor is connected with the other end of the eighth resistor and the second sampling end, and the other end of the ninth resistor is grounded.
4. The high voltage interlock circuit of claim 1 further comprising a switching circuit connected to the second power supply signal, the control terminal of the external processor, and the mirrored current source circuit for turning on a path between the second power supply signal and the mirrored current source circuit upon receipt of a start control signal output by the external processor;
Wherein the switching circuit comprises:
The emitting electrode of the second triode receives the second power supply signal, and the collecting electrode of the second triode is connected with the source electrode of the second mos tube and the source electrode of the first mos tube through the second resistor and the first resistor respectively;
And the collector electrode of the third triode is connected with the base electrode of the second triode, the emitting electrode of the third triode is grounded, and the base electrode of the third triode is connected with the control end of the external processor.
5. The high voltage interlock circuit of claim 1 further comprising a short circuit protection circuit wherein the short circuit protection circuit comprises:
the collector electrode of the fourth triode is connected with the second voltage dividing circuit and the circuit input end;
A tenth resistor, wherein one end of the tenth resistor is connected with the emitter of the fourth triode, and the other end of the tenth resistor is grounded;
The base electrode of the fifth triode is connected with one end of the tenth resistor and the emitter electrode of the fourth triode, the collector electrode of the fifth triode is connected with the base electrode of the fourth triode, and the emitter electrode of the fifth triode is grounded;
And one end of the eleventh resistor is connected with the collector electrode of the fifth triode and the base electrode of the fourth triode, and the other end of the eleventh resistor is connected with the control end of the external processor.
6. The high voltage interlock circuit of claim 5 further comprising a current limiting resistor having one end connected to the second voltage divider circuit and the circuit input and the other end connected to the collector of the fourth transistor.
7. The high voltage interlock circuit of claim 1 wherein the high voltage interlock circuit further comprises:
one end of the second filter capacitor is connected with the drain electrode of the second mos tube and the output end of the circuit, and the other end of the second filter capacitor is grounded;
one end of the third filter capacitor is connected with the first sampling end and the first voltage dividing circuit, and the other end of the third filter capacitor is grounded;
One end of the fourth filter capacitor is connected with the circuit input end and the second voltage dividing circuit, and the other end of the fourth filter capacitor is grounded;
And one end of the fifth filter capacitor is connected with the second sampling end and the second voltage dividing circuit, and the other end of the fifth filter capacitor is grounded.
8. A high voltage interlock comprising a high voltage interlock circuit, wherein the high voltage interlock circuit is the high voltage interlock circuit of any one of claims 1-7.
9. A high voltage loop detection system, comprising:
the high-voltage interlocking device is the high-voltage interlocking device described in the claim 8, and is used for detecting a high-voltage loop to be detected and outputting a first voltage and a second voltage;
And the processor is connected with the high-voltage interlocking device and is used for collecting the first voltage and the second voltage and determining whether the to-be-detected high-voltage loop fails or not based on the first voltage and the second voltage.
10. The high voltage loop detection system of claim 9, wherein the processor is configured to determine that the high voltage loop to be detected is malfunctioning when a difference between the first voltage and the second voltage does not fall within a predetermined difference range.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202322157379.4U CN220855147U (en) | 2023-08-11 | 2023-08-11 | High-voltage interlocking circuit, device and high-voltage loop detection system |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202322157379.4U CN220855147U (en) | 2023-08-11 | 2023-08-11 | High-voltage interlocking circuit, device and high-voltage loop detection system |
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| CN220855147U true CN220855147U (en) | 2024-04-26 |
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| CN202322157379.4U Active CN220855147U (en) | 2023-08-11 | 2023-08-11 | High-voltage interlocking circuit, device and high-voltage loop detection system |
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