CN220822623U

CN220822623U - DC power supply protection circuit

Info

Publication number: CN220822623U
Application number: CN202322401038.7U
Authority: CN
Inventors: 白辰宇
Original assignee: Prophet Electronic Technology Corp ltd
Current assignee: Prophet Electronic Technology Corp ltd
Priority date: 2023-09-05
Filing date: 2023-09-05
Publication date: 2024-04-19
Anticipated expiration: 2033-09-05

Abstract

The utility model provides a DC power supply protection circuit, comprising: EDS protection circuit; the ADM1270 chip circuit is electrically connected with the EDS protection circuit and used for overvoltage protection, undervoltage protection and overcurrent protection; and TMP390-Q1 chip circuit, electrically connected to said ADM1270 chip circuit and said EDS protection circuit for over-temperature protection. The utility model provides a DC power supply protection circuit which has obvious advantages in reliability, simplicity and cost, can continuously endure large current and realizes ESD protection, overvoltage protection, undervoltage protection, overcurrent protection and overtemperature protection.

Description

DC power supply protection circuit

Technical Field

The utility model relates to the technical field of electronic equipment, in particular to a DC power supply protection circuit.

Background

In the electronics industry, power supply problems have been one of the concerns. In computer motherboard products, power output problems often mean catastrophic results; for example, the power supply voltage or current is continuously too high, which can cause excessive power consumption of the main board, and the components continuously generate serious heat. Even if the power failure is not timely processed, the components are burned and fried, the main board catches fire, and the personal safety is endangered. Therefore, power protection design should be given high importance.

Current power protection schemes are mostly used in a scenario below 10A operating current, and may fail when encountering a scenario of greater operating current.

Disclosure of utility model

The utility model aims to overcome the problems in the prior art and provide a DC power supply protection circuit which can continuously withstand large current and realize ESD protection, overvoltage protection, undervoltage protection, overcurrent protection and over-temperature protection.

In order to achieve the technical purpose and the technical effect, the utility model is realized by the following technical scheme:

The utility model provides a DC power supply protection circuit, comprising:

EDS protection circuit;

The ADM1270 chip circuit is electrically connected with the EDS protection circuit and used for overvoltage protection, undervoltage protection and overcurrent protection; and

TMP390-Q1 chip circuit, electric connection is in the ADM1270 chip circuit and the EDS protection circuit is used for the over temperature protection.

In one embodiment of the utility model, the EDS protection circuit includes:

A fuse electrically connected to the ADM1270 chip circuit; and

One end of the TVS diode D1 is connected with the fuse, and the other end of the TVS diode D1 is grounded.

In one embodiment of the utility model, the ADM1270 chip circuit comprises:

An ADM1270 chip electrically connected with the fuse; and

And the peripheral circuits of the ADM1270 chip are electrically connected with the ADM1270 chip.

In one embodiment of the present utility model, the TMP390-Q1 chip circuit comprises:

a TMP390-Q1 chip electrically connected to said ADM1270 chip; and

TMP390-Q1 chip peripheral circuitry electrically connected to said TMP390-Q1 chip and said ADM1270 chip peripheral circuitry.

In one embodiment of the present utility model, the ADM1270 chip peripheral circuit includes a resistor R1, a resistor R2, a resistor R3, a resistor R5, and an NMOS transistor Q1, where the resistor R1, the resistor R2, the resistor R3, the resistor R5, and the NMOS transistor Q1 are electrically connected.

In one embodiment of the present utility model, the TMP390-Q1 chip peripheral circuit comprises a resistor R4 and an NMOS transistor Q2, wherein the resistor R4 is electrically connected with the NMOS transistor Q2.

In summary, the present utility model provides a DC power protection circuit, which is composed of a pure hardware circuit, and does not include any software control components (such as MCU, CPLD, etc.), compared with the power protection scheme relying on a software control chip, the scheme has obvious advantages in reliability, simplicity and cost, and can continuously withstand large current, thereby implementing ESD protection, overvoltage protection, undervoltage protection, overcurrent protection and over-temperature protection.

Drawings

The accompanying drawings, which are included to provide a further understanding of the utility model and are incorporated in and constitute a part of this specification, illustrate embodiments of the utility model and together with the description serve to explain the utility model and do not constitute a limitation on the utility model. In the drawings:

FIG. 1 is a schematic block diagram of the overall structure of the present utility model;

FIG. 2 is a typical application configuration of the ADM1270 chip of the present utility model;

FIG. 3 is a schematic diagram of a typical application configuration of a TMP390-Q1 chip of this utility model;

fig. 4 is a basic logic flow diagram of the present utility model.

Detailed Description

The utility model will be described in detail below with reference to the drawings in combination with embodiments.

Referring to fig. 1, the present utility model provides a DC power protection circuit, which can continuously withstand a large current, and realize ESD protection, overvoltage protection, undervoltage protection, overcurrent protection and over-temperature protection. Specifically, the DC power supply protection circuit comprises an EDS protection circuit, an ADM1270 chip circuit and a TMP390-Q1 chip circuit, wherein the EDS protection circuit comprises a fuse and a TVS diode D1, and the fuse is electrically connected with the ADM1270 chip circuit. One end of the TVS diode D1 is connected with the fuse, and the other end of the TVS diode D1 is grounded. The 12V DC voltage is input and then passes through the fuse first, and once the input current is overlarge, the fuse is fused, so that the whole link is cut off, and the effects of short circuit and overcurrent protection are achieved. The rear stage of the fuse is reversely connected with a TVS diode with reverse breakdown voltage of 40V to the ground, and when the input transient voltage is too high (more than 40V), the TVS diode can reversely break down, so that all current is released to the ground, and the effect of ESD protection is achieved.

Referring to fig. 1, in one embodiment of the present utility model, the ADM1270 chip circuit is electrically connected to an EDS protection circuit for over-voltage protection, under-voltage protection, and over-current protection. The ADM1270 chip circuitry includes an ADM1270 chip and ADM1270 chip peripheral circuitry, the ADM1270 chip being electrically connected to the fuse. ADM1270 is a protection chip with OVP, UVP, OCP and delayed turn-off protection functions. A typical chip application configuration is shown in fig. 2. The resistance values of the R6, R7 and R8 resistors are selected to determine the voltage values obtained by dividing the UV pin and the OV pin, so that the voltage values are respectively compared with 1V of the comparator to determine whether the power supply voltage has overvoltage or undervoltage phenomena. When the voltage of the UV pin is lower than 1V, or the voltage of the OV pin is higher than 1V, the GATE pin is pulled up from a low level to 12V. Combining the common resistance values in the market, and selecting the R6 resistance value of 24.9KΩ, the R2 resistance value of 1KΩ and the R8 resistance value of 2KΩ after calculation according to the partial pressure. ovp=13.95V, uvp=9.3V was determined as such. The Rsense resistor is a current sampling resistor connected in series between the sense+ and SENSE-pins of the chip. ADM1270 determines the value of the current flowing through the resistor by detecting the voltage drop across the resistor, and compares the detected voltage drop with a reference voltage on the inside of the chip to detect if there is an overcurrent. Since the default input reference voltage value Vsense in the chip is 50mV (which can be adjusted according to the use condition of the user), if Rsense selects a precision resistor with a resistance value of 0.0025Ω, an overcurrent protection effect with a threshold value of 20A can be achieved. When the chip detects an overcurrent event, the GATE pin is pulled up to 12V from a low level after a certain delay time is determined by the capacitance value of the capacitor Ctimer of the Timer pin. The capacitance of Ctimer is determined according to the overcurrent turn-off delay ton required by a user, the overcurrent turn-off delay can effectively prevent accidental turn-off caused by transient overcurrent and surge current, and the GATE pin can be pulled up only when an overcurrent event with duration longer than ton is detected by a chip. The delay time set in the scheme is 1ms. The capacitance value Ctimer can be calculated according to equation 1 to be chosen as 10nF. (Vtimerh defaults to 2V).

Equation 1

The VCAP pin continuously outputs 3.6V of electricity, and can supply power for the TMP390-Q1 chip power supply. The values of the turn-off delay can be adjusted according to different use scenes. The peripheral circuits of the ADM1270 chip are electrically connected to the ADM1270 chip. The ADM1270 chip peripheral circuit includes a resistor R1, a resistor R3, a resistor R5, and an NMOS Q1, where the resistor R1, the resistor R3, the resistor R5, and the NMOS Q1 are electrically connected.

Referring to FIG. 1, in one embodiment of the present utility model, the TMP390-Q1 chip circuit is electrically connected to the ADM1270 chip circuit and the EDS protection circuit for over-temperature protection. The TMP390-Q1 chip circuit comprises a TMP390-Q1 chip and a TMP390-Q1 chip peripheral circuit, wherein the TMP390-Q1 chip is electrically connected with the ADM1270 chip. TMP390-Q1 is a protection chip with over-temperature and under-temperature dual channels, the temperature detection range is-50 ℃ -124 ℃, the over-temperature protection function is used in the scheme, the typical application configuration of single-channel over-temperature protection is shown in figure 3, the normal state OUT pin outputs 3.9V voltage, when the chip detects that the temperature exceeds the threshold value of 124 ℃, the OUTA pin is pulled down to 0V, the chip has hysteresis of 10 ℃, and when the chip detects that the temperature falls below 114 ℃, the OUT pin is pulled up to 3.9V again. The temperature threshold of the over-temperature protection can be modified by adjusting the serial resistance values of the SETA pin and the SETB pin. The peripheral circuitry of the TMP390-Q1 chip is electrically connected to the peripheral circuitry of the TMP390-Q1 chip and the ADM1270 chip. The peripheral circuit of the TMP390-Q1 chip comprises a resistor R4 and an NMOS tube Q2, and the resistor R4 is electrically connected with the NMOS tube Q2.

Referring to fig. 1 and 4, when Vgs of the NMOS Q1 is not less than the on voltage (3V), Q1 is in the on state, vout is turned on with GND, so that vout=0v, and the purpose of cutting off the load and the power supply is achieved. When Vgs < on voltage (3V) of Q1, Q1 is in an off state, and the 12V power supply voltage is all output to the load Vout, vout=12v, i.e., the latter stage load operates normally. The value of Vgs is commonly controlled by both the ADM1270 and TMP390-Q1 chips. When the supply voltage and current are in the normal operating range, the GATE pin of the ADM1270 chip remains low level output, vgate=0v; when the ADM1270 chip detects that the supply voltage exceeds the OVP threshold (13.95V) or is below the UVP threshold (9.3V) or exceeds the OCP threshold (20A), the GATE pin will pull high, vgate=12v. Also according to TMP390-Q1 chip manual, when the temperature is within the normal range of values, vtemp is high (3.9V); when the temperature is above the set threshold, vtemp will pull down to 0V. The switching states of Q1 and Q2 are controlled according to the logic described above. According to the different fault modes, the following four states can be divided together:

Referring to fig. 4, state one: voltage, current and temperature are all in the normal range

In this state, GATE pin of ADM1270 is low, vgate=0v; the OUT pin of TMP390-Q1 is high and vout=3.9v. At this time, vgs=3.9v > of Q2 turns on the voltage 3V, Q2 so that the gate of Q1 turns on with ground while Vgate is at a low level, and thus vgs=0v, Q1 is in an off state. When Q1 is off, vin of 12V passes directly through the R1 current to Vout, so vout=12v, i.e. the load is in normal operation.

Referring to fig. 4, state two: the voltage and current are normal, the temperature is not in the normal range

In this state, GATE pin of ADM1270 is low, vgate=0v; TMP390-Q1 detects an over temperature and pulls the OUT pin low, at which point vout=0v, so vgs=0v for Q2, Q2 turns off, allowing 12V Vin to flow through R3 and R5 onto the gate link of Q1. Since vgate=0v, the gate voltage of Q1 is 8V after dividing 12V according to R2, R5, R3, i.e. vgs=8v > 3V, Q1 is turned on. When Q1 is on, vout is on with ground, vout=0v, i.e., the load terminal stops operating, and the power supply terminal is off.

Referring to fig. 4, state three: the voltage or current is not in the normal range and the temperature is normal

In this state, the GATE pin of ADM1270 is pulled high, vgate=12v, due to detection of OVP or UVP or OCP anomalies; the OUT pin of TMP390-Q1 is high and vout=3.9v. At this time, vgs=3.9v > of Q2 turns on voltage 3V, Q2 turns on, so 12V electricity of Vgate flows into ground through R2, R5. After the voltage division of R2 and R5, the gate voltage of Q1 is 6V, namely Vgs=6V > 3V, and Q1 is conducted. When Q1 is on, vout is on with ground, vout=0v, i.e., the load terminal stops operating, and the power supply terminal is off.

Referring to fig. 4, state four: the voltage or current is not in the normal range and the temperature is not in the normal range

In this state, the GATE pin of ADM1270 is pulled high, vgate=12v, due to detection of OVP or UVP or OCP anomalies; TMP390-Q1 detects an over temperature and pulls the OUT pin low, at which point vout=0v, so vgs=0v for Q2, Q2 turns off, allowing 12V Vin to flow through R3 and R5 onto the gate link of Q1. At the same time vgate=12v, so the gate voltage of Q1 is also 12V, i.e. vgs=12v of Q1, Q1 is on. Vout is on with ground, vout=0v, i.e. the load side is inactive, and the power supply side is off. The threshold value of overvoltage protection and undervoltage protection and overcurrent protection can be determined according to the peripheral circuit resistance value of the ADM1270 chip, and the temperature threshold value of overtemperature protection can be determined according to the peripheral circuit resistance value of the TMP390-Q1 chip.

In summary, the present utility model provides a DC power protection circuit, which selects a switch for controlling an NMOS transistor to protect the circuit, when a load is in a normal working state, the Q1 NMOS transistor is in an off state, the power supply current does not flow through the Q1, and only when a fault state occurs, the Q1 is turned on, so that the design can effectively avoid that the NMOS transistor continuously flows through a large current, and reduce the hidden trouble of the MOS transistor, meanwhile, compared with the PMOS transistor, the RDS (on) value of the NMOS transistor is much lower, which means that when the fault occurs, the Q1 is conducted and flows through a large current, the power consumption of the Q1 is also greatly reduced compared with the PMOS, so that the scheme can be applied to a use field with a relatively large power supply current, and the DC power protection circuit is composed of a pure hardware circuit, and does not include any software control components (such as MCU and CPLD).

The foregoing has shown and described the basic principles, principal features and advantages of the utility model. It will be understood by those skilled in the art that the present utility model is not limited to the embodiments described above, and that the above embodiments and descriptions are merely illustrative of the principles of the present utility model, and various changes and modifications may be made without departing from the spirit and scope of the utility model, which is defined in the appended claims.

Claims

1. A DC power protection circuit, the circuit comprising:

EDS protection circuit;

2. The DC power protection circuit of claim 1, wherein the EDS protection circuit comprises:

A fuse electrically connected to the ADM1270 chip circuit; and

3. The DC power protection circuit of claim 2, wherein said ADM1270 chip circuit comprises:

An ADM1270 chip electrically connected with the fuse; and

4. The DC power protection circuit of claim 1, wherein the TMP390-Q1 chip circuit comprises:

a TMP390-Q1 chip electrically connected to said ADM1270 chip; and

5. The DC power protection circuit of claim 1, wherein the ADM1270 chip peripheral circuit comprises a resistor R1, a resistor R2, a resistor R3, a resistor R5, and an NMOS transistor Q1, wherein the resistor R1, the resistor R2, the resistor R3, the resistor R5, and the NMOS transistor Q1 are electrically connected.

6. The DC power protection circuit of claim 1, wherein the TMP390-Q1 chip peripheral circuit includes a resistor R4 and an NMOS transistor Q2, the resistor R4 being electrically connected to the NMOS transistor Q2.