CN220774377U - Nitride-based semiconductor device - Google Patents

Abstract

The embodiment of the utility model discloses a nitride-based semiconductor device, which comprises: a substrate; a first nitride semiconductor layer located at one side of the substrate; a second nitride semiconductor layer located on a side of the first nitride semiconductor layer away from the substrate and having a band gap different from that of the first nitride semiconductor layer; a first electrode located on a side of the second nitride semiconductor layer away from the substrate; a gate structure located at a side of the second nitride semiconductor layer away from the substrate and surrounding the first electrode; a second electrode located at a side of the second nitride semiconductor layer away from the substrate and surrounding the gate electrode; and a back surface through hole penetrating the first nitride semiconductor layer and the second nitride semiconductor layer, wherein a conductive structure is arranged in the back surface through hole, a first end of the conductive structure is in contact connection with the substrate, and a second end of the conductive structure is in contact connection with the first electrode or the second electrode. The reliability of the nitride-based semiconductor device is improved.

Description

Nitride-based semiconductor device

Technical Field

The embodiment of the utility model relates to the technical field of semiconductors, in particular to a nitride-based semiconductor device.

Background

Nitride-based semiconductor devices utilize a heterojunction interface between two materials having different bandgaps to form a quantum well-like structure that accommodates a two-dimensional electron gas region, thereby meeting the requirements of high power/frequency devices. Currently, in order to meet more design requirements, nitride-based semiconductor devices are required to be smaller. Therefore, in the case of miniaturization of the nitride-based semiconductor device, it is necessary to secure reliability of the nitride-based semiconductor device.

Disclosure of Invention

The embodiment of the utility model provides a nitride-based semiconductor device, which is used for improving the reliability of the nitride-based semiconductor device.

According to an aspect of an embodiment of the present utility model, there is provided a nitride-based semiconductor device including:

a substrate;

a first nitride semiconductor layer located at one side of the substrate;

a second nitride semiconductor layer located at a side of the first nitride semiconductor layer away from the substrate and having a band gap different from that of the first nitride semiconductor layer to form a heterojunction having two-dimensional electron gas between the first nitride semiconductor layer and the second nitride semiconductor layer;

a first electrode located at a side of the second nitride semiconductor layer away from the substrate;

a gate structure located at a side of the second nitride semiconductor layer away from the substrate and surrounding the first electrode;

a second electrode located at a side of the second nitride semiconductor layer away from the substrate and surrounding the gate structure; the second electrode is arranged on one side of the grid structure far away from the first electrode;

and the back through hole penetrates through the first nitride semiconductor layer and the second nitride semiconductor layer, a conductive structure is arranged in the back through hole, a first end of the conductive structure is in contact connection with the substrate, and a second end of the conductive structure is electrically connected with the first electrode or in contact connection with the second electrode.

Optionally, the number of the first electrodes is multiple, and the multiple first electrodes are arranged on the surface of the second nitride semiconductor layer, which is far away from the substrate, at intervals;

the number of the gate structures is a plurality, and the number of the gate structures is the same as the number of the first electrodes; each grid structure is correspondingly arranged around one first electrode;

the number of the second electrodes is a plurality, and the number of the second electrodes is the same as the number of the gate structures; each second electrode is correspondingly arranged around one grid structure;

and the second electrodes are positioned between two adjacent grid structures and are shared, and a plurality of second electrodes are interwoven into a net structure.

Optionally, the shape of the orthographic projection of the first electrode on the substrate includes a circle, an ellipse, or a polygon;

the shape of the orthographic projection of the grid structure on the substrate comprises a circular ring shape, an elliptical ring shape or a polygonal ring shape;

the shape of the orthographic projection of the second electrode on the substrate comprises a circular ring shape, an elliptical ring shape or a polygonal ring shape.

Optionally, the first electrode is a source electrode, and the second electrode is a drain electrode; alternatively, the first electrode is a drain electrode, and the second electrode is a source electrode.

Optionally, a distance between the gate structure and the drain electrode is greater than a distance between the gate structure and the source electrode.

Optionally, the nitride-based semiconductor device further includes:

a passivation layer located on a side of the second nitride semiconductor layer away from the substrate and covering the gate structure, the first electrode, and the second electrode;

a field plate located in the passivation layer and disposed around the gate structure;

wherein the field plate is in a ladder shape; the field plate comprises a first field plate layer positioned above the grid structure, a second field plate layer positioned between the drain electrode and the grid structure, and an intermediate connecting part for connecting the first field plate layer and the second field plate layer.

Optionally, a second end of the conductive structure in the backside via is in contact with the source electrode; the orthographic projection of the back via on the substrate at least partially overlaps the orthographic projection of the source on the substrate.

Optionally, when the first electrode is a drain electrode and the second electrode is a source electrode, the orthographic projection of the back through hole on the substrate includes a circular ring shape, an elliptical ring shape or a polygonal ring shape.

Optionally, the nitride-based semiconductor device further includes:

a first electrode pad electrically connected to the first electrode with a first front-side via through at least one dielectric layer;

a second electrode pad electrically connected to the second electrode with a second front-side via through at least one dielectric layer;

and a gate pad electrically connected to the gate structure with a gate via through the at least one dielectric layer.

Optionally, the gate structure includes a third nitride semiconductor layer and a gate electrode; the third nitride semiconductor layer is located between the gate electrode and the second nitride semiconductor layer;

alternatively, the gate structure includes a gate insulating layer and a gate electrode; the gate insulating layer is located between the gate electrode and the second nitride semiconductor layer.

According to the technical scheme provided by the embodiment of the utility model, the grid structure and the second electrode are arranged into the annular structure, so that the size of the electrode structure can be adjusted, and the generation of a bare end surface falling outside the active area can be avoided; because the exposed end face is treated, the additional adverse effect can be generated on the device, the weakening of the grid control capability caused by the treatment of the exposed end face can be avoided, the possibility of electric leakage is reduced, the reliability of the device is improved, on the basis, the grounding of the first electrode or the second electrode is realized through the back through holes penetrating through the first nitride semiconductor layer and the second nitride semiconductor layer, and the whole film layer is thinner in the front section of the process due to the fact that the back through holes are formed, and excessively thick light resistance and long-time etching are not needed, so that the generation of polymers is reduced, and the reliability of the device is further improved.

It should be understood that the description in this section is not intended to identify key or critical features of the embodiments of the utility model or to delineate the scope of the utility model. Other features of the present utility model will become apparent from the description that follows.

Drawings

In order that those skilled in the art will better understand the present utility model, a technical solution in the embodiments of the present utility model will be clearly and completely described below with reference to the accompanying drawings in which it is apparent that the described embodiments are only some embodiments of the present utility model, not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the present utility model without making any inventive effort, shall fall within the scope of the present utility model.

It should be noted that the terms "first," "second," and the like in the description and the claims of the present utility model and the above figures are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged where appropriate such that the embodiments of the utility model described herein may be implemented in sequences other than those illustrated or otherwise described herein. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.

Fig. 1 is a schematic structural view of a nitride-based semiconductor device provided in the prior art;

FIG. 2 is a schematic cross-sectional view of the structure of FIG. 1 along section line AA 1;

FIG. 3 is a schematic diagram of a gate leakage in the structure of FIG. 1;

fig. 4 is a schematic structural view of a nitride-based semiconductor device according to an embodiment of the present utility model;

fig. 5 is a schematic cross-sectional structure of the structure shown in fig. 4 along a cross-sectional line BB 1;

fig. 6 is a schematic structural view of another nitride-based semiconductor device according to an embodiment of the present utility model;

FIG. 7 is a schematic cross-sectional view of the structure of FIG. 6 along section line CC 1;

fig. 8 is a schematic structural view of another nitride-based semiconductor device according to an embodiment of the present utility model;

fig. 9 is a schematic cross-sectional view of the structure shown in fig. 8 along the cross-sectional line DD 1.

Detailed Description

The utility model is described in further detail below with reference to the drawings and examples. It is to be understood that the specific embodiments described herein are merely illustrative of the utility model and are not limiting thereof. It should be further noted that, for convenience of description, only some, but not all of the structures related to the present utility model are shown in the drawings.

In recent years, intensive research on group III nitride-based semiconductor devices has been very widespread, especially in high-power switches and high-frequency applications. Group III nitride-based semiconductor devices utilize a heterojunction interface between two materials with different bandgaps to form a quantum-like well-like structure that accommodates a two-dimensional electron gas (two-dimensional electron gas,2 DEG) region that meets the requirements of high power/frequency devices. For example, heterojunction is formed with relatively wide bandgap materials such as AlGaN (aluminum gallium nitride) and relatively narrow bandgap materials such as GaN (gallium nitride).

Fig. 1 is a schematic structural diagram of a nitride-based semiconductor device provided in the prior art, fig. 2 is a schematic structural diagram of a cross-section along a sectional line AA1 of the structure shown in fig. 1, and referring to fig. 1 and 2, the nitride-based semiconductor device in the current main foundry mostly adopts a multi-gate finger structure, wherein a gate G, a source S and a drain D are in a strip shape, and the intervals among the gate G, the source S and the drain D can be automatically adjusted during layout design. But the striped gate G, source S and drain D have exposed end surfaces outside the active region, which causes edge effects to cause leakage in the off state of the gate. The solution that is commonly used at present is to add an IMP (Implant) process to form an ion implantation layer 1 as shown in fig. 1 and 2, break the edge 2DEG to prevent leakage and reduce the edge effect. However, because the IMP process is introduced, the side surfaces of the two ends of the gate G are damaged while the edge effect is solved, so that the control capability of the upper and lower ends of the gate D is reduced. Fig. 3 is a schematic diagram of the gate leakage in the structure shown in fig. 1, referring to fig. 3, when the gate G is in the off state with 0 potential, the leakage should be nearly 0, however, because of the damage of IMP, the gate G has a larger off state leakage on the side surfaces of the upper and lower ends, so as to affect the device performance. In addition, in the later stage of the process, in order to realize the grounding of the source electrode S, a preparation process of TGV (Through Glass Via, glass through hole) is performed, and the TGV penetrates from the front surface of the device to the substrate. However, since the overall film layer of the nitride epitaxial layer (EPI), the intermediate insulating layer (Inter Layer Dielectrics, ILD) and the In-Mold Decoration (IMD) on the substrate is thicker, a thicker photoresist is required to be selected, the etching time is longer, the polymer is heavier, defects are easily formed, the reliability of the device is affected, and the cost is higher.

In view of this, an embodiment of the present utility model provides a nitride-based semiconductor device, and fig. 4 is a schematic structural diagram of the nitride-based semiconductor device provided in the embodiment of the present utility model, and fig. 5 is a schematic sectional structural diagram of the structure shown in fig. 4 along a sectional line BB 1; referring to fig. 4 and 5, comprising:

a substrate 110;

a first nitride semiconductor layer 120 located at one side of the substrate 110;

a second nitride semiconductor layer 130 located at a side of the first nitride semiconductor layer 120 remote from the substrate 110 and having a band gap different from that of the first nitride semiconductor layer 120 to form a heterojunction having two-dimensional electron gas between the first nitride semiconductor layer 120 and the second nitride semiconductor layer 130;

a first electrode 10 located at a side of the second nitride semiconductor layer 130 remote from the substrate 110;

a gate structure 30 located at a side of the second nitride semiconductor layer 130 away from the substrate 110 and disposed around the first electrode 10;

a second electrode 20 located at a side of the second nitride semiconductor layer 130 away from the substrate 110 and disposed around the gate structure 30; the second electrode 20 is disposed on a side of the gate structure 30 remote from the first electrode 10;

the back surface via hole 40 penetrates the first nitride semiconductor layer 120 and the second nitride semiconductor layer 130, and a conductive structure is provided in the back surface via hole 40, a first end of the conductive structure is in contact connection with the substrate 110, and a second end of the conductive structure is electrically connected with the first electrode 10 or in contact connection with the second electrode 20.

Specifically, the substrate 110 may be a semiconductor substrate. In some embodiments, the substrate 110 may include, for example, but not limited to, a group III element, a group IV element, a group V element, or a combination thereof (e.g., a III-V compound).

The first nitride semiconductor layer 120 is located at a side of the substrate 110, and the second nitride semiconductor layer 130 is located at a side of the first nitride semiconductor layer 120 remote from the substrate 110. The material of the first nitride semiconductor layer 120 may include, but is not limited to, nitrides or III-V compounds, such as GaN, alN, inN, in _x Al _y Ga _(1-x-y) N (wherein x+y is less than or equal to 1), al _y Ga _(1-y) N (where y.ltoreq.1). The material of the second nitride semiconductor layer 130 may include, but is not limited to, a group III-V nitride semiconductor material, such as GaN, alGaN, inN, alInN, inGaN, alInGaN, or a combination thereof. The band gap (i.e., the forbidden band width) of the material of the first nitride semiconductor layer 120 and the band gap of the material of the second nitride semiconductor layer 130 are selected to be different from each other such that electron affinities thereof are different from each other and a heterojunction is formed therebetween.

The band gap of the material of the first nitride semiconductor layer 120 is set to be smaller than that of the material of the second nitride semiconductor layer 130, for example, the first nitride semiconductor layer 120 may be selected to be a GaN layer having a band gap of about 3.4eV, and the second nitride semiconductor layer 130 may be selected to be an AlGaN layer having a band gap of about 4.0eV, whereby the first nitride semiconductor layer 120 and the second nitride semiconductor layer 130 may function as a channel layer and a barrier layer, respectively. A triangular well potential is generated at the junction interface between the channel layer and the barrier layer such that electrons accumulate in the triangular well, thereby creating a two-dimensional electron gas (2 DEG) region adjacent to the heterojunction. Accordingly, the nitride-based semiconductor device can include at least one GaN-based high-resistance mobility transistor (HEMT). It should be noted that the formation of the 2DEG region is positively correlated to the degree of polarization effect between the channel and the barrier layer.

The gate structure 30 is located at a side of the second nitride semiconductor layer 130 remote from the substrate 110. The gate structure 30 includes a gate electrode that may be disposed on/over/on the second nitride semiconductor layer 130. The material of the gate electrode may be a metal or metal compound including, but not limited to, tungsten (W), gold (Au), palladium (Pd), titanium (Ti), tantalum (Ta), cobalt (Co), nickel (Ni), platinum (Pt), molybdenum (Mo), titanium nitride (TiN), tantalum nitride (TaN), other metal compounds, nitrides, oxides, silicides, doped semiconductors, metal alloys, or combinations thereof. In some embodiments, the gate electrode may be in contact with the second nitride semiconductor layer 130. In some embodiments, the gate structure 30 further includes a gate insulating layer disposed between the gate electrode and the second nitride semiconductor layer 130. In other embodiments, the gate structure 30 further includes a third nitride semiconductor layer disposed between the gate electrode and the second nitride semiconductor layer 130. The material of the third nitride semiconductor layer may include, but is not limited to, p-doped group III-V nitride semiconductor materials such as p-type GaN, p-type AlGaN, p-type InN, p-type AlInN, p-type InGaN, p-type AlInGaN, or combinations thereof. The p-doped material can Be obtained by using p-type impurities such as Be, zn, cd and Mg.

The first electrode 10 is located at a side of the second nitride semiconductor layer 130 remote from the substrate 110, and is in contact with the second nitride semiconductor layer 130. The gate structure 30 is disposed around the first electrode 10 forming a closed loop profile. The second electrode 20 is located at a side of the second nitride semiconductor layer 130 remote from the substrate 110 and contacts the second nitride semiconductor layer 130. The second electrode 20 is disposed around the gate electrode forming a closed loop profile. The first electrode 10 and the second electrode 20 are disposed on opposite sides of the gate structure 30. That is, the gate structure 30 and the second electrode 20 are sequentially disposed around the first electrode 10 in a direction away from the first electrode 10. By arranging the gate structure 30 and the second electrode 20 in a ring-shaped structure, the size of the electrode structure can be adjusted, and the generation of exposed end surfaces outside the active region can be avoided; because the structure is additionally and negatively affected when the exposed end face is processed, the weakening of the grid control capability caused by the processing of the exposed end face can be avoided, so that the possibility of electric leakage is reduced, and the reliability of the device is improved.

The first electrode 10 may be a source electrode S, and the second electrode 20 is a drain electrode D; alternatively, the first electrode 10 may be the drain electrode D, and the second electrode 20 may be the source electrode S. The function of the first electrode 10 and the second electrode 20 depends on the device design. In fig. 4 and 5, the first electrode 10 may be a source electrode S, and the second electrode 20 may be a drain electrode D. The first electrode 10 and the second electrode 20 may include, but are not limited to, metals, alloys, doped semiconductor materials (e.g., doped crystalline silicon), compounds such as silicides and nitrides, other conductor materials, or combinations thereof. The first electrode 10 and the second electrode 20 may be a single layer or a plurality of layers having the same or different compositions. In some embodiments, the first electrode 10 and the second electrode 20 form ohmic contacts with the second nitride semiconductor layer 130. Ohmic contact may be achieved by applying Ti, al, or other suitable materials to the first electrode 10 and the second electrode 20.

The back via hole 40 penetrates the first nitride semiconductor layer 120 and the second nitride semiconductor layer 130, and a conductive structure is disposed in the back via hole 40, a first end of which is electrically connected to the substrate 110, and a second end of which is electrically connected to the first electrode 10 or to the second electrode 20. Grounding of the first electrode 10 or the second electrode 20 is achieved through the back-side through-hole 40. Since the backside via 40 occurs at the front-end of the process, the overall film thickness is thinner, and no excessively thick photoresist and longer etching are required, thereby reducing the generation of polymers (polymers), further improving the reliability of the device, and reducing the cost of the device.

According to the nitride-based semiconductor device provided by the embodiment of the utility model, the grid structure and the second electrode are arranged into the annular structure, so that the size of the electrode structure can be adjusted, and the generation of a bare end surface falling outside the active region can be avoided; because the structure is additionally and negatively affected when the exposed end face is processed, the weakening of the grid control capability caused by the processing of the exposed end face can be avoided, so that the possibility of electric leakage is reduced, and the reliability of the device is improved. On the basis, the back through holes are arranged in the first nitride semiconductor layer and the second nitride semiconductor layer, so that the grounding of the first electrode or the second electrode is realized, and the back through holes are formed in the front section of the manufacturing process, so that the whole film layer is thinner in thickness, excessively thick photoresist and longer etching are not needed, the generation of polymers is reduced, and the reliability of the device is further improved.

On the basis of the above embodiments, in one embodiment of the present utility model, fig. 6 is a schematic structural view of another nitride-based semiconductor device provided in the embodiment of the present utility model, fig. 7 is a schematic sectional structural view of the structure shown in fig. 6 along a sectional line CC1, and referring to fig. 6 and 7, the number of the first electrodes 10 is plural, and the plural first electrodes 10 are disposed on a surface of the second nitride semiconductor layer 130 on a side away from the substrate 110 at intervals; the number of gate structures 30 is plural, and the number of gate structures 30 is the same as the number of first electrodes 10; each first electrode 10 is surrounded by a ring-shaped gate structure 30; the number of the second electrodes 20 is plural, and the number of the second electrodes 20 is the same as the number of the gate structures 30; each gate structure 30 is surrounded by a ring-shaped second electrode 20; wherein the second electrodes 20 located between two adjacent gate structures 30 are shared, and a plurality of the second electrodes 20 are interwoven into a mesh structure; the first electrode 10 is a source electrode S, and the second electrode 20 is a drain electrode D.

On the basis of the above embodiments, in one embodiment of the present utility model, fig. 8 is a schematic structural view of another nitride-based semiconductor device provided in the embodiment of the present utility model, fig. 9 is a schematic sectional structural view of the structure shown in fig. 8 along a sectional line DD1, and referring to fig. 8 and 9, the number of the first electrodes 10 is plural, and the plural first electrodes 10 are disposed on a surface of the second nitride semiconductor layer 130 on a side away from the substrate 110 at intervals; the number of gate structures 30 is plural, and the number of gate structures 30 is the same as the number of first electrodes 10; each first electrode 10 is surrounded by a ring-shaped gate structure 30; the number of the second electrodes 20 is plural, and the number of the second electrodes 20 is the same as the number of the gate structures 30; each gate structure 30 is surrounded by a ring-shaped second electrode 20; wherein the second electrodes 20 located between two adjacent gate structures 30 are shared, and a plurality of the second electrodes 20 are interwoven into a mesh structure; the first electrode 10 is a drain electrode D, and the second electrode 20 is a source electrode S.

Specifically, the number of the first electrodes 10, the gate structures 30, and the second electrodes 20 is plural, and the number of the first electrodes 10, the number of the gate structures 30, and the number of the second electrodes 20 are equal. Each first electrode 10 is surrounded by an annular gate structure 30, and each gate structure 30 is surrounded by an annular second electrode 20. Each of the first electrode 10 and its surrounding ring-shaped gate structure 30 and the second electrode 20 are used to form the source, drain, gate of a GaN-based high-resistivity mobility transistor (HEMT). That is, the nitride-based semiconductor device may include a plurality of GaN-based high-resistance mobility transistors (HEMTs). The second electrodes 20 between two adjacent gate structures 30 are shared, and the plurality of second electrodes 20 are interwoven into a mesh structure, so that the occupied area of the second electrodes 20 can be reduced. Therefore, the nitride-based semiconductor device is realized while the reliability thereof is also satisfied.

Optionally, the shape of the orthographic projection of the first electrode 10 on the substrate 110 includes a circle, an ellipse, or a polygon; the shape of the orthographic projection of the gate structure 30 on the substrate 110 includes an annular, elliptical annular, or polygonal annular shape; the shape of the orthographic projection of the second electrode 20 on the substrate 110 includes a circular ring shape, an elliptical ring shape, or a polygonal ring shape. The distances between the gate structure 30 and the first electrode 10 around which it is disposed may be equal at different positions; and the distances between the second electrode 20 and the gate structure 30 around which it is disposed are all equal at different positions; with this configuration, the distance deviation between the electrodes can be eliminated, so that the carrier flow can flow more uniformly outward or inward.

Based on the above embodiments, in one embodiment of the present utility model, please continue to refer to fig. 6-9, the distance between the gate structure 30 and the drain electrode D is greater than the distance between the gate structure 30 and the source electrode S.

Specifically, when the first electrode 10 is the source electrode S and the second electrode 20 is the drain electrode D, the distance between the gate structure 30 and the second electrode 20 is greater than the distance between the gate structure 30 and the first electrode 10. When the first electrode 10 is the drain electrode D and the second electrode 20 is the source electrode S, the distance between the gate structure 30 and the first electrode 10 is greater than the distance between the gate structure 30 and the second electrode 20.

Based on the above embodiments, in one embodiment of the present utility model, please continue to refer to fig. 6-9, in which the second end of the conductive structure located in the backside via 40 is in contact with the source electrode S; the front projection of the backside via 40 onto the substrate 110 at least partially overlaps the front projection of the source onto the substrate 110.

Specifically, the rear via 40 is located below the source electrode S, and the front projection of the rear via 40 on the substrate 110 at least partially overlaps with the front projection of the source on the substrate 110, so that the second end of the conductive structure located in the rear via 40 is electrically connected to, or directly contacted with, the source electrode S, thereby realizing grounding of the source electrode S. Because the backside via 40 occurs at the front-end of the process, the overall film thickness is thinner, eliminating the need for too thick photoresist and longer etching, thereby reducing polymer production and improving device reliability.

Referring to fig. 6 and 7, when the first electrode 10 is the source electrode S and the second electrode 20 is the drain electrode D, the backside via 40 is located under the first electrode 10. The shape of the orthographic projection of the backside via 40 on the substrate 110 may be circular, elliptical, or polygonal.

Referring to fig. 8 and 9, when the first electrode 10 is the drain electrode D and the second electrode 20 is the source electrode S, the rear through hole 40 is located under the second electrode 20. The shape of the orthographic projection of the backside via 40 on the substrate 110 includes an annular shape, an elliptical shape, or a polygonal shape. That is, the rear through-hole 40 may form an annular, elliptical or polygonal annular groove. The second electrode 20 located between the adjacent two gate structures 30 is shared, and thus, the backside via 40 located between the adjacent two gate structures 30 is shared.

On the basis of the above embodiments, in one embodiment of the present utility model, referring to fig. 7 and 9, the nitride-based semiconductor device further includes: a passivation layer 210, the passivation layer 210 being located at a side of the second nitride semiconductor layer 130 remote from the substrate 110 and covering the gate structure 30, the first electrode 10, and the second electrode 20; the field plate 50 is located in the passivation layer 210 and disposed around the gate structure 30.

Wherein the field plate 50 is stepped; the field plate 50 includes a first field plate layer a located above the gate structure 30, a second field plate layer b located between the drain electrode D and the gate structure 30, and an intermediate connection portion c connecting the first field plate layer a and the second field plate layer b.

Specifically, the material of the passivation layer 210 includes, but is not limited to, a dielectric material. For example, the material of the passivation layer 210 may include silicon nitride, such as silicon nitride (SiN) _x ) Silicon nitride (Si) ₃ N ₄ ) Silicon oxynitride (SiON), silicon boron nitride (SiBN), silicon boron nitride (SiCBN), or combinations thereof. The field plate 50 is disposed in the passivation layer 210, and the field plate 50 may include a first field plate layer a over the gate structure 30, a second field plate layer b between the drain electrode D and the gate structure 30, and an intermediate connection portion c connecting the first field plate layer a and the second field plate layer b. The intermediate connection c connects the first field plate layer a and the second field plate layer b, the intermediate connection c extending transversely between the first field plate layer a and the second field plate layer b. The first field plate layer a of the field plate 50 is located directly above the gate structure 30, and the first field plate layer a of the field plate 50 is electrically insulated from the gate structure 30 by the passivation layer 210. The second field plate layer b of the field plate 50 is located between the drain electrode D and the gate structure 30, and the second field plate layer b of the field plate 50 is electrically insulated from the gate structure 30, the drain electrode D, and the second nitride semiconductor layer 130 by the passivation layer 210.

The height relationship among the first field plate layer a, the intermediate connection portion c and the second field plate layer b of the field plate 50 is that the first field plate layer a is located at a position higher than the intermediate connection portion c, and the intermediate connection portion c is located at a position higher than the first field plate layer a, so that the field plate 50 is stepped. The material of the field plate 50 includes a conductive material such as titanium (Ti), tantalum (Ta), titanium nitride (TiN), tantalum nitride (TaN), or a combination thereof. In some embodiments, other conductive materials may also be used, such as aluminum, copper doped silicon (Cu doped Si), and alloys including these materials. The field plate 50 is used to change the electric field distribution of the drain region and affect the breakdown voltage of the semiconductor device. The field plate 50 suppresses electric field distribution in the target area and reduces its peak value.

On the basis of the above embodiments, in one embodiment of the present utility model, the nitride-based semiconductor device further includes: a first electrode pad electrically connected to the first electrode with a first front-side via hole passing through the at least one dielectric layer; a second electrode pad electrically connected to the second electrode with a second front via through the at least one dielectric layer; a gate pad electrically connected to the gate structure 30 with a gate via through the at least one dielectric layer. The first electrode pad, the second electrode pad and the gate pad are used for respectively realizing the electric connection of the first electrode, the second electrode and the gate structure with external electric signal terminals.

Note that the above is only a preferred embodiment of the present utility model and the technical principle applied. It will be understood by those skilled in the art that the present utility model is not limited to the particular embodiments described herein, but is capable of various obvious changes, rearrangements and substitutions as will now become apparent to those skilled in the art without departing from the scope of the utility model. Therefore, while the utility model has been described in connection with the above embodiments, the utility model is not limited to the embodiments, but may be embodied in many other equivalent forms without departing from the spirit or scope of the utility model, which is set forth in the following claims.

Claims (10)

1. A nitride-based semiconductor device, characterized by comprising:

a substrate;

a first nitride semiconductor layer located at one side of the substrate;

a second nitride semiconductor layer located on a side of the first nitride semiconductor layer away from the substrate and having a band gap different from that of the first nitride semiconductor layer; a heterojunction having a two-dimensional electron gas between the first nitride semiconductor layer and the second nitride semiconductor layer;

a first electrode located at a side of the second nitride semiconductor layer away from the substrate;

a gate structure located at a side of the second nitride semiconductor layer away from the substrate and surrounding the first electrode;

a second electrode located at a side of the second nitride semiconductor layer away from the substrate and surrounding the gate structure; the second electrode is arranged on one side of the grid structure far away from the first electrode;

and the back through hole penetrates through the first nitride semiconductor layer and the second nitride semiconductor layer, a conductive structure is arranged in the back through hole, a first end of the conductive structure is in contact connection with the substrate, and a second end of the conductive structure is in contact connection with the first electrode or the second electrode.

2. A nitride-based semiconductor device according to claim 1, wherein,

the number of the first electrodes is a plurality, and the first electrodes are arranged on the surface of the second nitride semiconductor layer, which is far away from the substrate, at intervals;

the number of the gate structures is a plurality, and the number of the gate structures is the same as the number of the first electrodes; each grid structure is correspondingly arranged around one first electrode;

the number of the second electrodes is a plurality, and the number of the second electrodes is the same as the number of the gate structures; each second electrode is correspondingly arranged around one grid structure;

and the second electrodes are positioned between two adjacent grid structures and are shared, and a plurality of second electrodes are interwoven into a net structure.

3. A nitride-based semiconductor device according to claim 1, wherein,

the shape of the orthographic projection of the first electrode on the substrate comprises a circle, an ellipse or a polygon;

the shape of the orthographic projection of the grid structure on the substrate comprises a circular ring shape, an elliptical ring shape or a polygonal ring shape;

the shape of the orthographic projection of the second electrode on the substrate comprises a circular ring shape, an elliptical ring shape or a polygonal ring shape.

4. A nitride-based semiconductor device according to any one of claims 1 to 3, wherein the first electrode is a source electrode and the second electrode is a drain electrode; alternatively, the first electrode is a drain electrode, and the second electrode is a source electrode.

5. The nitride-based semiconductor device of claim 4, wherein a distance between the gate structure and the drain electrode is greater than a distance between the gate structure and the source electrode.

6. The nitride-based semiconductor device according to claim 5, further comprising:

a passivation layer located on a side of the second nitride semiconductor layer away from the substrate and covering the gate structure, the first electrode, and the second electrode;

a field plate located in the passivation layer and disposed around the gate structure;

wherein the field plate is in a ladder shape; the field plate comprises a first field plate layer positioned above the grid structure, a second field plate layer positioned between the drain electrode and the grid structure, and an intermediate connecting part for connecting the first field plate layer and the second field plate layer.

7. The nitride-based semiconductor device of claim 5, wherein a second end of the conductive structure in the backside via is in contact with the source electrode; the orthographic projection of the back via on the substrate at least partially overlaps the orthographic projection of the source on the substrate.

8. The nitride-based semiconductor device according to claim 7, wherein when the first electrode is a drain electrode and the second electrode is a source electrode, a shape of an orthographic projection of the backside via hole on the substrate includes a circular ring shape, an elliptical ring shape, or a polygonal ring shape.

9. The nitride-based semiconductor device according to claim 1, further comprising:

a first electrode pad electrically connected to the first electrode with a first front-side via through at least one dielectric layer;

a second electrode pad electrically connected to the second electrode with a second front-side via through at least one dielectric layer;

and a gate pad electrically connected to the gate structure with a gate via through the at least one dielectric layer.

10. The nitride-based semiconductor device according to claim 1, wherein the gate structure includes a third nitride semiconductor layer and a gate electrode; the third nitride semiconductor layer is located between the gate electrode and the second nitride semiconductor layer;

alternatively, the gate structure includes a gate insulating layer and a gate electrode; the gate insulating layer is located between the gate electrode and the second nitride semiconductor layer.