CN220693133U - High-efficiency low-phase noise phase-locked loop circuit - Google Patents
High-efficiency low-phase noise phase-locked loop circuit Download PDFInfo
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- CN220693133U CN220693133U CN202322388185.5U CN202322388185U CN220693133U CN 220693133 U CN220693133 U CN 220693133U CN 202322388185 U CN202322388185 U CN 202322388185U CN 220693133 U CN220693133 U CN 220693133U
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Abstract
The utility model relates to a high-efficiency low-phase noise phase-locked loop circuit, which comprises a power supply unit, wherein the power supply unit supplies power to the phase-locked loop circuit and a monitoring unit, and the output end of the monitoring unit is connected with the input end of the phase-locked loop circuit; the power supply unit comprises a DC-DC switching power supply, a first power supply filtering unit, a high power supply rejection ratio low dropout linear voltage regulator and a second power supply filtering unit; the output end of the DC-DC switching power supply is connected with the input end of the first power supply filtering unit; the output end of the first power supply filtering unit is connected with the input end of the high power supply rejection ratio low dropout linear voltage regulator; the input end of the second power supply filtering unit is connected with the output end of the high power supply rejection ratio low dropout linear voltage regulator; and the output end of the second power supply filtering unit is connected with the phase-locked loop circuit and the power supply input end of the monitoring unit. The utility model can realize miniaturization, low cost and low phase noise.
Description
Technical Field
The utility model relates to a high-efficiency low-phase noise phase-locked loop circuit, belonging to the fields of microwave communication, signal sources, test systems and interference systems; the method is mainly used for local oscillation signal generation of equipment such as a radio frequency transceiver system, a phased array and the like.
Background
In a system or module containing a phase-locked loop, the existing phase-locked loop circuit cannot be fully compatible due to the limitation of power efficiency, low phase noise, low cost, miniaturization and module embedding.
Disclosure of Invention
The utility model solves the technical problems that: in a system or module including a phase locked loop, a high power efficiency, low phase noise, low cost, miniaturized high efficiency low phase noise phase locked loop circuit is provided.
The technical scheme adopted by the utility model is as follows:
the high-efficiency low-phase noise phase-locked loop circuit comprises a power supply unit, wherein the power supply unit supplies power to the phase-locked loop circuit and a monitoring unit, and the output end of the monitoring unit is connected with the input end of the phase-locked loop circuit;
the power supply unit comprises a DC-DC switching power supply, a first power supply filtering unit, a high power supply rejection ratio low dropout linear voltage regulator and a second power supply filtering unit;
the output end of the DC-DC switching power supply is connected with the input end of the first power supply filtering unit; the output end of the first power supply filtering unit is connected with the input end of the high power supply rejection ratio low dropout linear voltage regulator; the input end of the second power supply filtering unit is connected with the output end of the high power supply rejection ratio low dropout linear voltage regulator; and the output end of the second power supply filtering unit is connected with the phase-locked loop circuit and the power supply input end of the monitoring unit.
Preferably, the phase-locked loop circuit includes a reference signal, a phase detector, a loop filter, and a VCO;
the reference signal output end is connected with a corresponding input end of the phase discriminator, the phase discriminator output end is connected with the input end of the loop filter, and the loop filter output end is connected with the input end of the VCO.
Preferably, the output end of the VCO is connected to the input end of the amplifier, the output end of the amplifier is connected to the output port of the phase-locked loop circuit module to output the target frequency signal, the output end of the VCO is connected to the input end of the phase discriminator, and the output end of the monitoring unit is connected to the input end of the phase-locked loop circuit.
Preferably, the monitoring unit includes: the system comprises a communication interface, a singlechip circuit and a clock chip; the output end of the clock chip is connected with the corresponding input end of the singlechip circuit, the output end of the singlechip circuit is connected with the corresponding input end of the phase discriminator, and the I/O end of the interface circuit is connected with the corresponding I/O end of the singlechip circuit, so that the instruction issuing of the singlechip circuit and the receipt of the singlechip feedback instruction are realized; the power supply port of the monitoring unit supplies power to the monitoring unit, and the upper control interface is connected with the corresponding I/O end of the interface circuit of the monitoring unit, so that the monitoring unit is detected and controlled.
The utility model has the beneficial effects that:
in the system or module containing the phase-locked loop, the DC-DC switching power supply with high use efficiency converts high voltage (such as +24V, +28V, +48V and the like) into voltage (such as +5V, +3.3V, +1.8V and the like) which can be used by the phase-locked loop, but the DC-DC switching power supply can introduce power supply ripple, so that the PLL (phase noise) at the near end is deteriorated, and the voltage output by the DC-DC switching power supply can be furthest reduced or even eliminated through the LDO voltage stabilizer with high power supply rejection ratio. Therefore, the power supply efficiency is improved, the phase noise of the PLL output signal is optimized, the scheme is low in cost, the circuit size is small, and miniaturization and module embedding can be realized.
Drawings
Fig. 1 is a schematic structural view of the present utility model.
Detailed Description
In order to further describe the technical means and effects adopted by the present utility model for achieving the intended purpose, the following detailed description will refer to the specific implementation, structure, characteristics and effects according to the present utility model with reference to the accompanying drawings and preferred embodiments.
As shown in fig. 1, a high-efficiency low-phase noise phase-locked loop circuit is composed of a DC-DC switching power supply, a first power supply filtering unit, a high power supply rejection ratio low dropout linear voltage regulator, a second power supply filtering unit, a monitoring unit, a reference signal, a phase discriminator, a loop filter and a VCO.
The corresponding output end of the DC-DC switching power supply is connected with the input end of the first power supply filtering unit; the output end of the first power supply filtering unit is connected with the input end of the high power supply rejection ratio low dropout linear voltage regulator; the input end of the second power supply filtering unit is connected with the output end of the high power supply rejection ratio low dropout linear voltage regulator; the output end of the second power supply filtering unit is connected with the power supply input ends of the phase-locked loop unit and the monitoring unit.
The reference signal output end is connected with a corresponding input end of the phase discriminator, the phase discriminator output end is connected with the input end of the loop filter, and the loop filter output end is connected with the input end of the VCO; the output end of the VCO is connected with the input end of the amplifier, the output end of the amplifier is connected with the output port of the module to output a target frequency signal, the corresponding output end of the VCO is connected with the corresponding input end of the phase discriminator, and the output end of the monitoring unit is connected with the corresponding input end of the phase-locked loop circuit. The working process comprises the following steps: the power supply is provided by the system, and the DC-DC switching power supply of the circuit converts higher voltage into voltage used by the PLL and simultaneously supplies power to the phase discriminator, the VCO and the monitoring unit. The reference signal is a reference radio frequency signal of the phase detector and a radio frequency signal returned by the VCO are compared to generate an error voltage, and the error voltage is integrated by the loop filter to form a stable direct current voltage which is supplied to a voltage-controlled end of the VCO. When the voltage control terminal voltage of the VCO is different, the VCO outputs signals with different frequencies, and the signals output by the VCO are amplified by the amplifier to reach the required power level and then output.
The monitoring unit receives the instruction of the system, controls the singlechip circuit through the interface circuit, wherein the clock chip provides time sequence for the singlechip circuit, and the singlechip circuit receives the instruction and processes the corresponding data to be sent to the phase discriminator, and realizes the switching adjustment of frequency by adjusting the parameters in the phase discriminator.
In this embodiment, a DC-DC switching power supply is used to convert a higher voltage in the device into a voltage value (u+0.3) V required by the phase-locked loop, and the voltage value is supplied to the input terminal of the high-power supply rejection ratio low-dropout linear voltage regulator, which outputs the voltage U required by the phase-locked loop circuit. The efficiency of the DC-DC switching power supply is generally over 90 percent, and the power supply efficiency is extremely high; the high power supply rejection is extremely high compared with the efficiency that the input and output voltage of the linear voltage stabilizer is 0.3V tight. The high power supply rejection ratio is about 70dB, and ripple noise introduced by the DC-DC switching power supply can be effectively suppressed and eliminated. So that the phase noise at the near end (1 kHz, 10 kHz) of the phase locked loop is greatly optimized. Because the traditional circuit for filtering ripple waves is mostly a capacitor with a large capacitance value and an inductor with a high inductance value, the size of the devices is large, and the filtering effect is poor. The circuit can realize a miniaturized, low-cost, low-phase noise phase-locked loop design.
The utility model can be applied to the design of local oscillation signal modules with high power efficiency, low phase noise, low cost and miniaturization of equipment such as a radio frequency transceiver system, a phased array and the like.
The present utility model is not limited to the above embodiments, but is capable of modification and variation in detail, and other modifications and variations can be made by those skilled in the art without departing from the scope of the present utility model.
Claims (4)
1. The high-efficiency low-phase noise phase-locked loop circuit is characterized by comprising a power supply unit, wherein the power supply unit supplies power to the phase-locked loop circuit and a monitoring unit, and the output end of the monitoring unit is connected with the input end of the phase-locked loop circuit;
the power supply unit comprises a DC-DC switching power supply, a first power supply filtering unit, a high power supply rejection ratio low dropout linear voltage regulator and a second power supply filtering unit;
the output end of the DC-DC switching power supply is connected with the input end of the first power supply filtering unit; the output end of the first power supply filtering unit is connected with the input end of the high power supply rejection ratio low dropout linear voltage regulator; the input end of the second power supply filtering unit is connected with the output end of the high power supply rejection ratio low dropout linear voltage regulator; and the output end of the second power supply filtering unit is connected with the phase-locked loop circuit and the power supply input end of the monitoring unit.
2. The high efficiency low phase noise phase locked loop circuit of claim 1 wherein said phase locked loop circuit comprises a reference signal, a phase detector, a loop filter, and a VCO;
the reference signal output end is connected with a corresponding input end of the phase discriminator, the phase discriminator output end is connected with the input end of the loop filter, and the loop filter output end is connected with the input end of the VCO.
3. The high efficiency low phase noise phase locked loop circuit of claim 2 wherein the output of the VCO is connected to the input of an amplifier, the output of the amplifier is connected to the output of the phase locked loop circuit module, the output of the VCO is connected to the input of the phase detector, and the output of the monitor unit is connected to the input of the phase locked loop circuit.
4. A high efficiency low phase noise phase locked loop circuit as claimed in claim 3 wherein said monitoring unit comprises: the system comprises a communication interface, a singlechip circuit and a clock chip; the output end of the clock chip is connected with the corresponding input end of the singlechip circuit, the output end of the singlechip circuit is connected with the corresponding input end of the phase discriminator, the I/O end of the interface circuit is connected with the corresponding I/O end of the singlechip circuit, the power supply port of the monitoring unit supplies power for the monitoring unit, and the upper control interface is connected with the corresponding I/O end of the interface circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202322388185.5U CN220693133U (en) | 2023-09-04 | 2023-09-04 | High-efficiency low-phase noise phase-locked loop circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202322388185.5U CN220693133U (en) | 2023-09-04 | 2023-09-04 | High-efficiency low-phase noise phase-locked loop circuit |
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| Publication Number | Publication Date |
|---|---|
| CN220693133U true CN220693133U (en) | 2024-03-29 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202322388185.5U Active CN220693133U (en) | 2023-09-04 | 2023-09-04 | High-efficiency low-phase noise phase-locked loop circuit |
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| Country | Link |
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| CN (1) | CN220693133U (en) |
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2023
- 2023-09-04 CN CN202322388185.5U patent/CN220693133U/en active Active
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