CN220652007U - Multi-chip vertically stacked small-sized wafer level package structure - Google Patents
Multi-chip vertically stacked small-sized wafer level package structure Download PDFInfo
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- CN220652007U CN220652007U CN202321874741.3U CN202321874741U CN220652007U CN 220652007 U CN220652007 U CN 220652007U CN 202321874741 U CN202321874741 U CN 202321874741U CN 220652007 U CN220652007 U CN 220652007U
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- 239000002184 metal Substances 0.000 claims abstract description 54
- 239000005022 packaging material Substances 0.000 claims abstract description 19
- 239000000463 material Substances 0.000 claims abstract description 16
- 238000000034 method Methods 0.000 claims abstract description 16
- 235000012431 wafers Nutrition 0.000 claims description 116
- 229910000679 solder Inorganic materials 0.000 claims description 8
- 238000004806 packaging method and process Methods 0.000 abstract description 21
- 238000010586 diagram Methods 0.000 description 6
- 238000000465 moulding Methods 0.000 description 4
- 230000008521 reorganization Effects 0.000 description 4
- 239000000758 substrate Substances 0.000 description 3
- 229940125898 compound 5 Drugs 0.000 description 2
- 150000001875 compounds Chemical class 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 238000012536 packaging technology Methods 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 238000004026 adhesive bonding Methods 0.000 description 1
- 238000002507 cathodic stripping potentiometry Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000000227 grinding Methods 0.000 description 1
- 238000001746 injection moulding Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 239000012778 molding material Substances 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
- 238000007789 sealing Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
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Abstract
A multi-chip vertically stacked small-size wafer level package structure comprises a plastic package material, a large chip and a small chip, wherein the small chip is arranged below the large chip and within the projection range of the large chip; the front surface of the large wafer is downward, a plurality of metal high bumps are distributed on the front surface of the large wafer, and the metal high bumps are arranged on the periphery of the position where the small wafer is located. The front surface of the small wafer is downward, and a plurality of metal short bumps are distributed on the front surface of the small wafer; the back of the small wafer is connected with the front of the large wafer; the large wafer, the small wafer, the metal high bump and the metal low bump are all wrapped by plastic packaging material, and the bottom ends of the metal high bump and the metal low bump are exposed on the bottom surface of the plastic packaging material; the bottom ends of the metal high bumps and the bottom ends of the metal low bumps are connected with corresponding wiring terminals on the top surface of the rewiring layer; the bottom surface of the rewiring layer is provided with a UBM bonding pad; the top surface of the rewiring layer is clung to the bottom surface of the plastic packaging material. The packaging structure can be smaller in size and convenient to process.
Description
Technical Field
The utility model belongs to the technical field of chip packaging, and particularly relates to a small-size wafer-level packaging structure with vertically stacked multiple chips.
Background
In recent years, packaging technology has gradually progressed toward high integration, small volume, low power consumption, and excellent performance. The initial advent of chip scale packaging CSPs was to address the needs for consumer electronics to be light, thin, short, and small.
Conventional wafer level packaging WLP mostly adopts Fan-in (Fan-in) type, and is applied to ICs with a smaller number of pins (pins), as shown in fig. 1. The Fan-In (Fan-In) packaging structure is that the whole wafer chip is firstly subjected to packaging test, and then is cut into single chips, and the packaging size is identical to the chip size.
Along with the increase of the number of signal output pins of the chip, the requirements on the space between solder balls (Ball Pitch) are more and more strict, and the adjustment requirements of the PCB structure on the size after the IC package and the position of the signal output pins are changed, so that the Fan-out FOWLP package type is derived. Fan-Out package is based on a reorganization technology, after the chips are cut, the chips are reloaded to a reorganization carrier plate to form a reorganization wafer, package test is carried Out according to steps similar to a Fan-in packaging technology, then the reorganization wafer is cut into single chips, the area outside the chips is a Fan-Out area, and solder balls are allowed to be placed outside the area of the chip 9, as shown in fig. 2 and 3, namely the FOWLP package.
In general, FOWLP packages are characterized by small size, no substrate, and plastic package, but FOWLP packages have several problems: 1) When the die is packaged, the die needs to be tiled, so that the die cannot be stacked, and the size of the die is increased; 2) The die is prone to offset during die loading, and if the die exceeds the specification, the RDL process is affected.
Reference is made to patent application publication 115763390a for a TSV-free, substrate-free multi-wafer stack wafer level package structure and method, which discloses a TSV-free, substrate-free multi-wafer stack wafer level package structure comprising a molding compound, a die and a rewiring layer; the wafers are divided into large wafers and small wafers; the bonding pads on the front surface of the large wafer are provided with a plurality of high protruding points, and the tops of the high protruding points are connected with corresponding metal contacts on the top surface of the rewiring layer; a gap is formed between the front surface of the large wafer and the rewiring layer, and the small wafer is arranged in the gap; the front surface of the large wafer is opposite to the front surface of the small wafer, and the front surface of the small wafer is connected with a corresponding bonding pad on the front surface of the large wafer; the plastic packaging material seals the small chip; the top ends of the high bumps of the large wafer are exposed out of the plastic packaging material; the rewiring layer is distributed on the top surface of the plastic packaging material. Although the scheme can realize flip-chip interconnection of a plurality of wafers without Through Silicon Vias (TSVs), the cost and the process complexity are greatly reduced, the packaging structure has the following defects: during processing, the front surface of the small chip is connected with the corresponding bonding pad of the front surface of the large chip, and the flip-chip connection of the small chip under the structure needs to perform extra rewiring on the surface of the large chip to interconnect two chip circuits, and the SMT process is relatively complex.
Disclosure of Invention
In order to solve the problems in the prior art, the utility model provides a small-size wafer-level packaging structure with vertically stacked multiple wafers, which comprises a plastic package material, a large wafer and a small wafer, wherein the small wafer is arranged below the large wafer and in the projection range of the large wafer; the front surface of the large wafer is downward, a plurality of metal high bump bumps are distributed on the front surface of the large wafer, and the metal high bump bumps are arranged on the periphery of the position of the small wafer, and the method is characterized in that the front surface of the small wafer is downward, and a plurality of metal low bump bumps are distributed on the front surface of the small wafer; the back of the small wafer is connected with the front of the large wafer;
the large wafer, the small wafer, the metal high bump and the metal low bump are all wrapped by plastic packaging material, and the bottom ends of the metal high bump and the metal low bump are exposed on the bottom surface of the plastic packaging material;
the bottom ends of the metal high bumps and the bottom ends of the metal low bumps are connected with corresponding wiring terminals on the top surface of the rewiring layer; the bottom surface of the rewiring layer is provided with a UBM bonding pad;
the top surface of the rewiring layer is clung to the bottom surface of the plastic packaging material.
By adopting the packaging structure, the front surface of the small chip and the front surface of the large chip are connected to the RDL through the bump, so that rewiring is not needed to be conducted on the front surface of the large chip for transferring the circuit of the small chip. Meanwhile, the back of the small wafer is connected with the large wafer in a plurality of structural forms, such as DAF, direct gluing and the like, so that the process difficulty of connection between the large and small wafers is reduced.
In the structure, the front-side bump directions of the large and small wafers are consistent, the processing is convenient, the large and small wafers and the bump bumps thereof can be packaged by plastic packaging materials, the plastic packaging materials after polishing and curing are polished, the bump bumps of the large and small wafers are exposed on the surface of the plastic packaging materials, and finally the redistribution layer RDL is processed.
Preferably, a wafer bonding film DAF is arranged between the back surface of the small wafer and the front surface of the large wafer, and the small wafer and the large wafer are bonded through the wafer bonding film DAF. The structure is particularly convenient for production, and the DAF can be attached to the back of the wafer when the small chips are in the wafer stage, and then the wafer is cut to obtain individual small chips. The DAF is very stable (not flowing), so that the DAF is particularly suitable for grabbing by a manipulator in the chip packaging production process.
Further, the terminals of the top layer of the redistribution layer are metal microbumps u-bump. The structure is suitable for the process that RDL is prefabricated and then is adhered to the bottom surface of plastic package material, and the bump on the front surface of the large and small wafers is respectively connected and conducted with the metal micro bump u-bump of the corresponding RDL.
In addition to the prefabricated RDL of the structure, the RDL can also be directly manufactured (grown) on the bump of the large and small wafers exposed from the bottom surface of the molding compound.
Further, the UBM pads at the bottom layer of the redistribution layer are connected with solder balls.
Further, there are 1 or more small wafers; the small wafers are tiled below the large wafer in parallel and connected with the front surface of the large wafer.
The package structure can form a fan-in package structure or a fan-out package structure.
a. The projection of the large wafer on the rewiring layer is overlapped with the rewiring layer, so that the side face of the plastic package material is flush with the side face of the rewiring layer and the side face of the large wafer to form a fan-in type package structure;
b. the projection of the big wafer on the rewiring layer is within the range of the rewiring layer, then the side face of the plastic package material is flush with the side face of the rewiring layer, the big wafer is wrapped in the plastic package material (the side face of the big wafer is in the plastic package material, and the top face of the big wafer can be exposed out of the top face of the plastic package material.
Further, the height range of the metal high bump between the large wafer and the rewiring layer is 120-200 um; the height of the metal short bump between the die and the redistribution layer ranges from 50 to 90um. Within this range, the method can be applied to existing processing techniques/equipment, and the thickness of the package structure can be reduced as much as possible.
The packaging structure is adopted:
1) RDL is used for replacing the packaging substrate, and the material preparation and the exchange period of the substrate are not considered, so that the packaging cost can be saved by about 30%, and the packaging thickness is thinner.
2) The multi-chip die interconnection can be realized without using TSVs, and the process difficulty and the cost are reduced.
3) The different die are interconnected in a vertical stack, where the only dimension affecting the IC size is the dimension of the largest die. Compared with the existing multi-die tiled FOWLP packaging structure, the structure can be smaller in size.
Drawings
FIG. 1 is a schematic diagram of a Fan-in WLCSP package structure in the prior art;
FIG. 2 is a schematic diagram of a FOWLP package structure according to the prior art;
FIG. 3 is a schematic diagram of another foWLP package structure according to the prior art;
FIG. 4 is a schematic illustration of a fan-in stack package according to an embodiment of the present utility model;
FIG. 5 is a schematic diagram of a fan-out stack package according to an embodiment of the present utility model;
FIG. 6 is a schematic diagram of a three wafer fan-out stack package according to an embodiment of the present utility model;
in the figure: a large chip 1, a small chip 2, a metal high bump 3, a metal low bump 4, a molding compound 5, a rewiring layer 6, a chip bonding film 7, solder balls 8, a chip 9 and a metal bump 10.
Description of the embodiments
The present solution will be further described with reference to the following specific embodiments.
Referring to fig. 4 to 6, a multi-chip vertically stacked small-sized wafer level package structure includes a molding compound 5, a large die 1, and a small die 2, the small die 2 being below the large die 1 and within a projection range of the large die; the front surface of the large wafer is downward, a plurality of metal high bumps 3 are distributed on the front surface of the large wafer, and the metal high bumps are arranged on the periphery of the position of the small wafer. The front surface of the small wafer is downward, and a plurality of metal short bumps 4 are distributed on the front surface of the small wafer; the back of the small wafer is connected with the front of the large wafer; the large wafer, the small wafer, the metal high bump and the metal low bump are all wrapped by plastic packaging material, and the bottom ends of the metal high bump and the metal low bump are exposed on the bottom surface of the plastic packaging material; the bottom ends of each metal tall bump 3 and each metal short bump 4 are connected to corresponding terminals on the top surface of the rewiring layer 6; the bottom surface of the rewiring layer is provided with a UBM bonding pad; the top surface of the rewiring layer 6 is closely attached to the bottom surface of the plastic packaging material 5.
In this example:
a die bonding film 7 is provided between the back surface of the small die 2 and the front surface of the large die 1, and the small die and the large die are bonded by the die bonding film DAF. The UBM pads of the bottom layer of the rewiring layer 6 are connected with solder balls 8.
The number of small wafers is 1 (e.g., 1 in fig. 4 and 5) or more (e.g., 2 in fig. 6); the small wafers are tiled below the large wafer in parallel and connected with the front surface of the large wafer.
Referring to fig. 4, when the projection of the large wafer 1 on the re-wiring layer 6 is overlapped with the re-wiring layer, the side surface of the plastic package material is flush with the side surface of the re-wiring layer and the side surface of the large wafer, so as to form a fan-in package structure;
referring to fig. 5 and 6, the projection of the large wafer 1 on the re-wiring layer 6 is within the range of the re-wiring layer, so that the side surface of the plastic package material is flush with the side surface of the re-wiring layer, and the large wafer is wrapped in the plastic package material 5 to form a fan-out type package structure.
Under the existing process conditions, the height range of the metal high bump between the large wafer and the rewiring layer is 120-200 um; the height of the metal short bump between the die and the redistribution layer ranges from 50 to 90um. The terminals of the top layer of the rewiring layer may also be metal micro-bumps u-bumps.
1. Fan-in type multi die stacked wafer level package (see FIG. 4)
By the packaging structure, two or more wafers Die can be packaged in a vertically stacked mode, the overall size is kept consistent with the size of the largest wafer Die (namely, the large wafer 1 in the figure), and the minimum packaging size is realized.
According to the packaging structure, higher bump metal bumps (namely, metal high bumps) are grown on the periphery of the front surface of the large wafer 1, the middle area needs to be left enough for the small wafer 2 to be mounted, and shorter bum metal bumps (namely, metal low bumps) are also grown on the front surface of the small wafer 2, so that the stacking interconnection of two wafers Die can be realized through DAF. And filling the bump bumps covering the two Die with the injection molding material, and grinding the plastic packaging material until the bump bumps are exposed. And then carrying out RDL process on the exposed bump, and finally leading out a Solder ball Solder ball.
2. Fan-out type multi die stacked wafer level package (e.g. FIGS. 5 and 6)
If the number of I/O is increased, and the chip size (the projection area of the large wafer) cannot accommodate all the I/O pins, two or more Die may be packaged in a vertically stacked manner (as shown in fig. 5), and the contacts on the Die surface are extended beyond the projection area of the Die by the RDL layer, so that the flexibility of bump arrangement is increased, and the number of pins is increased, and the overall size is only slightly larger than the maximum Die size.
The package is basically consistent with the fan-in type multi-chip die stack package, and the scheme is very suitable for sealing one large-size chip and a plurality of small (size) chips, as shown in fig. 6, which is a schematic diagram of the 3-chip stack package.
In the processing process of the packaging structure, the problems that the surface of a large wafer needs to be subjected to extra rewiring in order to interconnect two chip circuits, the SMT process is more complex than the DAF connection and the like are avoided; meanwhile, the interface thickness BLT is uniform and controllable by using DAF (Die Attach Film) connection, and the mounting is smoother.
Claims (7)
1. A multi-chip vertically stacked small-size wafer level package structure comprises a plastic package material, a large chip and a small chip, wherein the small chip is arranged below the large chip and within the projection range of the large chip; the front surface of the large wafer is downward, a plurality of metal high bumps are distributed on the front surface of the large wafer, and the metal high bumps are arranged on the periphery of the position of the small wafer, and the method is characterized in that the front surface of the small wafer is downward, and a plurality of metal low bumps are distributed on the front surface of the small wafer; the back of the small wafer is connected with the front of the large wafer;
the large wafer, the small wafer, the metal high bump and the metal low bump are all wrapped by plastic packaging material, and the bottom ends of the metal high bump and the metal low bump are exposed on the bottom surface of the plastic packaging material;
the bottom ends of the metal high bumps and the bottom ends of the metal low bumps are connected with corresponding wiring terminals on the top surface of the rewiring layer; the bottom surface of the rewiring layer is provided with a UBM bonding pad;
the top surface of the rewiring layer is clung to the bottom surface of the plastic packaging material.
2. The multi-chip vertically stacked small scale wafer level package structure of claim 1 wherein die attach films are disposed between the back side of the small die and the front side of the large die, the small die and the large die being attached by the die attach films.
3. The multi-chip vertically stacked small scale wafer level package structure of claim 1, wherein UBM pads on the bottom layer of the redistribution layer are connected with solder balls.
4. The multi-chip vertically stacked small scale wafer level package structure of claim 1 wherein there are 1 or more small dies; the small wafers are tiled below the large wafer in parallel and connected with the front surface of the large wafer.
5. The small-sized wafer level package structure vertically stacked with multiple chips according to any one of claims 1 to 4, wherein the projection of the large chip on the rewiring layer is overlapped with the rewiring layer, and then the side surface of the plastic package material is flush with the side surface of the rewiring layer and the side surface of the large chip, so as to form a fan-in package structure;
and the projection of the large wafer on the rewiring layer is within the range of the rewiring layer, so that the side face of the plastic package material is flush with the side face of the rewiring layer, and the large wafer is wrapped in the plastic package material to form the fan-out type package structure.
6. The vertically stacked small-scale wafer level package structure of claim 5, wherein the height of the metal high bump between the large die and the redistribution layer is in the range of 120-200 um; the height of the metal short bump between the die and the redistribution layer ranges from 50 to 90um.
7. The multi-die vertically stacked small scale wafer level package structure of claim 5, wherein the terminals of the top layer of the redistribution layer are metal micro-bumps.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202321874741.3U CN220652007U (en) | 2023-07-17 | 2023-07-17 | Multi-chip vertically stacked small-sized wafer level package structure |
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| CN202321874741.3U CN220652007U (en) | 2023-07-17 | 2023-07-17 | Multi-chip vertically stacked small-sized wafer level package structure |
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| CN220652007U true CN220652007U (en) | 2024-03-22 |
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