CN220651712U

CN220651712U - PCIE extension line

Info

Publication number: CN220651712U
Application number: CN202322211042.7U
Authority: CN
Inventors: 于国庆; 李军; 胡光祥; 贾利宾; 刘天超; 谭双红
Original assignee: Shenzhen Suno Technology Co ltd
Current assignee: Shenzhen Suno Technology Co ltd
Priority date: 2023-08-16
Filing date: 2023-08-16
Publication date: 2024-03-22
Anticipated expiration: 2033-08-16

Abstract

The application provides a PCIE extension line, include: each transmission unit comprises a transmission line pair, a first shielding layer and an inner coating layer, wherein the first shielding layer is coated on the transmission line pair, and the inner coating layer is coated on the first shielding layer; and the second shielding layer is coated on the inner quilt layer. The PCIE extension line provided by the application is used for coating the first shielding layer outside the transmission line pair, so that each transmission unit is provided with an independent shielding cavity, mutual crosstalk between the transmission units is prevented, and the second shielding layer is coated outside the inner coating layer, so that interference of external signals to the transmission units is prevented.

Description

PCIE extension line

Technical Field

The application relates to the technical field of communication electric cables, in particular to a PCIE extension line.

Background

PCIE extension line is generally used in a server or a computer host, is used for connecting each internal template and transmitting signals, and the use occasion requires ultrathin wires and has strong electromagnetic interference resistance.

In the prior art, a PCIE extension line includes a plurality of transmission units and a shielding layer, where the shielding layer is wrapped outside the plurality of transmission units, however, crosstalk occurs between the plurality of transmission units in the shielding layer.

Disclosure of Invention

The application mainly provides a PCIE extension line, PCIE extension line includes: each transmission unit comprises a transmission line pair, a first shielding layer and an inner coating layer, wherein the first shielding layer is coated on the transmission line pair, and the inner coating layer is coated on the first shielding layer; and the second shielding layer is coated on the inner quilt layer.

In one embodiment, the second shielding layer is disposed outside the inner quilt layer.

In one embodiment, the second shielding layer includes a main body portion and two connection portions, the two connection portions are respectively connected to two sides of the main body portion, and the two connection portions are adhered.

In one embodiment, the second shielding layer includes a first sub-shielding layer and a second sub-shielding layer, where the first sub-shielding layer and the second sub-shielding layer are disposed opposite to each other.

In one embodiment, the first sub-shielding layer includes a first body portion and two first pairs of attachment portions, the two first pairs of attachment portions are respectively connected to two sides of the first body portion, the second sub-shielding layer includes a second body portion and two second pairs of attachment portions, the two second pairs of attachment portions are respectively connected to two sides of the second body portion, and the two first pairs of attachment portions and the two second pairs of attachment portions are respectively adhered.

In one embodiment, the PCIE extension line further includes an outer coating layer, where the outer coating layer is wrapped on the first sub-shielding layer and the second sub-shielding layer.

In one embodiment, the outer coating layer includes a first sub-outer coating layer and a second sub-outer coating layer, the first sub-outer coating layer is coated on the first sub-shielding layer, and the second sub-outer coating layer is coated on the second sub-shielding layer.

In one embodiment, the transmission unit further includes a ground line disposed between the transmission line pair and the first shielding layer, or between the first shielding layer and the inner cover layer.

In one embodiment, the transmission line pair includes two transmission lines, each of the transmission lines includes an inner conductor and an insulating layer, the insulating layer is coated on the inner conductor, and the first shielding layer is coated on the insulating layer.

In one embodiment, the insulating layer includes a first sub-insulating layer and a second sub-insulating layer, the first sub-insulating layer is coated on the inner conductor, the second sub-insulating layer is coated on the first sub-insulating layer, and the first shielding layer is coated on the second sub-insulating layer.

The beneficial effects of this application are: the PCIE extension line provided by the application is used for coating the first shielding layer outside the transmission line pair, so that each transmission unit is provided with an independent shielding cavity, mutual crosstalk between the transmission units is prevented, and the second shielding layer is coated outside the inner coating layer, so that interference of external signals to the transmission units is prevented.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are needed in the description of the embodiments will be briefly introduced below, it being obvious that the drawings in the following description are only some embodiments of the present application, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.

FIG. 1 is a schematic cross-sectional view of a PCIE extension in an embodiment of the present application;

fig. 2 is a schematic cross-sectional view of a PCIE extension line according to another embodiment of the present application;

fig. 3 is a schematic cross-sectional view of a PCIE extension line according to another embodiment of the present application;

fig. 4 is a schematic cross-sectional view of a transmission unit according to an embodiment of the present application.

Detailed Description

The present application is described in further detail below with reference to the drawings and the embodiments. It is specifically noted that the following embodiments are merely for illustrating the present application, but do not limit the scope of the present application. Likewise, the following embodiments are only some, but not all, of the embodiments of the present application, and all other embodiments obtained by one of ordinary skill in the art without inventive effort are within the scope of the present application.

The terms "first," "second," "third," and the like in this application are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first", "a second", and "a third" may explicitly or implicitly include at least one such feature. In the description of the present application, the meaning of "a plurality" is at least two, such as two, three, etc., unless explicitly defined otherwise as an alternative. All directional indications (such as up, down, left, right, front, back … …) in this embodiment are merely used to explain the relative positional relationship, movement, etc. between the components in a particular gesture (as shown in the drawings), and if the particular gesture changes, the directional indication changes accordingly. Furthermore, the terms "comprise" and "have," as well as any variations thereof, are intended to cover a non-exclusive inclusion. A process, method, system, article, or apparatus that comprises a list of steps or elements is not limited to only those listed but may optionally include other steps or elements not listed or inherent to such process, method, article, or apparatus.

Reference herein to "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment may be included in at least one embodiment of the present application. The appearances of such phrases in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive of other embodiments. Those skilled in the art will explicitly and implicitly understand that the embodiments described herein may be combined with other embodiments.

Referring to fig. 1, the present application provides a PCIE extension line 10, where the PCIE extension line 10 includes a plurality of transmission units 100 and a second shielding layer 200, each transmission unit 100 includes a transmission line pair 110, a first shielding layer 120 and an inner shielding layer 130, the first shielding layer 120 is coated outside the transmission line pair 110, the inner shielding layer 130 is coated outside the first shielding layer 120, and the second shielding layer 200 is coated outside the inner shielding layer 130. Compared with the prior art, the PCIE extension line 10 provided in the present application wraps the first shielding layer 120 outside the transmission line pair 110, so that each transmission unit 100 has an independent shielding cavity, thereby preventing crosstalk between the transmission units 100, and wraps the second shielding layer 200 outside the inner quilt layer 130, so as to prevent interference of external signals to the transmission units 100.

In one embodiment, as shown in fig. 1, the transmission line pair 110 includes two transmission lines, each transmission line includes an inner conductor 111 and an insulating layer 112, the insulating layer 112 is covered outside the inner conductor 111, and the first shielding layer 120 is covered outside the insulating layer 112, so as to ensure the safety of the PCIE extension line 10.

Alternatively, inner conductor 111 is a single or multi-stranded wire of any one of materials including, but not limited to, silver plated copper, tin plated copper, bare copper, tin plated copper clad steel, tin plated copper clad aluminum, silver plated copper clad steel, silver plated copper clad aluminum, aluminum magnesium alloy conductor. The cross-sectional shape of the inner conductor 111 may be any of circular, elliptical, flat, or other shapes.

Optionally, the insulating layer 112 comprises a polyethylene insulating layer, a foamed polyethylene insulating layer, a polypropylene insulating layer, a foamed polypropylene insulating layer, a polyperfluoroethylene propylene insulating layer, a foamed polyperfluoroethylene propylene insulating layer, a polytetrafluoroethylene insulating layer, a foamed polytetrafluoroethylene insulating layer, a microporous polytetrafluoroethylene insulating layer, or a fusible polytetrafluoroethylene insulating layer.

In one embodiment, as shown in fig. 4, the insulating layer 112 includes a first sub-insulating layer 112a and a second sub-insulating layer 112b, the first sub-insulating layer 112a is covered outside the inner conductor 111, the second sub-insulating layer 112b is covered outside the first sub-insulating layer 112a, and the first shielding layer 120 is covered outside the second sub-insulating layer 112 b. The first sub-insulating layer 112a and the second sub-insulating layer 112b may further improve the security of the PCIE extension line 10.

In one embodiment, the first shielding layer 120 may be any one of a hot-melt self-adhesive aluminum foil layer, a hot-melt self-adhesive copper foil layer, a hot-melt self-adhesive silver-plated copper foil layer, a hot-melt self-adhesive tin-plated copper foil, and a hot-melt self-adhesive tin-plated aluminum foil. The first shielding layer 120 may be wrapped on the insulating layer 112, or may be a straight wrap.

In one embodiment, the inner layer 130 is wrapped around the first shielding layer 120 to protect the first shielding layer 120, thereby improving the security of the PCIE extension line 10.

In one embodiment, each transmission unit 100 further includes a ground line 140, and the ground line 140 is disposed between the insulating layer 112 and the first shielding layer 120 and electrically connected to the first shielding layer 120. The material of the ground wire 140 includes, but is not limited to, any one of silver-plated copper, tin-plated copper, bare copper, tin-plated copper-clad steel, tin-plated copper-clad aluminum, silver-plated copper-clad steel, silver-plated copper-clad aluminum, aluminum-magnesium alloy conductors. The cross-sectional shape of the ground wire 140 may be any of circular, elliptical, flat, or other shapes.

It is understood that in other embodiments, the ground line 140 may also be disposed between the first shielding layer 120 and the inner cover 130 and electrically connected to the first shielding layer 120.

Alternatively, the number of the ground wires 140 may be one or more. For example, the number of the ground wires 140 is two, and the two ground wires 140 are respectively disposed on two opposite sides of the first shielding layer 120.

In one embodiment, the second shielding layer 200 may be any one of a hot-melt self-adhesive aluminum foil layer, a hot-melt self-adhesive copper foil layer, a hot-melt self-adhesive silver-plated copper foil layer, a hot-melt self-adhesive tin-plated copper foil, and a hot-melt self-adhesive tin-plated aluminum foil.

In one embodiment, as shown in fig. 2, the second shielding layer 200 is wound around the inner cover layer 130 to cover the plurality of transmission units 100, thereby preventing the transmission units 100 from being disturbed by external signals. The second shielding layer 200 includes a main body 230 and two connection portions 240, wherein the two connection portions 240 are respectively connected to two sides of the main body 230, and the two connection portions 240 are adhered.

In another embodiment, as shown in fig. 1, the second shielding layer 200 includes a first sub-shielding layer 210 and a second sub-shielding layer 220, where the first sub-shielding layer 210 and the second sub-shielding layer 220 are disposed opposite to each other, so that the second shielding layer 200 is coated on the inner passivation layer 130. The first sub-shielding layer 210 includes a first body portion 211 and two first pairs of attachment portions 212, the two first pairs of attachment portions 212 are respectively connected to two sides of the first body portion 211, the second sub-shielding layer 220 includes a second body portion 221 and two second pairs of attachment portions 222, the two second pairs of attachment portions 222 are respectively connected to two sides of the second body portion 221, and the two first pairs of attachment portions 212 are adhered to the two second pairs of attachment portions 222.

In one embodiment, as shown in fig. 3, the PCIE extension line further includes an outer cover layer 300, and the outer cover layer 300 is wrapped around the second shielding layer 200 to protect the second shielding layer 200. The outer coating 300 may be a nonmetallic film or an extruded plastic sheath.

In one embodiment, the outer cap layer 300 includes a first sub-outer cap layer 310 and a second sub-outer cap layer 320, the first sub-outer cap layer 310 is coated on the first sub-shielding layer 210, and the second sub-outer cap layer 320 is coated on the second sub-shielding layer 220.

Compared with the prior art, the PCIE extension line 10 provided in the present application wraps the first shielding layer 120 outside the transmission line pair 110, so that each transmission unit 100 has an independent shielding cavity, thereby preventing crosstalk between the transmission units 100, and wraps the second shielding layer 200 outside the inner quilt layer 130, so as to prevent interference of external signals to the transmission units 100.

The foregoing is only a part of the embodiments of the present application, and is not intended to limit the scope of the present application, and all equivalent devices or equivalent process transformations made by using the descriptions and the contents of the present application, or direct or indirect application to other related technical fields, are included in the scope of patent protection of the present application.

Claims

1. A PCIE extension line, comprising:

each transmission unit comprises a transmission line pair, a first shielding layer and an inner coating layer, wherein the first shielding layer is coated on the transmission line pair, and the inner coating layer is coated on the first shielding layer;

and the second shielding layer is coated on the inner quilt layer.

2. The PCIE extension cord of claim 1 wherein the second shield layer is disposed outside the inner quilt layer.

3. The PCIE extension line of claim 2 wherein the second shielding layer includes a main body portion and two connection portions, the two connection portions are respectively connected to two sides of the main body portion, and the two connection portions are adhered.

4. The PCIE extension line of claim 1 wherein the second shield layer comprises a first sub-shield layer and a second sub-shield layer, the first sub-shield layer and the second sub-shield layer being disposed opposite to each other.

5. The PCIE extension line of claim 4 wherein the first sub-shield layer comprises a first body portion and two first pairs of attachment portions, the two first pairs of attachment portions are respectively connected to two sides of the first body portion, the second sub-shield layer comprises a second body portion and two second pairs of attachment portions, the two second pairs of attachment portions are respectively connected to two sides of the second body portion, and the two first pairs of attachment portions and the two second pairs of attachment portions are respectively attached.

6. The PCIE extension cord of claim 4 further comprising an outer cover layer that wraps the first sub-shield layer and the second sub-shield layer.

7. The PCIE extension line of claim 6 wherein the outer cover layer comprises a first sub-outer cover layer and a second sub-outer cover layer, the first sub-outer cover layer being wrapped around the first sub-shield layer, the second sub-outer cover layer being wrapped around the second sub-shield layer.

8. The PCIE extension line of claim 1 wherein the transmission unit further comprises a ground line disposed between the transmission line pair and the first shield layer or between the first shield layer and an inner quilt layer.

9. The PCIE extension line of claim 1 wherein the pair of transmission lines comprises two transmission lines, each transmission line comprising an inner conductor and an insulating layer, the insulating layer coating the inner conductor, the first shielding layer coating the insulating layer.

10. The PCIE extension line of claim 9 wherein the insulation layer comprises a first sub-insulation layer and a second sub-insulation layer, the first sub-insulation layer is coated on the inner conductor, the second sub-insulation layer is coated on the first sub-insulation layer, and the first shielding layer is coated on the second sub-insulation layer.