CN220627803U - Semiconductor packaging structure and chip comprising same - Google Patents

Abstract

The present disclosure relates to semiconductor package structures and chips including the same. A semiconductor package structure includes: a multi-layered substrate core formed by reducing a thickness of a single-layered substrate core and applying lamination on the single-layered substrate core; and a Si capacitor embedded in the multilayer substrate core. According to the semiconductor packaging structure, ESL and ESR of the embedded capacitor can be remarkably reduced, the performance of the capacitor is improved, the mechanical strength of the substrate core can be ensured, and the number of ABF layers is reduced. The present disclosure also relates to a chip comprising such a semiconductor package structure.

Description

Semiconductor packaging structure and chip comprising same

Technical Field

The present disclosure relates to the field of semiconductor device design and fabrication. More particularly, the present disclosure relates to a semiconductor package structure manufactured using a technology of embedding a Si capacitor (Si capacitor) or a Si Cap (silicon capacitor) in a multilayer substrate core (substrate core), and a chip including the same.

Background

In a chip, as one of the package capacitances, a decoupling capacitance (decoupling capacitor) is typically used to mitigate or eliminate the effects of power supply coupling interference. In the prior art, decoupling capacitors are typically arranged in the form of MLCC capacitors (Multiplayer Ceramic Chip Capacitor, multilayer ceramic chip capacitors), which are typically arranged over the package substrate or over the substrate backside (ground side).

However, there are a number of disadvantages to using MLCCs, such as too far from the chip core, too high ESL (equivalent series inductance) and/or ESR (equivalent series resistance), limited noise rejection range, etc.

Accordingly, new capacitor deployment techniques are needed to at least partially address the shortcomings of the prior art and to improve capacitor performance.

Disclosure of Invention

To this end, the present disclosure proposes a new way of capacitor deployment.

According to a first aspect of the present disclosure, there is provided a semiconductor package structure including: a multi-layered substrate core formed by reducing a thickness of a single-layered substrate core and applying lamination on the single-layered substrate core; and a Si capacitor embedded in the multilayer substrate core.

According to the semiconductor package structure of the present disclosure, a higher capacitance density is provided by employing Si capacitance, and a lower capacitance ESL is provided by embedding Si capacitance into the substrate core. Meanwhile, according to the semiconductor package structure of the present disclosure, the mechanical strength requirement of the substrate core and the thickness requirement of the embedded Si capacitor are simultaneously satisfied by replacing the single-layer substrate core with the multi-layer substrate core.

In one embodiment, the Si capacitance is embedded in a build-up of the multi-layer substrate core and/or the single-layer substrate core. In another embodiment, the multi-layer substrate core includes a plurality of laminates applied on one side of the single-layer substrate core, and the Si capacitance is embedded in the plurality of laminates. Thus, according to the above embodiments, numerous capacitor embedding schemes can be designed to flexibly accommodate the size, structure, size of the substrate core, structure, and other design layout requirements of the capacitor.

In one embodiment, the thickness of the embedded Si capacitor is adapted to the thickness of the structure into which it is to be embedded. In another embodiment, the thickness of the structure to be embedded in the Si capacitance is adapted to the thickness of the Si capacitance to be embedded. Therefore, according to the above embodiment, the flexibility of capacitor embedding can be increased by bi-directionally adapting the thickness of the Si capacitor and the thickness of the portion to be embedded, and the problem that the Si capacitor is not adapted to the substrate core with a larger thickness and cannot be embedded into such substrate core is avoided. In one embodiment, the Si capacitance has a thickness between 50 and 760 μm.

In one embodiment, the semiconductor package structure further includes a computing core located over the multi-layer substrate core, and the Si capacitance is located on a side of the multi-layer substrate core proximate to the computing core. In a preferred embodiment, the Si capacitance is located directly below the computation core. In a still preferred embodiment, the Si capacitance is connected to the compute core through a multi-termination connection. Therefore, according to the above-described embodiment, the ESL and ESR of the pad from the capacitor to the upper computing core can be reduced by disposing the Si capacitor directly under the computing core and the multi-termination connection, thereby effectively reducing the high-frequency AC noise and increasing the highest frequency of the chip.

In one embodiment, the Si capacitance comprises a DTC capacitance and/or a 3D MIM capacitance. Therefore, according to this embodiment, various forms of Si capacitance can be utilized, making full use of the high capacitance density of the Si capacitance.

According to a second aspect of the present disclosure, there is provided a chip comprising the semiconductor package structure as described above. Thus, the chip may have various possible embodiments of the semiconductor package structure as described above and advantages thereof.

In one embodiment, the Si capacitance is a package level decoupling capacitance of the chip. Therefore, according to the embodiment, the package-level decoupling capacitor of the chip is realized by using the novel capacitor deployment mode, so that the problems of excessively long distance between the decoupling capacitor and the core of the chip, ESL and ESR, limited noise filtering range and the like in the prior art are at least partially solved.

According to a third aspect of the present disclosure, there is provided a method of manufacturing a semiconductor package structure, comprising the steps of: providing a single-layer substrate core; reducing the thickness of the single-layer substrate core; applying at least one build-up layer on the reduced thickness single layer substrate core to form a multi-layer substrate core; forming a cavity in the multi-layer substrate core; and embedding a Si capacitor in the formed cavity.

Thus, with the manufacturing method according to the present disclosure, it is enabled to easily manufacture the semiconductor package structure proposed by the present disclosure with the existing single-layer substrate core.

In one embodiment, forming the cavity in the multi-layer substrate core includes forming the cavity only in the at least one build-up applied on the single-layer substrate core or simultaneously forming the cavity in the at least one build-up and the single-layer substrate core. In one embodiment, forming a cavity in the multi-layer substrate core includes adapting a thickness of the Si capacitor to be embedded to a thickness of the cavity into which it is to be embedded. Thus, according to the above embodiments, numerous capacitor embedding schemes can be designed to flexibly accommodate the size, structure, size of substrate core, structure, size of build-up layers, structure, and other design layout requirements of the capacitor.

In one embodiment, after embedding the Si capacitance, the method further comprises the step of applying one or more ABF layers over the multilayer substrate core. Thus, according to the present disclosure, combining embedded capacitors with the build-up of the substrate core enables the thickness of the ABF layer to be reduced, thereby improving power transfer.

It is noted that one or more features described in the different aspects of the present disclosure may be combined with one or more features described in other aspects to form embodiments of the present disclosure. Thus, the embodiments described above are obviously not exhaustive.

Drawings

The above and other features, details and advantages of the present disclosure will become apparent upon reading the following detailed description and studying the drawings, wherein:

FIG. 1 shows one example of a schematic diagram of a chip circuit;

FIG. 2 schematically illustrates one example of an arrangement of MLCC capacitors according to the prior art;

FIG. 3 schematically illustrates an example structure of a Si capacitor;

fig. 4 schematically illustrates one preferred example of a capacitive arrangement according to the present disclosure;

fig. 5 schematically illustrates another preferred example of a capacitive arrangement according to the present disclosure;

fig. 6 schematically illustrates another preferred example of a capacitive arrangement according to the present disclosure;

fig. 7 schematically illustrates another preferred example of a capacitive arrangement according to the present disclosure; and

fig. 8A to 8G schematically show a manufacturing flow of a capacitive arrangement according to the present disclosure.

Detailed Description

Fig. 1 shows an example of a schematic diagram of a chip circuit. As shown in FIG. 1As shown, when designing a chip, the chip is generally divided into an innermost die level (die), a package level (package), a reticle level (MB), and an outermost chip level (chip). The power supply and voltage regulation modules (Voltage Regulator Module, VRM) for regulating the input voltage to a stable output voltage are typically disposed in the outermost chip level (chip) and deliver voltage to devices in the die level via various devices in the motherboard and package levels. For this purpose, decoupling capacitors are required in the package level (and possibly the reticle level) to absorb fluctuating disturbances in the voltage transfer or to filter out supply noise in general. Meanwhile, since the package capacitor is provided, C is used in FIG. 1 _pkg Expressed, an equivalent package inductance is thus created, represented by L in FIG. 1 _pkg1 And L _pkg2 To represent.

As previously described, in the prior art, an MLCC capacitor is generally employed as such a decoupling capacitor. Fig. 2 schematically shows an example of an arrangement of MLCC capacitors according to the prior art. As shown in fig. 2, in the related art, an MLCC capacitor as a decoupling capacitor may be disposed on a substrate surface, and thus referred to as a surface side capacitor (surface side capacitor), as schematically shown in the MLCC 1 of fig. 2. In another example, the MLCC capacitance as the decoupling capacitance may be disposed on a surface of the substrate backside (ground side), thus referred to as backside capacitance (land side capacitor), as schematically illustrated by MLCC 2 in fig. 2.

However, as the chip size increases, the surface side capacitance becomes farther and farther from the chip core (e.g., the substrate core in fig. 2), which results in an equivalent package inductance L _pkg1 And/or L _pkg2 Increasing. On the other hand, although the back side capacitance may be a short distance from the substrate core, in the case of disposing the back side capacitance, the core thickness is increased to 1.2mm or more in order to control the larger package. And the larger spacing of the thicker cores and plated through holes also increases the equivalent package inductance of the backside capacitance. Thus, a high equivalent package inductance (e.g., L shown in FIG. 1 _pkg1 And/or L _pkg2 ) So that the decoupling capacitor cannot effectively filter power supply noise of about 10 to 1000 MHz.

In addition, the equivalent package inductance increases for the package capacitance, whether it is deployed as a surface side capacitance or as a back side capacitance.

For this case, it is proposed to implement the decoupling capacitance in the form of Si capacitance (capacitance formed in the silicon interposer), that is, si capacitance as the decoupling capacitance is embedded in the substrate core. The 3D Si capacitance may include a capacitance formed within the Si substrate, such as a deep trench capacitance (Deep Trench Capacitor, DTC capacitance), or a capacitance formed on the Si substrate, such as a 3D MIM capacitance (metal-insulator-metal capacitance). An example structure of the Si capacitor is shown in fig. 3. The use of Si capacitors may provide higher capacitance densities than the MLCC capacitors described above. In addition, embedding the capacitor into the substrate core enables a lower capacitance ESL to be provided. The thickness of the Si capacitor may be about 770 μm. Therefore, for a substrate core having a thickness of 600 μm or less, it is possible to embed Si capacitance in the substrate core.

In such a solution, the substrate core used is typically a glass fiber substrate core doped with a resin. In addition, in the existing substrate, the substrate core is generally a single Layer, and at least one ABF Layer (Ajinomoto Build-up Film Layer ) is generally applied on the single Layer substrate core. In this configuration, the substrate core is required to have a higher mechanical strength than the ABF layer. For large packages, it is desirable to increase the thickness of the substrate core to about 1000 μm or more (typically 1200 μm or more) to increase the mechanical strength of the substrate and reduce warpage. However, it is difficult to embed Si capacitors in substrate cores with a thickness of 800 μm or more.

The present solution is proposed for the above situation. Fig. 4 schematically shows one preferred example of a capacitive arrangement according to the present disclosure.

In one aspect, the present disclosure proposes to use a multi-layer substrate core instead of a single-layer substrate core. According to one embodiment, the multi-layer substrate core may be realized by reducing the thickness of an existing substrate core and applying at least one build-up layer on the substrate core. In some embodiments, as shown in brackets labeled with reference numeral 402, it is a substrate core with at least one build-up layer that is included in a package substrate as shown in brackets labeled with reference numeral 401. In one embodiment, the laminate may be a prepreg ply (Prepeg ply). As shown in the preferred embodiment of fig. 4, the multi-layered substrate may be a substrate to which two laminates are applied, the laminates being on upper and lower sides of the substrate core, respectively. In accordance with the present disclosure, combining multiple build-up layers helps the substrate core meet strength requirements and reduces package warpage. At the same time, the applied build-up layer or layers also help to meet the thickness requirements required for embedded Si capacitors, e.g. less than 800 μm. According to the present disclosure, the formed multilayer substrate has mechanical strength comparable to a single layer substrate of higher thickness.

In another aspect, the present disclosure proposes embedding Si capacitors into one or more laminates of an applied multilayer substrate by adapting the thickness of the Si capacitors to the thickness of the one or more laminates. The present disclosure also proposes that the Si capacitance may be embedded into the one or more laminates of the applied multilayer substrate and the substrate core simultaneously by adapting the thickness of the Si capacitance to the thickness of the one or more laminates and the substrate core.

In accordance with the present disclosure, the Si capacitance to be embedded may include, for example, DTCs, 3D MIM capacitors, and the like. DTC is one of Si capacitors. The DTCs may be formed by slotting in the material of the substrate core. Meanwhile, for a part of the substrate core not having the DTC forming condition, other forms of Si capacitance may be adopted. Thus, even a substrate that cannot form a DTC can implement the technical solution of the present disclosure by forming an embedded Si capacitor on a silicon interposer, thereby improving the performance of the capacitor.

In some embodiments, embedding one or more Si capacitors in a build-up of a multilayer substrate may accommodate thickness limitations of such capacitors in accordance with the present disclosure. In one embodiment, the thickness of the Si capacitance to be embedded is between 50 and 760 μm. Thus, the Si capacitance and the build-up or both the Si capacitance and the build-up and the substrate core may be adapted by adjusting the thickness of the existing substrate core, adjusting the thickness of the applied build-up, adjusting the thickness of the capacitance to be embedded, or a combination of the above adjustments. This avoids the problem of the Si capacitance not fitting into the substrate core of greater thickness as described above, resulting in an inability to embed into such substrate core. As shown in the preferred embodiment of fig. 4, the thickness of the Si capacitor is adapted to the thickness of and embedded in the stack between the substrate core and the computing core. According to the present disclosure, combining the build-up of embedded capacitors and substrate cores enables the strength requirements (i.e., mechanical strength) of the substrate cores to be met while also reducing the thickness of the ABF layer, thereby improving power transfer.

In a preferred embodiment, one or more embedded capacitors may be disposed directly below the computing core, as shown in the preferred embodiment of FIG. 4. According to this embodiment, such an arrangement enables vertical connection to the computing core directly above, thereby enabling multi-terminal connection (multiple termination connection). In this case, with a multi-termination connection, the ESL and ESR from the capacitance to the pad of the computation core above would be much lower. According to one particular embodiment, the total ESL from the embedded capacitance to the pad of the compute core using the capacitive deployment of the present disclosure may be reduced to about 10pH. Furthermore, with the deployment of the present disclosure, high frequency AC noise will be reduced by at least 50%, which effectively increases the highest frequency Fmax of the overall chip at a fixed VRM input voltage or lower voltage at the same power.

In another preferred embodiment, one or more embedded capacitors may be arranged directly below the core that most requires high current. Similar to the preferred embodiment arranged directly below the compute core, according to this preferred embodiment multiple vertical connections to each core directly above can be achieved, achieving low ESL capacitance, providing better power transfer for the cores above that require high current. In a further preferred embodiment, one or more embedded capacitors may also be arranged directly under the switching power supply module.

As will be appreciated by those skilled in the art, there are various possible embodiments of the lamination application scheme and the capacitive embedding scheme according to the present disclosure. For example, in one preferred embodiment, a single laminate, such as a Prepeg prepreg ply, may be applied over and under the substrate core, and one or more Si capacitors embedded in the single laminate (e.g., prepeg prepreg ply) over the substrate core, as shown in the preferred embodiment of fig. 5, more specifically as shown in brackets labeled 501. In another preferred embodiment, a single build-up layer may be applied over and under the substrate core and one or more Si capacitors embedded in the single build-up layer over the substrate core and in the substrate core, as shown in the preferred embodiment of fig. 6, more particularly as shown in brackets labeled 601. In the preferred embodiment, the upper cladding layer and substrate core may be etched with a laser to form one or more cavities and one or more Si capacitors embedded in the one or more cavities. In yet another preferred embodiment, multiple layers may be applied over and under the substrate core, and one or more Si capacitors embedded in the multiple layers over the substrate core, as shown in the preferred embodiment of fig. 7, more particularly as shown in brackets labeled 701. Also in this preferred embodiment, one or more cavities may be formed by laser etching through multiple layers of material above and embedding capacitors into the one or more cavities. In the above preferred embodiments, according to the present disclosure, whether the capacitor is embedded in a single laminate, laminate and core, or multiple laminates, it is necessary to adapt the thickness of the capacitor embedding to the thickness of the portion to be embedded.

Furthermore, as will be appreciated by those skilled in the art, other build-up application schemes and capacitive embedding schemes may be designed to achieve a desired capacitance density, as low an ESL as possible, a desired substrate thickness, and/or a desired circuit interconnect pattern, depending on the actual circumstances of the chip design, the placement and routing of other devices, and/or the actual dimensions of the embedded capacitors employed. As one non-limiting example, multiple capacitors may be embedded in multiple build-ups of a substrate core in a stacked, staggered arrangement, etc., to achieve a wide variety of interconnect layouts. As another non-limiting example, a portion of the capacitance may also be embedded in the build-up layer on the underside of the substrate core.

Next, a manufacturing flow of the embedded capacitor according to the present disclosure is described with reference to fig. 8A to 8G.

In a first step, as shown in fig. 8A, a multi-layered substrate is formed, which includes a substrate core of reduced thickness and at least one build-up layer, and metal pads are formed (e.g., deposited) in the formed multi-layered substrate in accordance with a chip design.

In the second step, as shown in fig. 8B, laser cavities are formed in the formed multilayer substrate in accordance with the chip design. As described above, depending on the particular embedding of the one or more embedded capacitors, the laser cavity may be formed across a single build-up of the multi-layer substrate (e.g., the preferred embodiment shown in fig. 5), across one or more build-up and substrate core (e.g., the preferred embodiment shown in fig. 6), or across multiple build-ups (e.g., the preferred embodiment shown in fig. 7).

In a third step, as shown in fig. 8C, an embedded capacitor is embedded in the formed cavity. In this step, the thickness of the Si capacitance may optionally be reduced to accommodate the thickness of the laser cavity formed. Further, in this step, the bottom of the capacitor may be optionally fastened to the substrate by, for example, an adhesive or the like to enhance mechanical strength.

In a fourth step, as shown in fig. 8D, one or more ABF layers are applied over the multilayer substrate, more specifically, over the uppermost build-up layer, to fill the gaps and form the top and/or bottom layers. In this step, since the embedded capacitor is embedded in the multilayer substrate, the number of layers of ABF layer applied can be reduced compared to the prior art.

In a fifth step, as shown in fig. 8E, vias are formed (e.g., by laser etching) on the applied ABF layer(s) to expose the build-up pad and/or Si capacitor pad.

In a sixth step, as shown in fig. 8F, metallization/metal fill is performed on the ABF layer in the exposed vias to achieve interconnection across the ABF layer.

Finally, in a seventh step, as shown in fig. 8G, the metallization formed in the ABF layer is further processed to finally complete the substrate build.

Although the capacitor arrangement according to the present disclosure is mainly described above in connection with decoupling capacitors, in practice embedded Si capacitors according to the present disclosure may also be used as power regulating capacitors on chip and/or on package. In addition, the capacitive arrangement according to the present disclosure is particularly suitable for chips employing flip chip ball grid array (FlipChip Ball Grid Array, FCBGA) structures and enables improved die power transfer of FCBGA structures.

It will be understood by those skilled in the art that various modifications or variations in detail may be made in the semiconductor package structure according to the present disclosure without departing from the scope of the disclosure as claimed.

Claims (12)

1. A semiconductor package structure, comprising:

a multi-layered substrate core formed by reducing a thickness of a single-layered substrate core and applying lamination on the single-layered substrate core; and

and a Si capacitor embedded in the multilayer substrate core.

2. The semiconductor package structure according to claim 1, wherein the Si capacitor is embedded in a build-up of the multi-layer substrate core and/or the single-layer substrate core.

3. The semiconductor package structure according to claim 1, wherein the multilayer substrate core includes a plurality of build-up layers applied on one side of the single-layer substrate core, and the Si capacitance is embedded in the plurality of build-up layers.

4. A semiconductor package according to any one of claims 1 to 3, wherein the thickness of the embedded Si capacitor is adapted to the thickness of the structure into which it is to be embedded.

5. A semiconductor package structure according to any one of claims 1 to 3, wherein the thickness of the structure to be embedded with the Si capacitor is adapted to the thickness of the Si capacitor to be embedded.

6. A semiconductor package according to any one of claims 1 to 3, wherein the Si capacitance has a thickness between 50 and 760 μm.

7. A semiconductor package structure according to any one of claims 1 to 3, further comprising a computation core located above the multilayer substrate core, and the Si capacitance is located on a side of the multilayer substrate core close to the computation core.

8. The semiconductor package according to claim 7, wherein the Si capacitance is located directly below the computing core.

9. The semiconductor package according to claim 8, wherein the Si capacitance is connected to the compute core through a multi-termination connection.

10. A semiconductor package according to any of claims 1 to 3, wherein the Si capacitance comprises a DTC capacitance and/or a 3D MIM capacitance.

11. A chip characterized in that it comprises the semiconductor package structure according to any one of claims 1 to 10.

12. The chip of claim 11, wherein the Si capacitance is a package-level decoupling capacitance of the chip.