CN220605591U - Anti-interference charging awakening circuit based on BMS - Google Patents
Anti-interference charging awakening circuit based on BMS Download PDFInfo
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- CN220605591U CN220605591U CN202322284259.0U CN202322284259U CN220605591U CN 220605591 U CN220605591 U CN 220605591U CN 202322284259 U CN202322284259 U CN 202322284259U CN 220605591 U CN220605591 U CN 220605591U
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- 239000003990 capacitor Substances 0.000 claims abstract description 19
- 238000005070 sampling Methods 0.000 abstract description 2
- 238000010586 diagram Methods 0.000 description 5
- 230000000694 effects Effects 0.000 description 5
- 230000002159 abnormal effect Effects 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000008094 contradictory effect Effects 0.000 description 1
- 230000003203 everyday effect Effects 0.000 description 1
- 238000001914 filtration Methods 0.000 description 1
- GELKBWJHTRAYNV-UHFFFAOYSA-K lithium iron phosphate Chemical compound [Li+].[Fe+2].[O-]P([O-])([O-])=O GELKBWJHTRAYNV-UHFFFAOYSA-K 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
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- Charge And Discharge Circuits For Batteries Or The Like (AREA)
Abstract
The utility model discloses an anti-interference charging awakening circuit based on a BMS (battery management system), which comprises a voltage dividing circuit, a control switch and an MCU (micro control unit), wherein one end of the voltage dividing circuit is provided with a power supply anode at the output end of a battery pack, the other end of the voltage dividing circuit is connected with the control circuit, and the other end of the control circuit is connected with an LDO (low dropout regulator); the control switch is connected with the control circuit and used for triggering the on and off of the control circuit; the MCU power supply end is connected with the LDO, and the MCU signal output end is connected with the control switch. The voltage divider circuit is used for sampling the positive terminal voltage of the output end of the battery pack, the voltage is connected to the control circuit after voltage division, the control circuit is used for controlling the opening of the LDO, and when the voltage input into the control circuit fails to reach the enabling voltage value, the LDO cannot be opened, so that the aim of preventing the battery pack from being started by mistake due to the interference of the positive terminal level is achieved. The divided voltage is connected with the capacitor in series and then grounded, so that the aim of preventing the battery pack from being started by mistake caused by interference conditions such as ESD, EMI and the like is fulfilled.
Description
Technical Field
The utility model relates to the technical field of battery management systems, in particular to an anti-interference charging wake-up circuit based on a BMS.
Background
Outdoor battery packs, commonly referred to as outdoor power supplies, are becoming more common in everyday business. Outdoor battery packs are typically low voltage, normally on power supplies, and for such battery packs it is normal practice to wake up the entire battery pack when the charger is plugged in to charge it. However, in reality, various interference conditions often exist, and when a charging gun is not fully inserted yet, voltage fluctuation caused by poor contact causes the battery pack to be started by interference; some battery packs are used in environments that are relatively harsh, such as being charged with complex ESD and EMI, and the entire battery pack is disturbed and opened even if no charger is inserted. When the MOSFET is at the high side, the abnormal starting of the battery pack is caused by the voltage fluctuation of the positive electrode of the power supply at the output end of the battery pack.
Therefore, there is a need for an anti-interference wake-up circuit for battery pack charging, which solves the problem of false start-up caused by the battery pack MCU receiving the level jitter of the positive end of the battery output end.
Disclosure of Invention
The utility model provides an anti-interference charging awakening circuit based on a BMS, which can be integrated on the BMS or used as an independent module to be combined with the BMS, the voltage at the positive end of the output end of a battery pack is sampled through a voltage dividing circuit, the voltage is connected into a control circuit after voltage division, and the control circuit is used for controlling the opening of an LDO (low dropout regulator) so as to achieve the aim of preventing the wrong starting up of the battery pack caused by the interference of the level at the positive end. The divided voltage is connected with the capacitor in series and then grounded, so that the aim of preventing the battery pack from being started by mistake due to interference conditions such as ESD, EMI and the like is fulfilled.
According to the BMS-based anti-interference charging wake-up circuit, the charging wake-up circuit can be integrated on the BMS or used as a single module in combination with the BMS, and comprises a voltage dividing circuit, a control switch and an MCU, wherein one end of the voltage dividing circuit is connected with the positive electrode of a battery pack output end power supply, the other end of the voltage dividing circuit is connected with the control circuit, and the other end of the control circuit is connected with an LDO; the control switch is connected with the control circuit and is used for triggering the on and off of the control circuit; the MCU power supply end is connected with the LDO, and the MCU signal output end is connected with the control switch.
As an alternative scheme of the technical scheme of the utility model, the voltage dividing circuit comprises a first resistor and a second resistor which are connected in series, the other end of the first resistor is connected with the positive electrode of the power supply at the output end of the battery pack, and the other end of the second resistor is grounded; the first diode and the third resistor are connected in series, and the anode of the first diode is connected between the first resistor and the second resistor.
As an alternative of the technical scheme of the present utility model, the control circuit includes an integrated circuit, the voltage input end of the integrated circuit is connected with the third resistor, and the voltage input end is connected with the first capacitor in series and then grounded; the integrated circuit enabling end is connected with the voltage input end after being connected with a fourth resistor in series; the voltage output end of the integrated circuit is connected with the LDO after being connected with the second diode in series, the voltage output end is connected with the anode of the second diode, and the voltage output end is grounded after being connected with the second capacitor in series.
As an alternative of the technical scheme of the utility model, the control switch comprises an NMOS tube, wherein the source electrode of the NMOS tube is grounded, the drain electrode of the NMOS tube is connected to the enabling end of the integrated circuit, and the grid electrode is connected with a fifth resistor and a sixth resistor in series and then grounded.
As an alternative of the technical scheme of the utility model, the signal output end of the MCU is connected between the fifth resistor and the sixth resistor.
As an alternative scheme of the technical scheme of the utility model, a voltage-stabilizing diode is also connected between the source electrode and the grid electrode of the NMOS tube, wherein the source electrode is connected with the anode of the voltage-stabilizing diode, and the grid electrode is connected with the cathode of the voltage-stabilizing diode.
As an alternative of the technical scheme of the present utility model, a third capacitor is further connected between the source electrode and the gate electrode of the NMOS transistor.
The beneficial effects obtained by the utility model are as follows: the voltage divider circuit is used for sampling the positive terminal voltage of the output end of the battery pack, the voltage is connected to the control circuit after voltage division, the control circuit is used for controlling the opening of the LDO, and when the voltage input into the control circuit fails to reach the enabling voltage value, the LDO cannot be opened, so that the aim of preventing the battery pack from being started by mistake due to the interference of the positive terminal level is achieved. The divided voltage is connected with the capacitor in series and then grounded, so that the aim of preventing the battery pack from being started by mistake caused by interference conditions such as ESD, EMI and the like is fulfilled.
The effects of the present utility model are not limited to the above-described effects, and those skilled in the art can obtain effects not described above from the following description.
Drawings
Fig. 1 is a schematic diagram of a BMS-based anti-interference charging wake-up circuit system according to the present utility model.
Fig. 2 is a schematic diagram of a BMS-based anti-interference charging wake-up circuit according to the present utility model.
Fig. 3 is a schematic diagram of anti-interference charging wake-up circuit parameters based on a BMS according to the present utility model.
Detailed Description
In order to make the technical problems, technical solutions and advantageous effects solved by the present utility model more apparent, the present utility model is further described in detail below with reference to the accompanying drawings and examples. It should be understood that the following specific examples are intended to illustrate the utility model and are not intended to limit the utility model. All other embodiments, which can be made by a person skilled in the art without any inventive effort, are based on the following examples, which fall within the scope of the utility model.
It should be noted that, in the description of the present utility model, the positional or positional relationship indicated by the terms such as "upper", "lower", "left", "right", "front", "rear", etc. are based on the positional or positional relationship of the drawings, and are merely for convenience of description of the present utility model, and are not indicative or implying that the apparatus or element in question must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be construed as limiting the present utility model. In the description of the embodiments, the terms "disposed," "connected," and the like are to be construed broadly unless otherwise specifically indicated and defined. The specific meaning of the above terms in the present utility model will be understood in specific cases by those of ordinary skill in the art.
The anti-interference charging wake-up circuit system based on the BMS according to the present utility model as shown in FIG. 1 is implemented by controlling whether an LDO (Low drop out) supplies power to an MCU (Microcontroller Unit, micro control unit) to thereby realize whether the BMS (Battery Management System ) turns on the battery pack charging. The charging wake-up circuit comprises a voltage dividing circuit, a control switch and an MCU, wherein the positive electrode of a power supply at the output end of the battery pack is connected to the control circuit after passing through the voltage dividing circuit, the other end of the control circuit is connected with the LDO in a direct current positive way, when the voltage after voltage division reaches the enabling voltage of the control circuit, the control circuit is conducted, a voltage signal normally supplies power to the MCU at the later stage through the control circuit and the LDO, and the BMS starts the battery pack to charge; when the divided voltage does not reach the enabling voltage of the control circuit, the control circuit is turned off, the voltage signal is disconnected from the LDO, and therefore power supply to the MCU of the later stage is disconnected, and the BMS stops charging of the battery pack. The control switch is connected with the control circuit and used for controlling the on and off of the control circuit. The MCU power supply end is connected with the LDO, the signal output end is connected with the control switch, and the MCU controls the control switch through the signal output end under different conditions, so that the control circuit is controlled to be turned on and off.
As shown in fig. 2, the anti-interference charging wake-up circuit schematic diagram based on the BMS according to the present utility model includes a first resistor R1 and a second resistor R2 connected in series, wherein an upper end of the first resistor R1 is connected to a power supply positive electrode of an output end of a battery pack, and a lower end of the second resistor R2 is grounded. The voltage dividing circuit further comprises a first diode D1 and a third resistor R3 which are connected in series, wherein the positive electrode of the first diode D1 is connected between the first resistor R1 and the second resistor R2. The voltage dividing circuit adjusts the voltage values output from the first diode D1 and the third resistor R3 by setting different resistance values of the first resistor R1 and the second resistor R2. The control circuit comprises an integrated circuit U1, wherein a voltage input end VIN of the integrated circuit U1 is connected with the other end of the third resistor R3, and the voltage input end VIN is connected with a first capacitor C1 in series and then is grounded together with a grounding end GND; the enable end EN of the integrated circuit U1 is connected with the voltage input end VIN after being connected with the fourth resistor R4 in series; the voltage output end VOUT of the integrated circuit U1 is connected with the second diode D2 in series and then is connected with the LDO, and is grounded after being connected with the second capacitor C2 in series, and the voltage output end VOUT is connected with the anode of the second diode D2. The first capacitor C1 and the second capacitor C2 filter the voltage input terminal VIN and the voltage output terminal VOUT of the integrated circuit U1 to the ground when they have a large level fluctuation. The second diode D2 can prevent the voltage from flowing into the integrated circuit U1 in the reverse direction to cause damage. The control switch comprises an NMOS tube Q1, wherein the source electrode of the NMOS tube Q1 is grounded, the drain electrode of the NMOS tube Q1 is connected with the enable end EN of the integrated circuit U1, and the grid electrode of the NMOS tube Q1 is connected with a fifth resistor R5 and a sixth resistor R6 in series and then grounded. The control switch also comprises a zener diode D3 and a third capacitor C3 which are connected in parallel between the source electrode and the grid electrode of the NMOS tube, wherein the source electrode is connected with the anode of the zener diode D3, and the grid electrode is connected with the cathode of the zener diode D3. The MCU power supply end is connected with the LDO, and the MCU signal output end is connected between the five resistors R5 and the sixth resistor R6 and is used for inputting a high-level signal to the grid electrode of the NMOS tube Q2. When no signal is input to the grid electrode of the NMOS tube Q1, the grid electrode is grounded at a low level, and the NMOS tube Q1 is closed; when the gate is connected to a high level, the NMOS transistor Q1 is turned on. Under the condition that the MCU output level is unstable, the third capacitor C3 can also enable the grid electrode of the NMOS tube Q1 to be connected with a high level, so that the NMOS tube Q1 is conducted.
In summary, the detailed layout of the anti-interference charging wake-up circuit based on the BMS of the present utility model is described, and the operation principle of the charging wake-up circuit is further described by describing in conjunction with FIG. 2.
The resistance values of the first resistor R1 and the second resistor R2 are determined in conjunction with the battery pack charging voltage and the enable voltage of the integrated circuit U1. When the charger is not inserted normally, the enable end EN voltage value of the integrated circuit U1 fails to reach the enable voltage value, the integrated circuit U1 is closed, the voltage signal is disconnected from the LDO, so that power supply to the MCU of the later stage is disconnected, and the BMS does not wake up for charging; when the charger is normally inserted, the enable end EN voltage value of the integrated circuit U1 reaches the enable voltage value, the integrated circuit U1 is conducted, voltage signals normally supply power to the MCU of the later stage through the integrated circuit U1 and the LDO, and the BMS wakes up for charging. When the battery pack is in a severe environment such as ESD and EMI, a large level fluctuation occurs at the voltage input terminal VIN and the voltage output terminal VOUT of the integrated circuit U1, the battery pack can be filtered to the ground through the first capacitor C1 and the second capacitor C2. When the battery pack is in a charging state, the MCU signal output end does not output signals, at the moment, the grid electrode of the NMOS tube Q1 is grounded through the fifth resistor R5 and the sixth resistor R6, the grid electrode is in a low level, the NMOS tube Q1 is kept closed, the integrated circuit U1 is kept on, and the battery pack maintains the charging state. After the battery pack is full, the MCU signal output end outputs a high level signal to the position between the fifth resistor R5 and the sixth resistor R6, the grid electrode of the NMOS tube Q1 is at a high level, the NMOS tube Q1 is conducted, the enable end EN of the integrated circuit U1 is grounded, the integrated circuit U1 is closed, and the battery pack stops charging.
As shown in fig. 3, according to the parameter schematic diagram of the anti-interference charging wake-up circuit based on the BMS of the present utility model, the measured battery pack adopts six strings of lithium iron phosphate 18650 cells, fourteen parallel, the voltage of a single cell is 3.65V, the capacity is 3350mAh, and the parameters of each element in the wake-up circuit are shown in fig. 3. The actual measurement has better anti-interference effect on the conditions of positive-side level interference, ESD, EMI and the like.
In summary, the anti-interference charging wake-up circuit based on the BMS provided by the utility model can be integrated on the BMS or used as a single module in combination with the BMS. The voltage values output from the first diode D1 and the third resistor R3 are adjusted by setting the resistance values of the first resistor R1 and the second resistor R2 which are different, so that the on and off of the integrated circuit U1 are controlled, whether the later LDO supplies power to the MCU is further controlled, whether the battery pack is awakened to charge is realized, and the aim of preventing the battery pack from being started by mistake due to the interference of the positive-end level is fulfilled. The first capacitor C1 and the second capacitor C2 arranged at the voltage input end VIN and the voltage output end VOUT of the integrated circuit U1 are used for filtering the large level fluctuation to the ground, so that the aim of preventing the battery pack from being started by mistake caused by interference conditions such as ESD, EMI and the like is fulfilled.
The above-described embodiments of the anti-interference charging wake-up circuit based on the BMS are only illustrative of preferred embodiments and are not intended to limit the present utility model, and any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present utility model should be included in the scope of the present utility model. In addition, the technical solutions between the embodiments may be combined with each other, but must be based on the implementation by those of ordinary skill in the art; when the combination of the technical solutions is contradictory or impossible to realize, it should be considered that the combination of the technical solutions does not exist and is not within the scope of protection claimed by the present utility model.
Claims (7)
1. Anti-interference wake-up circuit that charges based on BMS, the wake-up circuit that charges can integrate on BMS or use as independent module combines BMS, its characterized in that includes:
the voltage division circuit is connected with the positive electrode of the power supply at the output end of the battery pack, the other end of the voltage division circuit is connected with the control circuit, and the other end of the control circuit is connected with the LDO;
the control switch is connected with the control circuit and used for triggering the on and off of the control circuit;
and the power supply end of the MCU is connected with the LDO, and the signal output end of the MCU is connected with the control switch.
2. The anti-interference charging awakening circuit based on BMS (battery management system) as claimed in claim 1, wherein the voltage dividing circuit comprises a first resistor and a second resistor which are connected in series, the other end of the first resistor is connected with the positive electrode of a battery pack output end power supply, and the other end of the second resistor is grounded; the first diode and the third resistor are connected in series, and the anode of the first diode is connected between the first resistor and the second resistor.
3. The BMS-based anti-tamper charge wake-up circuit of claim 2 wherein said control circuit comprises an integrated circuit, said integrated circuit voltage input being connected to said third resistor while being connected in series with a first capacitor and then connected to ground; the integrated circuit enabling end is connected with the voltage input end after being connected with a fourth resistor in series; the voltage output end of the integrated circuit is connected with the LDO after being connected with the second diode in series, the voltage output end is connected with the anode of the second diode, and the voltage output end is grounded after being connected with the second capacitor in series.
4. The BMS-based anti-tamper charge wake-up circuit of claim 3 wherein the control switch comprises an NMOS transistor, wherein the NMOS transistor has a source connected to ground, a drain connected to the enable terminal of the integrated circuit, and a gate connected in series with a fifth resistor and a sixth resistor and then connected to ground.
5. The BMS-based anti-tamper charge wake-up circuit of claim 4 wherein the MCU signal output is terminated between a fifth resistor and a sixth resistor.
6. The BMS-based anti-interference charge wake-up circuit of claim 4, wherein a zener diode is further connected between the source and the gate of the NMOS transistor, wherein the source is connected to the positive pole of the zener diode and the gate is connected to the negative pole of the zener diode.
7. The BMS-based anti-interference charge wake-up circuit of claim 4, wherein a third capacitor is further connected between the source and the gate of the NMOS transistor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202322284259.0U CN220605591U (en) | 2023-08-24 | 2023-08-24 | Anti-interference charging awakening circuit based on BMS |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202322284259.0U CN220605591U (en) | 2023-08-24 | 2023-08-24 | Anti-interference charging awakening circuit based on BMS |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN220605591U true CN220605591U (en) | 2024-03-15 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202322284259.0U Active CN220605591U (en) | 2023-08-24 | 2023-08-24 | Anti-interference charging awakening circuit based on BMS |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN220605591U (en) |
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2023
- 2023-08-24 CN CN202322284259.0U patent/CN220605591U/en active Active
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