CN220603577U - Current sampling circuit - Google Patents
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- CN220603577U CN220603577U CN202322043291.XU CN202322043291U CN220603577U CN 220603577 U CN220603577 U CN 220603577U CN 202322043291 U CN202322043291 U CN 202322043291U CN 220603577 U CN220603577 U CN 220603577U
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- 238000004804 winding Methods 0.000 claims abstract description 139
- 239000003990 capacitor Substances 0.000 claims description 29
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- 238000004146 energy storage Methods 0.000 claims description 3
- 230000002159 abnormal effect Effects 0.000 abstract description 2
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- 238000010248 power generation Methods 0.000 description 2
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 1
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Abstract
The utility model discloses a current sampling circuit, which comprises a secondary winding output circuit and N primary winding input circuits, wherein the N primary winding input circuits are sequentially connected in series; the current sampling circuit further comprises a current transformer and a current acquisition unit, the output end of the N-th primary winding input circuit is respectively connected to the homonymous end of the primary winding of the current transformer and the reference ground, the heteronymous end of the primary winding of the current transformer is connected with the negative voltage end of the direct current voltage, the output end of the current transformer is connected to the input end of the current acquisition unit, and the output end of the current acquisition unit is connected to the current sampling port. According to the utility model, the current transformer is used for current sampling, and when the switching tube is inconsistent in time sequence or current is abnormal due to non-uniform capacitance, the current transformer can be used for collecting correct current waveforms, so that the primary winding power device is ensured to work in a reliable range, and the reliability of a product is greatly improved.
Description
Technical Field
The utility model relates to the technical field of electronic circuits, in particular to a current sampling circuit.
Background
With the increasing global energy crisis and the proposal of the 'two carbon' strategic target in China, the development and utilization of clean energy are imperative. Therefore, solar power generation is rapidly developed. In photovoltaic power generation and power transmission, the input voltage of a control system is very high and reaches several kilovolts, and the conventional single-stage power supply topology cannot be applied because the voltage stress of a switching tube cannot meet the design requirement, so that the cascade technology is often adopted for input voltage expansion.
Fig. 1 is a circuit structure of a conventional high-voltage-resistant overlapped flyback DC-DC converter with an automatic voltage equalizing function, and the design of the high-voltage-resistant overlapped flyback DC-DC converter in the 5 th period of 2001 in journal of electrotechnology explains the double-overlapping structure in detail, and meanwhile, fig. 1 is disclosed.
The circuit schematic diagram of the known high-voltage-resistant overlapped flyback DC-DC converter is shown in fig. 1, and the circuit schematic diagram comprises a primary winding input circuit and an output circuit, wherein the primary winding input circuit comprises two stages of identical primary winding units and voltage equalizing units which are connected in series, the primary winding units of each stage are connected in parallel with the voltage equalizing units, the primary winding units of each stage are connected in series with each other, and the voltage equalizing units of the first stage consist of a capacitor C1; the voltage equalizing unit of the second stage consists of a capacitor C2; the primary winding unit of the first stage comprises a primary winding N1 and a switching tube Q1, one end of the primary winding N1 is used as an input end of the primary winding unit of the first stage, the other end of the primary winding N1 is connected with a conducting current inflow end of the switching tube Q1, and a conducting current outflow end of the switching tube Q1 is used as an output end of the primary winding unit of the first stage. The primary winding unit of the second stage comprises a primary winding N2, a switching tube Q2 and a sampling resistor Rcs, one end of the primary winding N2 is used as an input end of the primary winding unit of the second stage, the other end of the primary winding N2 is connected with a conducting current inflow end of the switching tube Q2, a conducting current outflow end of the switching tube Q2 is connected with the sampling resistor Rcs and then is used for being connected with a current sampling pin of the control IC, and the other end of the sampling resistor Rcs is used as an output end of the primary winding unit of the second stage and is used for being grounded. The control end of each switching tube applies synchronous driving signals, and primary windings of all stages are controlled in phase and share a magnetic core.
The known circuit structure is different from the common single-ended flyback conversion in that the primary winding of the high-voltage-resistant overlapping flyback converter circuit is divided into two identical parts, namely a primary winding N1 and a primary winding N2, the primary windings N1 and N2 are respectively controlled to be on-off by switching tubes Q1 and Q2, and synchronous driving signals are applied to the gates of the switching tubes Q1 and Q2. In this way, under ideal operating conditions, the switching transistors Q1, Q2 are simultaneously turned on and off, and the potential at point a is equalized due to the consistency of the primary windings N1, N2. Although the circuit can solve the problem of over-high voltage stress of the switching tube, when the circuit is practically applied to products, a plurality of reliability problems exist. Because the on voltages of the two switching tubes and the driving signals of the two switching tubes cannot be perfectly consistent, there are many uncontrollable differences, which tend to cause the on and off of the power switching tubes Q1 and Q2 in the circuit structure to be unsynchronized, once the on and off of the power switching tubes Q1 and Q2 are unsynchronized, the following problems occur:
as shown in fig. 2, when the switching tube is turned on inconsistently, it is assumed that the switching tube Q1 is turned on first, and the terminal voltage Vc1 of the capacitor C1 is greater than the terminal voltage Vc2 of the capacitor C2 at this moment, because the switching tube Q2 is not turned on yet, the polarity of the primary winding N2 is positive and negative at this moment, the positive voltage V2 induced by the primary winding N2 will be greater than Vc2, and the positive voltage V2 charges the capacitor C2 positively through the body diode of the switching tube Q2, and at this moment, the positive current will increase, and a very large negative voltage will be generated on the resistor Rcs, which will affect the normal sampling of the control IC of the product. Because the resistor Rcs is negative pressure, the current sampling turn-off voltage of the control IC can not be reached, the control IC still provides driving, the peak current of the primary winding in the period is overlarge, and the phenomenon of damage to a switch tube caused by saturation of a magnetic core of the transformer can be caused when the peak current is serious.
Disclosure of Invention
Therefore, the present utility model is directed to a current sampling circuit, so as to solve the problem that the converter generates forward current due to asynchronous switching or unbalanced capacitance, which causes sampling error of control IC current and causes excessive peak current of primary winding, thereby damaging switching tube.
In order to solve the technical problems, the utility model is realized by the following technical measures:
the utility model provides a current sampling circuit, which comprises a secondary winding output circuit and N primary winding input circuits, wherein the N primary winding input circuits are sequentially connected in series, and N is an integer greater than or equal to 2;
each primary winding input circuit comprises a voltage equalizing unit and a primary switch unit, the voltage equalizing unit and the primary switch units are connected in parallel, and each primary switch unit is connected with a synchronous driving signal;
the current sampling circuit further comprises a current transformer and a current acquisition unit, the input end of the 1 st primary winding input circuit is connected to the positive voltage end of the direct current voltage, the output end of the N th primary winding input circuit is respectively connected to the homonymous end of the primary winding of the current transformer and the reference ground, the heteronymous end of the primary winding of the current transformer is connected with the negative voltage end of the direct current voltage, an energy storage capacitor is connected between the positive voltage end and the negative voltage end, the output end of the current transformer is connected to the input end of the current acquisition unit, and the output end of the current acquisition unit is connected to the current sampling port.
Further, the voltage equalizing unit comprises a capacitor, and the capacitor is connected with the primary switch unit in parallel.
Further, the primary switch unit comprises a primary winding and a switch tube, wherein a first end of the primary winding is connected with a first end of the voltage equalizing unit, a first end of the switch tube is connected with a synchronous driving signal, a second end of the switch tube is connected with a second end of the primary winding, and a third end of the switch tube is connected with a second end of the voltage equalizing unit.
Further, the current acquisition unit comprises a first resistor, a first diode and a second resistor, the homonymous end of the secondary winding of the current transformer is connected to the anode of the first diode, the anode of the first diode is connected to the reference ground through the first resistor, the cathode of the first diode is connected to the reference ground through the second resistor, the homonymous end of the secondary winding of the current transformer is connected to the reference ground, and the cathode of the first diode is connected to the current sampling port.
Further, the high-low voltage overcurrent compensation circuit is connected between the output end of the N-th primary winding input circuit and the same-name end of the primary winding of the current transformer, the input end of the high-low voltage overcurrent compensation circuit is connected to the output end of the N-th primary winding input circuit, the first output end of the high-low voltage overcurrent compensation circuit is connected to the current sampling port, and the second output end of the high-low voltage overcurrent compensation circuit is connected to the same-name end of the primary winding of the current transformer.
Further, the high-low voltage overcurrent compensation circuit comprises a third resistor and a second diode, wherein a first end of the third resistor is connected with the output end of the N-th primary winding input circuit, an anode of the second diode is connected with the output end of the N-th primary winding input circuit, a cathode of the second diode is connected to a current sampling port, and a second end of the third resistor is respectively connected to a homonymous end of a primary winding of the current transformer and a reference ground.
Further, the switching tube is an NMOS tube, the grid electrode of the switching tube is connected with a synchronous driving signal, the drain electrode of the switching tube is connected with the second end of the primary winding, and the source electrode of the switching tube is connected with the second end of the voltage equalizing unit.
Further, the switching tube is a PMOS tube, the grid electrode of the switching tube is connected with a synchronous driving signal, the source electrode of the switching tube is connected with the second end of the primary winding, and the drain electrode of the switching tube is connected with the second end of the voltage equalizing unit.
Further, the switching tube is an NPN triode, the base electrode of the switching tube is connected with a synchronous driving signal, the collector electrode of the switching tube is connected with the second end of the primary winding, and the emitter electrode of the switching tube is connected with the second end of the voltage equalizing unit.
Further, the switching tube is a PNP triode, the base electrode of the switching tube is connected with a synchronous driving signal, the emitting electrode of the switching tube is connected with the second end of the primary winding, and the collecting electrode of the switching tube is connected with the second end of the voltage equalizing unit.
Compared with the prior art, the current sampling circuit has the following beneficial effects:
according to the utility model, the current in the primary switch unit is sampled through the current transformer and the current acquisition unit, when the current is abnormal due to inconsistent time sequence of the switch tube or uneven capacitance, the current waveform can be acquired through the current acquisition unit of the current transformer, so that the problem that the control IC current is sampled incorrectly and the peak current of the primary winding is overlarge to cause damage to the switch tube due to the fact that the switch is asynchronous or uneven capacitance is generated is effectively avoided, and the working range of the primary winding power device is ensured to be within a reliable range, and the reliability of products is greatly improved.
Drawings
The utility model will now be described in further detail with reference to the drawings and to specific examples.
FIG. 1 is a schematic circuit diagram of a prior art high voltage tolerant, overlapping flyback DC-DC converter;
FIG. 2 is a current loop diagram of a high voltage resistant overlapping flyback DC-DC converter in the prior art when switching tubes are not consistent and capacitors are not uniform;
FIG. 3 is a circuit diagram of a first embodiment of a current sampling circuit according to the present utility model;
FIG. 4 is a circuit diagram of a second embodiment of a current sampling circuit according to the present utility model;
FIG. 5 is a circuit diagram of a third embodiment of a current sampling circuit according to the present utility model;
fig. 6 is a circuit diagram of a fourth embodiment of a current sampling circuit according to the present utility model.
Detailed Description
In order that the utility model may be more readily understood, a more particular description thereof will be rendered by reference to specific embodiments that are illustrated in the appended drawings. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the scope of the utility model.
The utility model provides a current sampling circuit, which comprises a secondary winding output circuit 20 and N primary winding input circuits 10, wherein the N primary winding input circuits 10 are sequentially connected in series, and N is an integer greater than or equal to 2;
each primary winding input circuit 10 comprises a voltage equalizing unit 101 and a primary switch unit 102, wherein the voltage equalizing unit 101 and the primary switch units 102 are connected in parallel, and each primary switch unit 102 is connected with a synchronous driving signal;
the current sampling circuit further comprises a current transformer T2 and a current acquisition unit 30, the input end of the 1 st primary winding input circuit 10 is connected to the positive voltage end of the direct current voltage, the output end of the N th primary winding input circuit 10 is respectively connected to the homonymous end of the primary winding of the current transformer T2 and the reference ground, the heteronymous end of the primary winding of the current transformer T2 is connected with the negative voltage end of the direct current voltage, an energy storage capacitor C is connected between the positive voltage end and the negative voltage end, the output end of the current transformer T2 is connected to the input end of the current acquisition unit 30, and the output end of the current acquisition unit 30 is connected to the current sampling port CS.
First embodiment
Referring to fig. 3, a schematic diagram of a current sampling circuit according to a first embodiment of the present utility model is shown, where the current sampling circuit includes a primary winding input circuit 10 and a secondary winding output circuit 20, the primary winding input circuit 10 includes a voltage equalizing unit 101 and a primary switching unit 102, the primary switching unit 102 is composed of a primary winding and a switching tube, the current sampling unit 30 is connected in series with a current output end in a loop of a final stage primary switching unit 102, the primary switching unit 102 of each stage is connected in parallel with the voltage equalizing unit 101, and the primary switching units 102 are connected in series with each other; the input end of the first-stage primary switch unit 102 is connected with the positive voltage end of the direct-current voltage, and the output end of the final-stage primary switch unit 102 is connected with the negative voltage end of the direct-current voltage after being connected with the current sampling unit. In this embodiment, the voltage equalizing unit 101 of the first stage is a capacitor C1, and the voltage equalizing unit 101 of the second stage is a capacitor C2.
The first-stage primary switch unit 102 comprises a primary winding N1 and a switch tube Q1, the switch tube Q1 is an NMOS tube, one end of the primary winding N1 is used as an input end of the first-stage primary switch unit 102 to be connected with a positive voltage end of direct-current voltage, the other end of the primary winding N1 is connected with a drain electrode of the switch tube Q1, a source electrode of the switch tube Q1 is used as an output end of the first-stage primary switch unit 102, one end of a capacitor C1 is connected with the input end of the first-stage primary switch unit 102, and the other end of the capacitor C1 is connected with the output end of the first-stage primary switch unit 102.
The second-stage primary switching unit 102 includes a primary winding N2 and a switching tube Q2, and the current transformer current collecting unit 30 includes a current transformer T2, a first resistor R1, a first diode D1, and a second resistor R2. The switching tube Q2 is an NMOS tube, one end of the primary winding N2 is used as an input end of the second-stage primary switching unit 102, the other end of the primary winding N2 is connected with a drain electrode of the switching tube Q2, a source electrode of the switching tube Q2 is used as an output end of the second-stage primary winding unit and is connected with a primary winding homonymous end of the current transformer T2, and a primary winding heteronymous end of the current transformer T2 is connected with a negative voltage end of the direct-current voltage. The same-name end of the secondary winding of the current transformer T2 is connected with the first end of the first resistor R1 and the anode of the first diode D1, the complex-edge different-name end of the current transformer T2 is connected with the second ends of the first resistor R1 and the second resistor R2 and the reference ground, and the cathode of the first diode D1 and the first end of the second resistor R2 are connected together and then used as a current sampling point to be connected to a current sampling port CS of the control IC. The output end of the first-stage primary switch unit 102 is connected with the input end of the second-stage primary switch unit 102, and the voltage-equalizing capacitor C1 and the capacitor energy stored by the capacitor C1 provide buffer time for the corresponding switch loop, so that the voltage balance among the primary winding N1 and the switch tube Q1, the primary winding N2 and the switch tube Q2 is ensured.
The circuit of this embodiment works as follows:
as shown in fig. 3, when the switching transistors in the primary switch units 102 are turned on consistently, sampling is performed through the current transformer T2, coupling is performed through the current transformer T2, the same-name end of the secondary winding of the current transformer T2 is coupled to the voltage with the same voltage as that of the primary winding, and the first diode D1 is turned on to transmit a current signal to the control IC, so that the current of the primary winding is sampled normally. When the driving timings of the switching transistors are inconsistent, in order to avoid negative current generated in fig. 2 from affecting the control IC current sampling, the IC continuously drives the switching transistors, which causes the switching transistors not to be turned off, and finally causes excessive primary winding current to damage the switching transistors. The circuit disclosed by the utility model is sampled by the current transformer T2, and negative current generated by inconsistent driving forms a loop in a network formed by the primary winding N2, the capacitor C3 and the switching tube Q2, so that the negative current cannot flow through the current transformer, namely the negative current cannot be sampled by the control IC, thereby avoiding the problem that the switching tube is finally damaged due to continuous driving of the switching tube by the IC caused by the negative current, and greatly improving the reliability of the circuit.
Second embodiment
Fig. 4 is a schematic diagram of a current sampling circuit according to a second embodiment of the present utility model, which is different from fig. 3 in that the present embodiment includes: the primary switching unit 102 and the voltage equalizing unit 101 of the power converter with the same N (N > 2) stage are overlapped in series, and the current sampling unit connected with the primary switching unit 102 of the last stage Nth stage is the same as that in the first embodiment. The working principle of the circuit after the cascade superposition of the multistage circuits is the same as that of the first embodiment, and the same effect can be realized.
Third embodiment
Fig. 5 is a schematic diagram of a current sampling circuit according to a third embodiment of the present utility model, and this embodiment is a modification of the first embodiment, and is used to improve the consistency of the high-low voltage current passing points. The current transformer comprises a primary winding input circuit 10, a secondary winding output circuit 20, a current transformer T2, a current acquisition unit 30 and a high-low voltage overcurrent point compensation circuit 40. The primary winding input circuit 10 comprises a voltage equalizing unit 101 and a primary switching unit 102, wherein the primary switching unit 102 consists of a primary winding and a switching tube, a current sampling unit is connected in series with a current output end in a loop of a final primary switching unit 102, the primary switching unit 102 of each stage is connected with the voltage equalizing unit 101 in parallel, and the primary switching units 102 are connected in series; the input end of the first-stage primary switch unit 102 is connected with the positive voltage end of the direct-current voltage, and the output end of the final-stage primary switch unit 102 is connected with the negative voltage end of the direct-current voltage after being connected with the current sampling unit. In this embodiment, the voltage equalizing unit 101 of the first stage is a capacitor C1, and the voltage equalizing unit 101 of the second stage is a capacitor C2.
The first-stage primary switch unit 102 comprises a primary winding N1 and a switch tube Q1, the switch tube Q1 is an NMOS tube, one end of the primary winding N1 is used as an input end of the first-stage primary switch unit 102 to be connected with a positive voltage end of direct-current voltage, the other end of the primary winding N1 is connected with a drain electrode of the switch tube Q1, a source electrode of the switch tube Q1 is used as an output end of the first-stage primary switch unit 102, one end of a capacitor C1 is connected with the input end of the first-stage primary switch unit 102, and the other end of the capacitor C1 is connected with the output end of the first-stage primary switch unit 102.
The second stage primary switching unit 102 includes a primary winding N2 and a switching tube Q2, and the high-low voltage overcurrent point compensation circuit 40 includes a compensation sampling resistor third resistor R3 and a diode D2. The current collecting unit 30 includes a first resistor R1, a first diode D1, and a second resistor R2. The switching tube Q2 is an NMOS tube, one end of the primary winding N2 is used as an input end of the second-stage primary switching unit 102, the other end of the primary winding N2 is connected to a drain electrode of the switching tube Q2, a source electrode of the switching tube Q2 is used as an output end of the second-stage primary winding unit to be connected to an input end of the third resistor R3 and an anode of the diode D2 of the high-low voltage overcurrent compensation circuit 40, a second end of the third resistor R3 is connected to a homonymous end of the primary winding of the current transformer T2, and a heteronymous end of the primary winding of the current transformer T2 is connected to a negative voltage end of the direct current voltage. The same-name end of the secondary winding of the current transformer T2 is connected with the first end of the first resistor R1 and the anode of the first diode D1, the different-name end of the secondary winding of the current transformer T2 is connected with the first resistor R1, the second end of the second resistor R2 and the reference ground, and the cathode of the first diode D1 is connected with the first end of the second resistor R2 and the cathode of the second diode D2 of the high-low voltage compensation circuit 40 to serve as a current sampling point for being connected to a current sampling port CS of the control IC. The output end of the first-stage primary switch unit 102 is connected with the input end of the second-stage primary switch unit 102, and the voltage-equalizing capacitor C1 and the capacitor energy stored by the capacitor C2 provide buffer time for the corresponding switch loop, so that the voltage balance among the primary winding N1 and the switch tube Q1, the primary winding N2 and the switch tube Q2 is ensured.
The circuit of this embodiment works as follows:
as shown in fig. 5, when the switching transistors in the primary switch units 102 are turned on consistently, sampling is performed through the current transformer T2, coupling is performed through the current transformer T2, the same-name end of the secondary winding of the current transformer T2 is coupled to the voltage with the same voltage as that of the primary winding, and the first diode D1 is turned on to transmit a current signal to the control IC, so that the current of the primary winding is sampled normally. When the driving timings of the switching transistors are inconsistent, in order to avoid negative current generated in fig. 2 from affecting the control IC current sampling, the IC continuously drives the switching transistors, which causes the switching transistors not to be turned off, and finally causes excessive primary winding current to damage the switching transistors. According to the circuit, the third resistor R3 for high-low voltage compensation is introduced, when a driving signal is inconsistent to generate negative current, the negative current forms a loop among the primary winding N2, the second capacitor C2, the third resistor R3 and the switching tube Q2, negative pressure is generated at two ends of the voltage of the third resistor R3, the second diode D2 is cut off, the control IC cannot collect the negative voltage, the problem that the switching tube is finally damaged due to the fact that the switching tube is continuously driven by the IC due to the negative current is avoided, meanwhile, the third resistor R3 for high-low voltage compensation is introduced, the high-low voltage passing points of products are kept consistent, and the reliability of the circuit is greatly improved.
Fourth embodiment
Fig. 6 is a schematic diagram of a current sampling circuit according to a fourth embodiment of the present utility model, which is different from fig. 5 in that the present embodiment includes: the primary switch unit 102 and the voltage equalizing unit 101 of the power converter with the same N (N > 2) stage are stacked in series, and the current sampling unit connected to the primary switch unit 102 is the same as that in the third embodiment. The working principle of the circuit after the cascade superposition of the multistage circuits is the same as that of the third embodiment, and the same effect can be realized.
It will be appreciated by those skilled in the art that although the present utility model has been described with reference to several exemplary embodiments, it should be understood that the sampling circuit of the present utility model may be applied to, but is not limited to, multi-winding series flyback converters, and may also be applied to multi-winding series converters of various types, such as multi-winding series forward converters, multi-winding series BUCK-BOOST converters, and the like.
In light of the foregoing, and by using common technical knowledge and conventional means in the art, the implementation circuit of the present utility model may be modified, replaced or altered in various other ways without departing from the basic technical concept of the present utility model, and all the modifications and alterations fall within the scope of the claims of the present utility model.
Claims (10)
1. The current sampling circuit is characterized by comprising a secondary winding output circuit and N primary winding input circuits, wherein the N primary winding input circuits are sequentially connected in series, and N is an integer greater than or equal to 2;
each primary winding input circuit comprises a voltage equalizing unit and a primary switch unit, the voltage equalizing unit and the primary switch units are connected in parallel, and each primary switch unit is connected with a synchronous driving signal;
the current sampling circuit further comprises a current transformer and a current acquisition unit, the input end of the 1 st primary winding input circuit is connected to the positive voltage end of the direct current voltage, the output end of the N th primary winding input circuit is respectively connected to the homonymous end of the primary winding of the current transformer and the reference ground, the heteronymous end of the primary winding of the current transformer is connected with the negative voltage end of the direct current voltage, an energy storage capacitor is connected between the positive voltage end and the negative voltage end, the output end of the current transformer is connected to the input end of the current acquisition unit, and the output end of the current acquisition unit is connected to the current sampling port.
2. A current sampling circuit according to claim 1, wherein: the voltage equalizing unit comprises a capacitor, and the capacitor is connected with the primary switch unit in parallel.
3. A current sampling circuit according to claim 1, wherein: the primary switch unit comprises a primary winding and a switch tube, wherein the first end of the primary winding is connected with the first end of the voltage equalizing unit, the first end of the switch tube is connected with a synchronous driving signal, the second end of the switch tube is connected with the second end of the primary winding, and the third end of the switch tube is connected with the second end of the voltage equalizing unit.
4. A current sampling circuit according to claim 1, wherein: the current acquisition unit comprises a first resistor, a first diode and a second resistor, the homonymous end of the secondary winding of the current transformer is connected to the anode of the first diode, the anode of the first diode is connected to the reference ground through the first resistor, the cathode of the first diode is connected to the reference ground through the second resistor, the homonymous end of the secondary winding of the current transformer is connected to the reference ground, and the cathode of the first diode is connected to the current sampling port.
5. A current sampling circuit according to claim 1, wherein: the high-low voltage overcurrent compensation circuit is connected between the output end of the N-th primary winding input circuit and the same-name end of the primary winding of the current transformer, the input end of the high-low voltage overcurrent compensation circuit is connected to the output end of the N-th primary winding input circuit, the first output end of the high-low voltage overcurrent compensation circuit is connected to the current sampling port, and the second output end of the high-low voltage overcurrent compensation circuit is connected to the same-name end of the primary winding of the current transformer.
6. The current sampling circuit of claim 5 wherein: the high-low voltage overcurrent compensation circuit comprises a third resistor and a second diode, wherein a first end of the third resistor is connected with the output end of the N-th primary winding input circuit, an anode of the second diode is connected with the output end of the N-th primary winding input circuit, a cathode of the second diode is connected to a current sampling port, and a second end of the third resistor is respectively connected to a homonymous end of a primary winding of the current transformer and a reference ground.
7. A current sampling circuit according to claim 3, wherein: the switching tube is an NMOS tube, the grid electrode of the switching tube is connected with a synchronous driving signal, the drain electrode of the switching tube is connected with the second end of the primary winding, and the source electrode of the switching tube is connected with the second end of the voltage equalizing unit.
8. A current sampling circuit according to claim 3, wherein: the switching tube is a PMOS tube, the grid electrode of the switching tube is connected with a synchronous driving signal, the source electrode of the switching tube is connected with the second end of the primary winding, and the drain electrode of the switching tube is connected with the second end of the voltage equalizing unit.
9. A current sampling circuit according to claim 3, wherein: the switching tube is an NPN triode, the base electrode of the switching tube is connected with a synchronous driving signal, the collector electrode of the switching tube is connected with the second end of the primary winding, and the emitter electrode of the switching tube is connected with the second end of the voltage equalizing unit.
10. A current sampling circuit according to claim 3, wherein: the switching tube is a PNP triode, the base electrode of the switching tube is connected with a synchronous driving signal, the emitting electrode of the switching tube is connected with the second end of the primary winding, and the collecting electrode of the switching tube is connected with the second end of the voltage equalizing unit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202322043291.XU CN220603577U (en) | 2023-07-31 | 2023-07-31 | Current sampling circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202322043291.XU CN220603577U (en) | 2023-07-31 | 2023-07-31 | Current sampling circuit |
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| Publication Number | Publication Date |
|---|---|
| CN220603577U true CN220603577U (en) | 2024-03-15 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN202322043291.XU Active CN220603577U (en) | 2023-07-31 | 2023-07-31 | Current sampling circuit |
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| CN (1) | CN220603577U (en) |
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2023
- 2023-07-31 CN CN202322043291.XU patent/CN220603577U/en active Active
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