CN2205574Y - Multifunction computer programming testing instrument - Google Patents

Abstract

The utility model relates to a multifunctional intelligent programming testing instrument, which can complete the test of an integrated circuit and EPROM copy independently, and the utility model can be matched with a PC to complete EPROM and GAl programming and GAL analysis. The utility model is composed of a power supply, a keyboard, a display, an RS-232 communicating part, a driving head for input and output, etc., wherein, the power supply and the keyboard are controlled by a CPU and are connected with the CPU; under the control of the CPU, the driving head which is connected with a testing fixture adds a working power supply, grounding, high-resistance grounding, high/low driving, backward read, programming voltage, elevating edge triggering, etc. to the corresponding base pin of a measured chip; the driving head which is composed of a series of switching devices is turned on or turned off under the control of the CPU, outputting various logic level required by tests.

Description

Multifunction computer programming testing instrument

The utility model relates to a kind of proving installation, relates to a kind of integrated circuit tester or rather.

Universal integrated circuit (74/54 series, 4000 series, 4500 series), EPROM memory, it is in the DLC (digital logic circuit) and other logical circuits of core that general gate-array circuit GAL etc. has been widely used in the microprocessor, for making things convenient for exploitation and maintenance personal to use, test these circuit, various integrated circuit testers also arise at the historic moment.Resolve instrument etc. as " general-purpose programmable device ", " copy card ", GAL/PAL.Strong, the special function of these instrument is more perfect, but function singleness is difficult to satisfy the various demands of user in exploitation and maintenance process, satisfies needs in the work and have to buy plurality of devices, not only increased spending, and be not easy to use and manage.

The purpose of this utility model is a kind of multifunctional intellectual programming and testing instrument of design, has the advantages that to integrate integrated circuit testing, EPROM programming and copy, GAL programming, GAL parsing, can overcome the defective of existing testing apparatus function singleness.

Multifunctional intellectual programming and testing instrument of the present utility model, with the state that works alone of PC off line under, can finish the copy work of the logic function test of 74,40,45 serial most of chips in the integrated circuit (IC) commonly used and EPROM-2716, the last erasable read-only memory of EPROM-27512; With the online condition of PC under finish the programming of above-mentioned EPROM and GAL16V8, GAL20V8 programmable logic device (PLD) and the GAL device of having encrypted made logical analysis.

Multifunctional intellectual programming and testing instrument of the present utility model, form with the power supply unit, keyboard and the display unit that are connected with the CPU control assembly, RS-232 communication interface, I/O driving head by the CPU control assembly, test fixture is connected with driving head, test fixture comprises the A anchor clamps that are used for IC test and EPROM and copy sub-sheet, be used for the B anchor clamps of EPROM copy master slice and be used for the C anchor clamps of GAL logical analysis, wherein the CPU control assembly is the control core of tester, and the operation of miscellaneous part all is to finish under its monitoring control.Power supply unit will provide working power to whole tester, adjustable working power and programming power supply will be provided to the chip under test on the IC test fixture.Keyboard and display unit are interactive interfaces, and the user is by keyboard input of control commands and data, and tester is by display tube display routine operation process and operation result.The RS-232 communication interface is used for the communication with PC, finishes the data transmission between tester and PC.The I/O driving head is used for chip under test is directly operated, and is the design key of whole tester.

The technology that is adopted in above-mentioned each parts is the technology that particularly adopts usually in the IC technical field of measurement and test in this technical field substantially, but wherein finish by driving head that CPU applies drive signal to chip on the test fixture and to the retaking of a year or grade of chip under test output signal, be tester design core also be the key of design success or not.Because this tester function chip range various, that covered is extensive, the input-output characteristic difference of chip is very big, therefore the difficulty of design is that driving head will merge and satisfy the drive characteristic of different condition, comprises chip under test is added the work power supply, chip under test is added ground, chip under test is added the output of high and low excitation, retaking of a year or grade chip under test and chip under test is added program voltage.Again owing to comprised the content that applies program voltage, thereby require the above voltage of driving head ability 25V.

The design feature of the utility model I/O driving head is: on described A, each pin of B anchor clamps and be connected to input stimulus parts, output retaking of a year or grade parts, pull-up resistor R1, pull-up resistor R2, electronic switch 3, electronic switch 4, resistance R 3, electronic switch 6 and resistance R 4; Pull-up resistor R1 other end serial connection electronic switch 1 back with on draw power vd to be connected, pull-up resistor R2 other end serial connection electronic switch 2 backs with on draw power vd to be connected, electronic switch 3 another termination working power VDD, electronic switch 4 another termination programming power supply VPP, resistance R 3 other ends serial connection electronic switch 5 backs are connected with ground, electronic switch 6 other end ground connection, resistance R 4 other ends also connect C anchor clamps one pin and input-output characteristic judgement part; Described electronic switch 1 connects the output terminal of described CPU control assembly decoding scheme respectively to the control end of electronic switch 6, the data bus that is connected the CPU control assembly of described input stimulus parts, output retaking of a year or grade parts and input-output characteristic judgement part, the read-write control end of described input stimulus parts, output retaking of a year or grade parts and input-output characteristic judgement part is connected with CPU control assembly decoding scheme output terminal respectively.

Described electronic switch 1 to electronic switch 4 is high pressure resistant device TWH8778, and electronic switch 5 and electronic switch 6 are cmos switch IRFD020.

Described input stimulus parts constitute the data latching termination CPU control assembly decoding scheme output terminal of data latches by data latches serial connection OE open circuit door 74LS07.

Described output retaking of a year or grade parts and input-output characteristic judgement part are connected in series high pressure resistant device CMOS4050 by data latches respectively and constitute, data latches gating termination CPU control assembly decoding scheme output terminal.

Described R1 is 10K, and R2 is 200 Ω, and R3 is 15K, and R4 is 470 Ω.

Describe technology of the present utility model in detail below in conjunction with embodiment and accompanying drawing.

Fig. 1 tester software pie graph

Fig. 2 tester hardware structure diagram

Fig. 3 CPU control assembly basic circuit diagram

Fig. 4 input, output drive head basic circuit diagram

Fig. 5 input, output drive head are implemented circuit diagram

Referring to Fig. 1, system software comprises system's master routine 100, each function subprogram 101 and basic I/O driven element program 102.System's master routine is the commander in chief, finishes System self-test, initialization and receives the user function order and call each function subprogram, finishes user's function needs.Function subprogram comprises integrated circuit testing subroutine, EPROM copy subroutine, EPROM programming subroutine, GAL programming subroutine and GAL decryption subprogram.Calling of each function subprogram receiving system master routine called after obtaining required parameter and is positioned at the 3rd layer various driven element programs, finishes every feature operation.And basic I/O driver comprises keyboard interrupt service subprogram, display driver subroutine, writes subroutine, reads subroutine, adds the power supply subroutine, adds ground subroutine and communicating interrupt service subprogram.They are the programs that directly drive hardware, and each program is finished a kind of simple function.These programs mainly are subjected to calling of each function subprogram 101, but master routine 100 also calls keyboard interrupt service subroutine and display driver subroutine.

Referring to Fig. 2, tester hardware comprises that CPU control assembly 200, power supply unit 201, keyboard and display unit 202, RS-232 communication interface 203 and input and output driving head 204,205 are test fixture.

5 groups of direct currents of power supply unit 201 outputs, be respectively be used for tester work+5V ,+15V ,-the 15V power supply, be used for test chip working power VDD, on draw power vd+5V ,+12V ,+15V and adjustable, the programming power supply VPP 0-25V linearity that is used for test chip is adjustable.VD and VPP realize that by resistance pressure regulation net of CPU control and a linear voltage regulation circuit D/A converter in the power supply unit provides the chip select signal by the decoding scheme of CPU parts respectively during enforcement.

Keyboard and display unit 202 are used for man-machine conversation, comprise that function key, the numerical key by keyboard finished intervention and the data input of people to using system state, and finish application system by eight hop count sign indicating number display tubes and report running status and operation result to the people.Select for use monolithic 8279 as the interface device between keyboard, demonstration and CPU among the embodiment, a monolithic just can be finished keyboard input and two kinds of functions of LED demonstration control.The scan mode that keyboard portion provides can link to each other with the array with 64 button sensors, can remove shake automatically and to the protection in keystroke when operation while.The display part can show 8 or 16 LED displaying blocks by scan mode work.

RS-232 communication interface 203 because this tester CPU control assembly adopts the CPU with full duplex asynchronous communication serial port, has been simplified the design of communication system, and the simplest RS-232C data communication is adopted in the communication between CPU and PC.Take into account processing speed and the systemic-function requirement of CPU in the enforcement, simultaneously also adopt the serial communication mode for the convenience of the user, can adopt integrated VA1488 and VA1489 to finish between the two level conversion.

I/O driving head 204 is finished the repertoire operation of tester, is made up of a series of switching devices, opens or closes under the control of CPU control assembly, provides test needed various conditions (logic level), thereby finishes every test function.

This tester have independent operating and with the ability of PC communication, can make whole 40 pins of test fixture have driving, power of test and two-way literacy, arbitrary pin all can connect easily working power VDD, programming power supply VPP, on draw power vd and ground connection etc.

Referring to Fig. 3, tester adopts MSC-51 series 8031 single-chip microcomputer U1, fast operation, and the serial port with full duplex can transmit and receive data simultaneously, and its inherent boolean processor can carry out computing to Boolean variable (one).

U2 provides data bus to drive, and DIR is the control signal of decision U2 conducting direction, by the FO end acquisition of code translator U9 among the figure.

U3, U4 provide the address to drive, and wherein U3 is the least-significant byte that utilizes address latch signal ALE latch address from the PO mouth of U1, and U4 directly drives the most-significant byte of address.

U5 is a memory under program of depositing whole executive routines, and U6 is the external data memory, selects for use 6264 of 8K capacity to provide data necessary working area and transmission, send buffer for tester.

U7-U10 is four code translators that are made of the GAL device, for guarantee that the complete machine co-ordination provides necessary control, latchs, gating and chip selection signal.Code translator is input as address signal and necessary control signal WR, PSEN, RD, decoding output signal comprises the direction control signal DIR of U2, send the gating signal EN1-ENT(U7-U10 of " reading " pin level state to driving head retaking of a year or grade parts and input-output characteristic judgement part), send the LE1-LE5(U9 of " writing " latch signal to driving head input stimulus parts), the chip selection signal CS1 that provides to U6, show the chip selection signal CS3 that control and power supply unit D/A transducer (not shown) provide to keyboard, CS4(U8) and be used to produce the CS5-CS11(U7 of electronic switch 1 to 6 control signal, U8).

Referring to Fig. 4, the function of driving head comprises to excitation, the retaking of a year or grade output state (high and low) that the chip under test pin adds work power vd D, ground connection, increases, low level excitation VD, rising edge negative edge trigger, add program voltage VPP, high resistance ground is provided and only be used for GAL resolves the C anchor clamps, the chip under test pin is made the I/O characteristic judges (judging that promptly particular end is input end or output terminal).

The parts and the syndeton of the A of anchor clamps shown in the figure, B, the arbitrary pin of C.401 is that the input stimulus parts are OE open circuit and high voltage bearing U16(74LS07 by data latches U1 connection export structure) constitute, finish the input driving.402 for output retaking of a year or grade parts, connects high voltage bearing cmos device U17(4050 by data latches U2) constitute, finish the output retaking of a year or grade.403 is the input-output characteristic judgement part, connects high voltage bearing cmos device U18(4050 by data latches U13) constitute, finish output retaking of a year or grade (74LS07 can the high pressure of anti-30V when off-state, and CMOS4050 also is high pressure resistant device).

401-403 and pull-up resistor R1, R2 constitute the two-way I/O port of standard, and the effect of resistance R 2 is driving forces of raising driving head, are used for when the sequential logic chip of test rising edge triggering and the reliable triggering of connecting resistance assurance.R3 is used to control GAL programming chips pin and whether needs the ground connection by R3, and R4 is used for accurately differentiating at the GAL logical analysis I/O character of chip.

S1-S6 is an electronic switch, when its control end CTO-CT6 is " 1 ", and switch opens, switch cuts out during for " 0 ".And when system's initial state, electronic switch is a Close All, thereby the chip under test pin is a high-impedance state.S1-S4 is a power switch, and adopting TWH8778, S5, S6 during enforcement is the ground switch, adopts VMOS switching tube IRFD020 during enforcement, and when flowing through the 500mA electric current, their pressure drop is respectively 0.3V and 0.09V.

State by control CT1-CT6 comes closing of gauge tap S1-S6 respectively or disconnected, finishes operations such as input stimulus, output retaking of a year or grade respectively by control LE1-LE5, EN1-EN7.

As, add work power vd D for the chip under test pin, then CT3 is " 1 "; To chip under test pin ground connection, then CT6 is " 1 "; When the chip under test pin was added the high level excitation, CT1 controlled U16(74LS07 simultaneously for " 1 ") end; When the chip under test pin was added the low level excitation, CT1 controlled the U16 conducting simultaneously for " 1 "; When the chip under test pin was provided rising, negative edge, CT1 controlled the U16 conducting simultaneously for " 1 ", and making CT2 again is that " 1 " allows U16 end simultaneously, and making CT2 again is that " 0 " controls the U16 conducting simultaneously; During to the retaking of a year or grade of chip under test pin, a trigger pip of U12 (EN1-EN5) is given in control, and the pin data readback is to data bus; When the chip under test pin was added programming power supply VPP, then CT4 was " 1 ", and during to the chip under test high resistance ground, then CT5 is " 1 "; When the chip under test pin in the anchor clamps is done the input-output characteristic differentiation (Transistor-Transistor Logic level), its test process is: earlier respective pin is added power supply and ground connection, make it in running order, add the high-low level excitation for pin PIN ' by U16, the level signal of this PIN ' of a trigger pip retaking of a year or grade of U13 is given in control again, then be judged to input end (or high-impedance state) if the high-low level of retaking of a year or grade conforms to input stimulus, otherwise then be judged to output terminal.

Referring to Fig. 5, U11, U16 constitute the input stimulus parts, and U12, U17 constitute output retaking of a year or grade parts, and U13, U18 constitute the input-output characteristic judgement part, the control signal CT1-CT6 of U14, U15 output electronic switch S1-S6.

LE1(-LE5) for controlling the latch signal that U16 provides the U11 of excitation, EN1(-EN7) be the gating signal of retaking of a year or grade P1N or P1N ' level state U12, U13, CS5, CS6 are the U14, the latch signal of U15 of control electronic switch, and CPU reaches control to various electronic switches and other unit by control U11-U15.

Be used to export U11, U14, the U15 of control, all have a mouth state separately to deposit in the internal memory of CPU control module, end as the 74LS07 that will make among the figure end that links to each other with PIN, the CPU control module is first gets the present condition of U11 by data bus, if 10110011; This state and 11111110 is made AND-operation, get 10110010, this state is deposited in send output order in the status register simultaneously again; CPU send address bus with the port address of U11, send data bus with 10110010 in the register, makes WR signal effectively (LE1) at last, and this moment, bus data was latched at the U11 output terminal, and the U16 pin two is " 0 ".The control procedure of U14, U15 is identical with U11, is the object difference that port address is different and control, and wherein U14 controls power supply switch tube TWH8778, U15 control grounding switch pipe D020.

The CPU control module to the control procedure of U13, U14 is: when CPU will read the level of PIN end, at first send port address to address bus, send then that to read RD effective, read data bus when RD is effective.As, because EN1 is the effective gating of output of U12, so when port address was all effective with RD, U12 ability was delivered to data on the data bus DB, otherwise output terminal is a high resistant.CPU 8 bit data of reading back are extracted and are obtained required that data.

The utility model is when implementing, because the chip under test power supply,, the programming power end the position certain rules is arranged, therefore needn't design the driving force of 40 pins, add the ground connection switch as needing only at the 20th, 23,24,25 ends, add the programming power switch at the 7th, 10,12,21,28,29 ends, the 17th, 18,26,27, the 30-34 end adds power switch, but not only simplified design was saved device but also can be guaranteed that the complete machine function realized.

The utility model is a kind of synthesization instrument that integrates multiple function, multiple functional easy to use, adopt the control of full-electronic switch, the program voltage self-adaptation is regulated, software resolves with the hardware testing result and matches, and new technologies such as excitation, measuring head fusion have improved the performance and the extensibility of equipment, service object's broad covered area can satisfy various class users' requirement.

Claims (5)

1, a kind of multifunctional intellectual programming and testing instrument, by CPU control assembly and the power supply unit, keyboard and the display unit that are connected with the CPU control assembly, RS-232 communication interface, I/O driving head, the test fixture that is connected with the I/O driving head is formed, and it is characterized in that:

Described test fixture comprises the A anchor clamps that are used for IC test and EPROM and copy sub-sheet, be used for the B anchor clamps of EPROM copy master slice and be used for the C anchor clamps of GAL logical analysis;

On described A, each pin of B anchor clamps and be connected to input stimulus parts, output retaking of a year or grade parts, pull-up resistor R1, pull-up resistor R2, electronic switch 3, electronic switch 4, resistance R 3, electronic switch 6 and resistance R 4; Pull-up resistor R1 other end serial connection electronic switch 1 back with on draw power vd to be connected, pull-up resistor R2 other end serial connection electronic switch 2 backs with on draw power vd to be connected electronic switch 3 another termination working power VDD, electronic switch 4 another termination programming power supply VPP, resistance R 3 other ends serial connection electronic switch 5 backs are connected with ground, electronic switch 6 other end ground connection, resistance R 4 other ends also connect C anchor clamps one pin and input-output characteristic judgement part; Described electronic switch 1 connects the output terminal of described CPU control assembly decoding scheme respectively to the control end of electronic switch 6, described input stimulus parts, output retaking of a year or grade parts are connected the data bus of CPU control assembly with the input-output characteristic judgement part, the read-write control end of described input stimulus parts, output retaking of a year or grade parts and input-output characteristic judgement part is connected with CPU control assembly decoding scheme output terminal respectively.

2, multifunctional intellectual programming and testing instrument according to claim 1 is characterized in that: described electronic switch 1 is high pressure resistant device TWH8778 to electronic switch 4, and electronic switch 5 and electronic switch 6 are cmos switch IRFD020.

3, multifunctional intellectual programming and testing instrument according to claim 1 is characterized in that: described input stimulus parts constitute the data latching termination CPU control assembly decoding scheme output terminal of data latches by data latches serial connection OE open circuit door 74LS07.

4, multifunctional intellectual programming and testing instrument according to claim 1, it is characterized in that: described output retaking of a year or grade parts and input-output characteristic judgement part are connected in series high pressure resistant device CMOS4050 by data latches respectively and constitute, data latches gating termination CPU control assembly decoding scheme output terminal.

5, multifunctional intellectual programming and testing instrument according to claim 1, it is characterized in that: described R1 is 10K, and R2 is 200 Ω, and R3 is 15K, and R4 is 470 Ω.

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