CN220543910U - Metal structure for reducing metal parasitic capacitance of high-speed switch channel - Google Patents
Metal structure for reducing metal parasitic capacitance of high-speed switch channel Download PDFInfo
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- CN220543910U CN220543910U CN202321902585.7U CN202321902585U CN220543910U CN 220543910 U CN220543910 U CN 220543910U CN 202321902585 U CN202321902585 U CN 202321902585U CN 220543910 U CN220543910 U CN 220543910U
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- 239000002184 metal Substances 0.000 title claims abstract description 113
- 229910052751 metal Inorganic materials 0.000 title claims abstract description 113
- 230000003071 parasitic effect Effects 0.000 title claims abstract description 29
- 238000002161 passivation Methods 0.000 claims abstract description 32
- 239000000758 substrate Substances 0.000 claims abstract description 30
- 229920000642 polymer Polymers 0.000 claims abstract description 15
- 229920002521 macromolecule Polymers 0.000 claims description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 8
- 229910052710 silicon Inorganic materials 0.000 abstract description 8
- 239000010703 silicon Substances 0.000 abstract description 8
- 238000005516 engineering process Methods 0.000 abstract description 3
- 239000010410 layer Substances 0.000 description 129
- 238000000034 method Methods 0.000 description 20
- 238000001259 photo etching Methods 0.000 description 12
- 238000000151 deposition Methods 0.000 description 7
- 239000010408 film Substances 0.000 description 6
- 238000002955 isolation Methods 0.000 description 6
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 5
- 229910052802 copper Inorganic materials 0.000 description 5
- 239000010949 copper Substances 0.000 description 5
- 238000011049 filling Methods 0.000 description 4
- 239000003989 dielectric material Substances 0.000 description 3
- 238000000227 grinding Methods 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 238000004026 adhesive bonding Methods 0.000 description 2
- 238000009713 electroplating Methods 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- 229920001721 polyimide Polymers 0.000 description 2
- 238000002360 preparation method Methods 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- 238000004528 spin coating Methods 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- 239000004642 Polyimide Substances 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 230000000750 progressive effect Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
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- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
The utility model discloses a metal structure for reducing metal parasitic capacitance of a high-speed switch channel, which comprises the following components: the MOS transistor comprises a switch MOS transistor, a substrate layer, a first passivation layer, a top metal layer and a high polymer dielectric layer; the first passivation layer and the high polymer dielectric layer are sequentially arranged on the substrate layer, the top metal layer is arranged on the first passivation layer, and the switch MOS tube is arranged on the substrate layer; the utility model is equivalent to adding a plurality of metal dielectric layers in the existing silicon technology metal by adding a layer of rewiring metal layer, thereby reducing parasitic capacitance with low cost and improving the bandwidth of the high-speed switch.
Description
Technical Field
The utility model relates to the technical field of semiconductors, in particular to a metal structure for reducing metal parasitic capacitance of a high-speed switch channel.
Background
At present, the high-speed switch integrated circuit is widely used in mobile portable equipment, such as a mobile processor interface switch, a high-speed USB3.0 switch, a USB3.1 switch and the like, and the main performance index of the integrated circuit is the bandwidth frequency of a passable effective signal, and any capacitance to ground on a high-speed signal switch channel can attenuate the high-speed signal to reduce the bandwidth of the passable signal. This requires that the parasitic capacitance to ground on the signal path be minimized.
However, in order to meet the requirements of reducing the product size, data transmission stability and integration, a high-speed signal switch channel with multiple paths is generally integrated in a high-speed switch integrated circuit, and the metal interconnection line from each channel input/output pin to the source/drain of the switch MOS tube has a considerable length in layout, but in order to meet the on-resistance requirement of the product application on the switch, the width of the metal interconnection line with a longer switch channel needs to be ensured to be quite wide, and at the moment, the metal interconnection line of the high-speed channel has quite large area to generate considerable parasitic capacitance to the substrate; in this case, the metal interconnection line connecting the input and output channels of the high-speed switch channel and the parasitic capacitance of the metal bonding pads at the two ends to the ground must be considered, the existing method for reducing the parasitic capacitance is to use the top metal layer on the interconnection line of the high-speed channel, and the effect of reducing the parasitic capacitance generated by adding one metal layer per metal layer becomes smaller and smaller along with the increase of the total dielectric thickness by increasing the thickness of the interlayer dielectric between the top metal interconnection line and the substrate ground, but a larger process cost increase is brought, because two process layers are added per metal layer, the process cost of a wafer is increased by more than 10%, and the cost of the chip is increased sharply.
Therefore, how to provide a metal structure capable of reducing the parasitic capacitance of the high-speed switch channel metal is a problem that needs to be solved by those skilled in the art.
Disclosure of Invention
In view of this, the utility model provides a metal structure for reducing the parasitic capacitance of the high-speed switch channel metal, which is a method for greatly reducing the number of metal layers in the silicon process, reducing the parasitic capacitance with low cost and improving the bandwidth of the high-speed switch by adding a layer of rewiring metal layer, which is equivalent to adding 6 layers of metal in the existing silicon process metal.
In order to achieve the above purpose, the present utility model adopts the following technical scheme:
the utility model provides a reduce metal structure of high-speed switch signal channel metal parasitic capacitance, includes a switch MOS pipe, still includes: the substrate layer, the first passivation layer, the top metal layer and the high polymer dielectric layer;
the first passivation layer and the high polymer dielectric layer are sequentially arranged on the substrate layer, the first passivation layer is arranged on the top metal layer, and the switch MOS tube is arranged on the substrate layer.
Preferably, the method further comprises: and the rerouting metal layer is arranged on the high polymer dielectric layer, so that the dielectric thickness is further increased.
Preferably, the method further comprises: and the second passivation layer is arranged on the rerouting metal layer and plays a role in protecting the rerouting metal.
Preferably, the thickness of the first passivation layer is more than or equal to 3 mu m.
Preferably, the thickness of the polymer dielectric layer is 4-10 μm.
Further, the utility model also provides a preparation process of the metal structure for reducing the metal parasitic capacitance of the high-speed switch signal channel, which comprises the following steps:
step S1: performing a standard CMOS integrated circuit front-end process, and forming P-well, N-well and active devices required by circuits on the substrate layer;
step S2: photoetching an active region contact hole on a source drain electrode of the switch MOS tube, and filling a through hole with metal;
step S3: photoetching a top layer through hole of the top layer metal layer, filling the through hole with metal, depositing the top layer metal layer to a specified thickness, photoetching a top layer metal pattern, depositing the first passivation layer, and chemically and mechanically grinding to the specified thickness;
step S4: spin-coating the macromolecule medium layer with a specified thickness, photoetching the macromolecule medium layer until the top metal layer is windowed, sputtering a copper seed layer, gluing, photoetching and developing a rewiring layer, electroplating the rewiring metal layer, etching to remove the redundant copper seed layer on the substrate layer after photoresist removal, forming a second passivation layer on the rewiring layer, and photoetching a bonding pad window.
Compared with the prior art, the utility model discloses a metal structure for reducing the metal parasitic capacitance of a high-speed switch channel, which is characterized in that a thick dielectric material film layer is added on a first passivation layer after the chip process is finished, and a metal rewiring layer on the thick dielectric film layer is used as the interconnection metal of a top-layer high-speed signal channel, so that the dielectric thickness between the metal interconnection line of the high-speed signal channel and a substrate is effectively increased, and the ground parasitic capacitance of the metal interconnection of the high-speed signal channel is greatly reduced.
Drawings
In order to more clearly illustrate the embodiments of the present utility model or the technical solutions in the prior art, the drawings that are required to be used in the embodiments or the description of the prior art will be briefly described below, and it is obvious that the drawings in the following description are only embodiments of the present utility model, and that other drawings can be obtained according to the provided drawings without inventive effort for a person skilled in the art.
Fig. 1 is a schematic structural diagram of a metal structure for reducing parasitic capacitance of a high-speed switch channel according to the present utility model.
Detailed Description
The following description of the embodiments of the present utility model will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present utility model, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the utility model without making any inventive effort, are intended to be within the scope of the utility model.
Example 1
Referring to fig. 1, embodiment 1 of the present utility model discloses a metal structure for reducing metal parasitic capacitance of a high-speed switch signal channel, which comprises a switch MOS tube 1, and further comprises: the substrate layer 2, the first passivation layer 3, the top metal layer 4 and the high polymer dielectric layer 5;
the substrate layer 2 is sequentially provided with a first passivation layer 3 and a high polymer dielectric layer 5, the first passivation layer 3 is arranged on the top metal layer 4, and the switch MOS tube 1 is arranged on the substrate layer 2.
Wherein the substrate layer 2 may be a P-type substrate.
Specifically, the top metal layer 4 may have a thickness of 0.8-4 μm.
In a specific embodiment, the method further comprises: and a redistribution metal layer 6, wherein the redistribution metal layer 6 is disposed on the polymer dielectric layer 5.
In a specific embodiment, the method further comprises: and a shallow trench isolation dielectric layer 7, wherein the shallow trench isolation dielectric layer 7 is arranged on the substrate layer 2.
In a specific embodiment, the method further comprises: the metal dielectric structure 8, the metal dielectric structure 8 is set up between isolation dielectric layer 7 of shallow slot and passivation layer 3.
In a specific embodiment, the metal dielectric structure 8 comprises: the first metal dielectric layer 81 and the second metal dielectric layer 82 are sequentially arranged between the shallow trench isolation dielectric layer 7 and the passivation layer 3.
Specifically, the redistribution metal layer 6 of the signal path may be copper wiring, with a width of 8-20 μm and a thickness of 3-10 μm.
In a specific embodiment, the method further comprises: a second passivation layer 19, the second passivation layer 19 being disposed on the rerouting metal layer 6.
In a specific embodiment, the thickness of the first passivation layer 3 is ≡3 μm.
In a specific embodiment, the thickness of the first passivation layer 3 is greater than or equal to 3 μm, and the passivation layer 3 may be a single silicon oxide film or a silicon oxide film and a silicon nitride film after chemical mechanical polishing planarization.
In a specific embodiment, the thickness of the polymer dielectric layer 5 is 4-10 μm, and may be 5 μm.
In a specific embodiment, the polymer dielectric layer 5 is generally a polymer thin film dielectric material, and specifically a polyimide film with a thickness of 4-10 μm and a relative dielectric constant of 2-6 can be used.
Specifically, when the utility model is used, the parasitic capacitance between the signal channel metal interconnection line of the top layer and the substrate ground is reduced by a method of adding the rerouting metal layer 6 on the thick dielectric material after the substrate layer 2 to serve as the interconnection metal of the top layer high-speed signal channel.
The polymer dielectric layer 5 is arranged at about 4-10 μm, which is equivalent to the thickness of more than 4 metal dielectric layers, so that compared with the prior art of increasing the number of the metal dielectric layers, the parasitic capacitance to the ground can be reduced more efficiently and at lower cost. For example, in a 0.18 μm line width process, the inter-metal dielectric thickness is typically around 0.8 μm, while the polyimide under the redistribution metal (and SiO 2 Dielectric constants are similar) are generally more than 5 mu m, then the redistribution layer is used as the channel metal, and the thick dielectric layer added below the redistribution layer can greatly increase the dielectric thickness between the channel metal and the silicon substrate ground, namely greatly reduce the parasitic capacitance of the channel metal to the ground, and improve the bandwidth performance of the high-speed switch.
In addition, when the re-wiring layer is used as the high-speed signal channel, the medium under the re-wiring layer is composed of three parts, namely, the medium under the silicon top layer metal, the thickness d1, the first passivation layer medium, the thickness d2, the high-molecular thick medium film between the first passivation layer and the re-wiring metal layer, the thickness d3, the medium thickness of the parasitic capacitance between the channel metal and the silicon substrate is d1+d2+d3, the thickness of the high-molecular medium layer 5 under the re-wiring metal layer is usually more than 5 mu m due to the flattening technology adopted by the first passivation layer 3, the medium thickness from the channel metal layer to the silicon substrate is increased by more than 8 mu m after the high-speed signal channel metal layer is adopted by the re-wiring metal layer in the patent, and the medium thickness of the channel metal layer to the silicon substrate is increased by approximately 1.25 mu m in the standard technology in the prior art.
Example 2
The embodiment 2 of the utility model provides a preparation process of a metal structure for reducing metal parasitic capacitance of a high-speed switch signal channel, which comprises the following steps:
step S1: carrying out a standard CMOS integrated circuit front-pass process, depositing a shallow trench isolation dielectric layer 7 on a substrate layer 2, and forming a P well, an N well and active devices required by a circuit on the substrate layer 2;
step S2: depositing a shallow slot isolation dielectric layer 7 on a substrate layer 2, photoetching an active area contact hole on a source electrode and a drain electrode of a switch MOS tube 1, filling a through hole with metal, sequentially depositing a first metal dielectric layer 81, a first metal layer 9 and a second metal dielectric layer 82, and chemically and mechanically grinding to a specified thickness;
step S3: photoetching a top layer through hole of a top layer metal layer 4, filling the through hole with metal, depositing to a top layer metal layer with a specified thickness, photoetching a top layer metal pattern, depositing a passivation layer 3, and chemically and mechanically grinding to the specified thickness;
step S4: spin-coating a macromolecule medium layer 5 with a specified thickness, photoetching a window from the macromolecule medium layer 5 to a top metal layer 4, sputtering a copper seed layer, gluing, photoetching and developing a rewiring layer, electroplating a rewiring metal layer 6, etching to remove the redundant copper seed layer on the substrate layer 2 after photoresist removal, forming a passivation layer 19 on the rewiring layer, and photoetching a press pad window.
In the present specification, each embodiment is described in a progressive manner, and each embodiment is mainly described in a different point from other embodiments, and identical and similar parts between the embodiments are all enough to refer to each other. For the device disclosed in the embodiment, since it corresponds to the method disclosed in the embodiment, the description is relatively simple, and the relevant points refer to the description of the method section.
The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present utility model. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the utility model. Thus, the present utility model is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
Claims (5)
1. The utility model provides a reduce high-speed switch passageway metal parasitic capacitance metal structure, includes a switch MOS pipe (1), its characterized in that still includes: the device comprises a substrate layer (2), a first passivation layer (3), a top metal layer (4) and a high polymer dielectric layer (5);
the substrate layer (2) is sequentially provided with the first passivation layer (3) and the high polymer dielectric layer (5), the first passivation layer (3) is arranged on the top metal layer (4), and the switch MOS tube (1) is arranged on the substrate layer (2).
2. The high speed switch channel metal parasitic capacitance reducing metal structure of claim 1, further comprising: and a rewiring metal layer (6), wherein the rewiring metal layer (6) is arranged on the macromolecule medium layer (5).
3. The high speed switch channel metal parasitic capacitance reducing metal structure of claim 2, further comprising: -a second passivation layer (19), said second passivation layer (19) being arranged on said rewiring metal layer (6).
4. A metal structure for reducing parasitic capacitance of high speed switch channel metal according to claim 1, characterized in that the thickness of the first passivation layer (3) is not less than 3 μm.
5. The metal structure for reducing the metal parasitic capacitance of the high-speed switch channel according to claim 2, wherein the thickness of the high-molecular dielectric layer (5) is 4-10 μm.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202321902585.7U CN220543910U (en) | 2023-07-18 | 2023-07-18 | Metal structure for reducing metal parasitic capacitance of high-speed switch channel |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202321902585.7U CN220543910U (en) | 2023-07-18 | 2023-07-18 | Metal structure for reducing metal parasitic capacitance of high-speed switch channel |
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| Publication Number | Publication Date |
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| CN220543910U true CN220543910U (en) | 2024-02-27 |
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| CN202321902585.7U Active CN220543910U (en) | 2023-07-18 | 2023-07-18 | Metal structure for reducing metal parasitic capacitance of high-speed switch channel |
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| Country | Link |
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| CN (1) | CN220543910U (en) |
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- 2023-07-18 CN CN202321902585.7U patent/CN220543910U/en active Active
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