CN220401739U - Signal processing circuit and system - Google Patents

Abstract

The utility model relates to the technical field of power electronics, and provides a signal processing circuit and a system, wherein the signal processing circuit comprises a sampling module, an amplifying module and a conversion module; the sampling module is respectively connected with the device to be tested and the amplifying module, the amplifying module is connected with the conversion module, and the conversion module is used for being in communication connection with the controller. When the device to be tested is in the dynamic gate bias test, the sampling module is used for collecting leakage current of the device to be tested, converting the leakage current into a voltage signal and inputting the voltage signal to the amplifying module so that the amplifying module amplifies the voltage signal; the conversion module is used for converting the amplified voltage signal into a digital signal and sending the digital signal to the controller so that the controller stores the digital signal of the device to be tested. Based on the method, when the semiconductor device fails, a digital signal of the semiconductor device can be obtained, and an electric parameter corresponding to the semiconductor device is obtained based on the digital signal and an algorithm program, so that the reason of the failure of the semiconductor device is determined according to the electric parameter.

Description

Signal processing circuit and system

[ field of technology ]

The present utility model relates to the field of power electronics, and in particular, to a signal processing circuit and system.

[ background Art ]

The semiconductor device is a core component of modern electronic technology, has the advantages of miniaturization, high speed, low power consumption, high reliability and the like, and is required to perform performance detection before the semiconductor device is put into use so as to ensure the reliability of the semiconductor device. However, the prior art only includes testing the performance of the semiconductor device, and the preservation of the test results is not involved, but the preservation of the test results can provide electrical parameters of the semiconductor device when the semiconductor device fails, thereby realizing the determination of the cause of the failure of the semiconductor device by analyzing the electrical parameters of the semiconductor device.

Therefore, how to preserve the electrical parameters of the semiconductor device is a technical problem to be solved in the prior art.

[ utility model ]

The embodiment of the utility model provides a signal processing circuit and a system, which aim to solve the technical problem that the failure cause of a semiconductor device cannot be analyzed in the prior art.

In order to solve the technical problems, one technical scheme adopted by the embodiment of the utility model is as follows: the signal processing circuit comprises a sampling module, an amplifying module and a converting module; the sampling module is respectively connected with the device to be tested and the amplifying module, the amplifying module is connected with the conversion module, and the conversion module is also used for being in communication connection with the controller; when the device to be tested is in a dynamic gate bias test, the sampling module is used for collecting leakage current of the device to be tested, converting the leakage current into a voltage signal and inputting the voltage signal to the amplifying module so that the amplifying module amplifies the voltage signal; the conversion module is used for converting the amplified voltage signal into a digital signal and sending the digital signal to the controller so that the controller stores the digital signal of the device to be tested.

Optionally, the amplifying module includes a first amplifying unit, a second amplifying unit, a third amplifying unit, an emitter follower U1 and a sliding rheostat R1; the first input end of the first amplifying unit is connected with the sampling module, the second input end of the first amplifying unit is connected with the grounding end, the output end of the first amplifying unit is connected with the first input end of the second amplifying unit, the second input end of the second amplifying unit is connected with the output end of the emitter follower U1, the output end of the second amplifying unit is connected with the first input end of the third amplifying unit, the second input end of the third amplifying unit is connected with the grounding end, the output end of the third amplifying unit is connected with the conversion module, the first input end of the emitter follower U1 is connected with the second end of the sliding rheostat R1, the first end of the sliding rheostat R1 is connected with a first power supply, the second end of the sliding rheostat R1 is connected with a second power supply, and the second input end of the emitter follower U1 is connected with the output end of the emitter follower U1.

Optionally, the first amplifying unit includes an operational amplifier U2, a resistor R2, and a resistor R3; the same direction end of the operational amplifier U2 is connected with the sampling module, the reverse end of the operational amplifier U2 is connected with the grounding end through the resistor R2, the reverse end of the operational amplifier U2 is also connected with the output end of the operational amplifier U2 through the resistor R3, and the output end of the operational amplifier U2 is also connected with the first input end of the second amplifying unit.

Optionally, the second amplifying unit includes an operational amplifier U3, a resistor R4, and a resistor R5; the same direction end of the operational amplifier U3 is connected with the output end of the operational amplifier U2, the reverse end of the operational amplifier U3 is connected with the output end of the emitter follower U1 through the resistor R4, the reverse end of the operational amplifier U3 is also connected with the output end of the operational amplifier U3 through the resistor R5, and the output end of the operational amplifier U3 is also connected with the first input end of the third amplifying unit.

Optionally, the third amplifying unit includes an operational amplifier U4, a resistor R6 and a resistor R7; the same direction end of the operational amplifier U4 is connected with the output end of the operational amplifier U3, the reverse end of the operational amplifier U4 is connected with the grounding end through the resistor R6, the reverse end of the operational amplifier U4 is also connected with the output end of the operational amplifier U4 through the resistor R7, and the output end of the operational amplifier U4 is also connected with the conversion module.

Optionally, the sampling module includes a diode D1, a diode D2, a diode D3, a diode D4, a diode D5, a diode D6, a diode D7, a voltage regulator D8, a voltage regulator D9, a sampling resistor R8, a resistor R9, and a capacitor C5; the first end of sampling resistance R8 respectively with await measuring the device the first end of resistance R9 is connected, the second end of sampling resistance R8 is used for ground connection, the second end of resistance R9 respectively with the positive pole of steady voltage tube D8, the first end of electric capacity C5 and amplification module 32 is connected, the negative pole of steady voltage tube D8 with the negative pole of steady voltage tube D9 is connected, the positive pole of steady voltage tube D9 with the second end of electric capacity C5 all with the ground connection, diode D1, diode D2, diode D3, diode D4 and diode D5 establish ties, the positive pole of diode D1 is connected with the device that awaits measuring, the negative pole of diode D5 is connected with the ground connection, the negative pole of diode D6 with the device that awaits measuring, the positive pole of diode D6, the negative pole of diode D7 all is connected with the ground connection, the positive pole of diode D7 with the device that awaits measuring.

Optionally, the signal processing circuit further includes a processing module, where the processing module includes an inductor L1, an inductor L2, a capacitor C1, a capacitor C2, a capacitor C3, a capacitor C4, and an emitter follower U6; the first end of inductance L1 respectively with amplifying module's output the first end of electric capacity C1 is connected, inductance L1's second end respectively with electric capacity C2's first end with inductance L2's first end is connected, inductance L2's second end respectively with emitter follower U6's syntropy end the first end of electric capacity C4 is connected, electric capacity C1, electric capacity C2 and the second end of electric capacity C4 all are used for ground connection, electric capacity C3 with electric capacity C2 connects in parallel, emitter follower U6's reverse end with emitter follower U6's output is connected, emitter follower U6's output still with converting module connects.

Optionally, the conversion module is an ADC chip U5, where the ADC chip U5 includes an input pin and an output pin, and the output pins include 14 output pins; the input pin of the ADC chip U5 is connected with the output end of the amplifying module; the ADC chip U5 is used for receiving the voltage signal output by the amplifying module and converting the voltage signal so as to output a 14-bit digital signal through an output pin of the ADC chip U5.

Optionally, the signal processing circuit further includes a buffer U7; the buffer U7 comprises 14 input pins and 14 output pins, the 14 input pins of the buffer U7 are correspondingly connected with the 14 output pins of the ADC chip U5, and the 14 output pins of the buffer U7 are connected with the controller.

In order to solve the technical problems, another technical scheme adopted by the embodiment of the utility model is as follows: there is provided a signal processing system comprising: a device under test; a controller; and a signal processing circuit as described above.

The utility model provides a signal processing circuit and a system, which are different from the situation of the related art, wherein the signal processing circuit comprises a sampling module, an amplifying module and a converting module; the sampling module is respectively connected with the device to be tested and the amplifying module, the amplifying module is connected with the conversion module, and the conversion module is also used for being in communication connection with the controller; when the device to be tested is in a dynamic gate bias test, the sampling module is used for collecting leakage current of the device to be tested, converting the leakage current into a voltage signal and inputting the voltage signal to the amplifying module so that the amplifying module amplifies the voltage signal; the conversion module is used for converting the amplified voltage signal into a digital signal and sending the digital signal to the controller so that the controller stores the digital signal of the device to be tested. Based on the method, when the semiconductor device fails, a digital signal corresponding to the semiconductor device is acquired, an electric parameter corresponding to the semiconductor device is obtained based on the digital signal and an algorithm program, and the reason of the failure of the semiconductor device is determined according to the electric parameter.

[ description of the drawings ]

One or more embodiments are illustrated by way of example and not limitation in the figures of the accompanying drawings, in which like references indicate similar elements, and in which the figures of the drawings are not to scale, unless expressly stated otherwise.

Fig. 1 is a block diagram of a signal processing system according to an embodiment of the present utility model;

fig. 2 is a block diagram of a signal processing circuit according to an embodiment of the present utility model;

FIG. 3 is a circuit diagram of an amplifying module according to an embodiment of the present utility model;

FIG. 4 is a circuit diagram of an amplification module according to another embodiment of the present utility model;

FIG. 5 is a circuit diagram of a digital potentiometer according to an embodiment of the present utility model;

FIG. 6 is a circuit diagram of a sampling module provided by an embodiment of the present utility model;

FIG. 7 is a circuit diagram of a processing module according to an embodiment of the present utility model;

fig. 8 is a circuit diagram of an ADC chip according to an embodiment of the utility model;

FIG. 9 is a circuit diagram of a waveform processing module according to an embodiment of the present utility model;

fig. 10 is a circuit diagram of a buffer according to an embodiment of the present utility model.

[ detailed description ] of the utility model

The present utility model will be described in further detail with reference to the drawings and examples, in order to make the objects, technical solutions and advantages of the present utility model more apparent. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the scope of the utility model.

It should be noted that, if not in conflict, the features of the embodiments of the present utility model may be combined with each other, which are all within the protection scope of the present utility model. In addition, although the division of the functional modules is performed in the apparatus schematic, in some cases, the division of the modules may be different from that in the apparatus schematic.

Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this utility model belongs. The terminology used in the description of the utility model herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the utility model. The term "and/or" as used in this specification includes any and all combinations of one or more of the associated listed items.

In addition, the technical features mentioned in the different embodiments of the utility model described below can be combined with one another as long as they do not conflict with one another.

Referring to fig. 1, fig. 1 is a block diagram of a signal processing system according to an embodiment of the present utility model, and as shown in fig. 1, the signal processing system 100 includes a device under test 10, a controller 20, and a signal processing circuit 30; the signal processing circuit 30 is connected to the device under test 10 and the controller 20, respectively. The signal processing circuit 30 is configured to obtain test data of the device under test 10 when the device under test 10 performs a dynamic gate bias test, process the test data, and finally send the processed test data to the controller 20, so that the controller 20 stores the test data, and when the device under test 10 fails, determine a cause of the failure of the device under test 10 according to the test data. Wherein the test data includes leakage current of the device under test 10, etc. It should be noted that, before storing the test data of the device under test 10, the controller 20 may store information such as a model number of the device under test 10, so as to correspond the test data to the device under test 10. It should be noted that, the dynamic bias test refers to that when the bias test is performed on the device 10 to be tested, a high voltage is periodically applied to the device 10 to be tested, so that the device 10 to be tested is continuously switched between an on state and an off state based on the high voltage.

In some embodiments, the signal processing system 100 further includes an operating power supply 50 (not shown), the operating power supply 50 including a first power supply 51 (not shown), a second power supply 52 (not shown), a third power supply 53 (not shown), and a fourth power supply 54 (not shown), respectively. Wherein the first power source 51, the third power source 53 and the fourth power source 54 are positive voltages, and the second power source 52 is a negative voltage. Optionally, the first power supply 51 is 15V, the second power supply 52 is-15V, the third power supply 53 is 5V, and the fourth power supply 54 is 3.3V

Referring to fig. 2, fig. 2 is a block diagram of a signal processing circuit according to an embodiment of the present utility model, and as shown in fig. 2, the signal processing circuit 30 includes a sampling module 31, an amplifying module 32, and a converting module 33; the sampling module 31 is respectively connected with the device under test 10 and the amplifying module 32, the amplifying module 32 is connected with the converting module 33, and the converting module 33 is also used for being in communication connection with the controller 20.

When the device under test 10 is in a dynamic gate bias test, the sampling module 31 is configured to collect a leakage current of the device under test 10, and convert the leakage current into a voltage signal and input the voltage signal to the amplifying module 32, so that the amplifying module 32 amplifies the voltage signal;

The conversion module 33 is configured to convert the amplified voltage signal into a digital signal, and send the digital signal to the controller 20, so that the controller 20 stores the digital signal of the device under test 10.

Further, as shown in fig. 2, the amplifying module 32 includes a first amplifying unit 321, a second amplifying unit 322, a third amplifying unit 323, an emitter follower U1, and a sliding resistor R1; the first input end of the first amplifying unit 321 is connected with the sampling module 31, the second input end of the first amplifying unit 321 is connected with the ground, the output end of the first amplifying unit 321 is connected with the first input end of the second amplifying unit 322, the second input end of the second amplifying unit 322 is connected with the output end of the emitter follower U1, the output end of the second amplifying unit 322 is connected with the first input end of the third amplifying unit 323, the second input end of the third amplifying unit 323 is connected with the ground, the output end of the third amplifying unit 323 is connected with the conversion module 33, the first input end of the emitter follower U1 is connected with the second end of the sliding resistor R1, the first end of the sliding resistor R1 is connected with the first power supply 51, the second end of the sliding resistor R1 is connected with the second power supply 52, and the second input end of the emitter follower U1 is connected with the output end of the emitter follower U1.

Specifically, when the sampling module 31 outputs a voltage signal based on the collected leakage current, the voltage signal is amplified by the first amplifying unit 321, the second amplifying unit 322 and the third amplifying unit 323, and the amplified voltage signal is input to the converting module 33, so that the converting module 33 converts the amplified voltage signal into a digital signal. The voltage at the first input terminal of the emitter follower U1 is controlled by the sliding resistor R1, and the voltage at the first input terminal of the emitter follower U1 is controlled by controlling the resistance value of the sliding resistor R1, so as to control the voltage at the second input terminal of the second amplifying unit 322. It is known that the voltage of the second input terminal of the second amplifying unit 322 is changed by the emitter follower U1, so as to raise the potential of the second input terminal of the second amplifying unit 322, thereby suppressing the zero drift generated by the first amplifying unit 321 and the second amplifying unit 322. It should be noted that, when the voltage signal is input to the conversion module 33 for conversion, it is required to ensure that the voltage signal meets the requirement of the conversion module 33, and the voltage signal output by the sampling module 31 is generally in a microvolt level, if the voltage signal is directly input to the conversion module 33, the signal may not be correctly identified, so before the voltage signal is input to the conversion module 33, the voltage signal needs to be amplified, so that the frequency of the voltage signal output by the sampling module 31 is the frequency identifiable by the conversion module 33, and thus the leakage current of the device under test 10 can be correctly stored in the controller 20.

Referring to fig. 3, fig. 3 is a circuit diagram of an amplifying module according to an embodiment of the present utility model, as shown in fig. 3, the first amplifying unit 321 includes an operational amplifier U2, a resistor R2 and a resistor R3; the second amplifying unit 322 includes an operational amplifier U3, a resistor R4, and a resistor R5; the third amplifying unit 323 includes an operational amplifier U4, a resistor R6, and a resistor R7.

The same direction end of the operational amplifier U2 is connected with the sampling module 31, the opposite direction end of the operational amplifier U2 is connected with the ground end through the resistor R2, the opposite direction end of the operational amplifier U2 is also connected with the output end of the operational amplifier U2 through the resistor R3, and the output end of the operational amplifier U2 is connected with the first input end of the second amplifying unit 322.

The same direction end of the operational amplifier U3 is connected with the output end of the operational amplifier U2, the reverse end of the operational amplifier U3 is connected with the output end of the emitter follower U1 through the resistor R4, the reverse end of the operational amplifier U3 is also connected with the output end of the operational amplifier U3 through the resistor R5, and the output end of the operational amplifier U3 is also connected with the first input end of the third amplifying unit 323;

The same direction end of the operational amplifier U4 is connected with the output end of the operational amplifier U3, the reverse end of the operational amplifier U4 is connected with the ground end through the resistor R6, the reverse end of the operational amplifier U4 is further connected with the output end of the operational amplifier U4 through the resistor R7, and the output end of the operational amplifier U4 is further connected with the conversion module 33.

Specifically, the common-direction end of the operational amplifier U2 receives the voltage signal, amplifies the voltage signal, and outputs the amplified voltage signal to the common-direction end of the operational amplifier U3, and at the same time, the emitter follower U1 outputs a voltage in a preset range to the opposite-direction end of the operational amplifier U3 based on the sliding rheostat R1, so as to provide a reference voltage for the operational amplifier U3; at this time, the operational amplifier U3 continues to amplify the amplified voltage signal based on the reference voltage, and inputs the amplified voltage signal to the same directional terminal of the operational amplifier U4 for amplification. Based on this, the voltage signal output from the sampling module 31 is amplified three times and then input to the conversion module 33, so that the leakage current of the device under test 10 can be accurately identified by the conversion module 33. Wherein the voltage of the preset range is set by the first power source 51 and the second power source 52.

In some embodiments, as shown in fig. 3, the first amplifying unit 321 further includes a resistor R10, a sliding resistor R12, a resistor R13, a resistor R14, a capacitor C6, a capacitor C8, a capacitor C9, a capacitor C10, and a capacitor C13; the resistor R10 is respectively connected with the sampling module 31 and the homodromous end of the operational amplifier U2, the capacitor C6 is respectively connected with the second end and the grounding end of the resistor R10, the first pin of the operational amplifier U2 is connected with the fifth pin of the operational amplifier U2 through the sliding rheostat R12, the moving end of the sliding rheostat R12 is connected with the seventh pin of the operational amplifier U2, the fifth pin of the operational amplifier U2 is also connected with the grounding end through the capacitor C8, the first pin of the operational amplifier U2 is also grounded through the capacitor C9, the seventh pin of the operational amplifier U2 is also connected with the first power supply 51 through the resistor R13, the fourth pin of the operational amplifier U2 is connected with the second power supply 52 through the resistor R14, the first power supply 51 is connected with the grounding end through the capacitor C10, and the second power supply 52 is connected with the grounding end through the capacitor C13. It should be noted that, the resistor R10 and the capacitor C6 form an RC filter, and noise in the voltage signal output by the sampling module 31 is filtered by the RC filter, so as to reduce distortion generated during signal amplification. The capacitors C10 and C13 are mainly used to filter noise in the first power supply 51 and the second power supply 52. Further, the first amplifying unit 321 may further include a resistor R11, a capacitor C7, a capacitor C11, a capacitor C12, a capacitor C14, and a capacitor C15, where the resistor R11 and the capacitor C7 form a second stage RC filter for further filtering noise in the voltage signal output by the sampling module 31. The capacitor C11 and the capacitor C12 are connected in parallel with the capacitor C10, and the capacitor C14 and the capacitor C15 are connected in parallel with the capacitor C13. It will be appreciated that the RC filters are only used to filter noise from the input signal, so in some embodiments the number of RC filters may be set as desired for the voltage signal.

As shown in fig. 3, the second discharging unit 322 further includes a resistor R15 and a capacitor C16 that form an RC filter, and a sliding resistor R18, a resistor R17, a resistor R19, a capacitor C18, a capacitor C21, a capacitor C22, and a capacitor C23; the resistor R15 is respectively connected with the output end of the operational amplifier U2 and the same-directional end of the operational amplifier U3, the capacitor C16 is respectively connected with the second end of the resistor R15 and the ground end, the first pin of the operational amplifier U3 is connected with the fifth pin of the operational amplifier U3 through the sliding resistor R18, the moving end of the sliding resistor R18 is connected with the seventh pin of the operational amplifier U3, the fifth pin of the operational amplifier U3 is further grounded through the capacitor C21, the first pin of the operational amplifier U3 is further grounded through the capacitor C22, the seventh pin of the operational amplifier U3 is further connected with the first power supply 51 through the resistor R17, the fourth pin of the operational amplifier U3 is connected with the second power supply 52 through the resistor R19, the first power supply 51 is grounded through the capacitor C18, and the second power supply 52 is grounded through the capacitor C23. The RC filter is configured to filter noise in the voltage signal output by the operational amplifier U2, so as to reduce distortion generated during signal amplification. The capacitors C18 and C23 are used to filter noise in the first power supply 51 and the second power supply 52. Further, in order to accurately remove noise in the signal or in the power supply, the second amplifying unit 322 further includes a capacitor C19, a capacitor C20, a capacitor C24, a capacitor C25, and a resistor R16 and a capacitor C17 that form a second stage RC filter; the capacitor C19 and the capacitor C20 are connected in parallel with the capacitor C18, and the capacitor C24 and the capacitor C25 are connected in parallel with the capacitor C23.

As shown in fig. 3, the third amplifying unit 323 further includes a resistor R20 and a capacitor C26 that form an RC filter, a sliding resistor R23, a resistor R22, a resistor R24, a resistor R25, a capacitor C28, a capacitor C32, a capacitor C29, and a capacitor C33; the resistor R20 is respectively connected with the output end of the operational amplifier U3 and the same-directional end of the operational amplifier U4, the capacitor C26 is respectively connected with the second end of the resistor R20 and the ground end, the first pin of the operational amplifier U4 is connected with the fifth pin of the operational amplifier U4 through the sliding resistor R23, the moving end of the sliding resistor R23 is connected with the seventh pin of the operational amplifier U4, the output end of the operational amplifier U4 is connected with the conversion module 33 through the resistor R24, the fifth pin of the operational amplifier U4 is further grounded through the capacitor C28, the first pin of the operational amplifier U4 is further grounded through the capacitor C32, the seventh pin of the operational amplifier U4 is further connected with the first power supply 51 through the resistor R22, the fourth pin of the operational amplifier U4 is connected with the second power supply 52 through the resistor R25, and the first pin of the operational amplifier U4 is further grounded through the capacitor C29 and the second power supply 51 is grounded through the capacitor C33. It should be noted that, in order to accurately remove noise in the signal or in the power supply, the third amplifying unit 323 further includes a capacitor C30, a capacitor C31, a capacitor C34, a capacitor C35, and a resistor R21 and a capacitor C27 that form the second stage RC filter; the capacitor C30 and the capacitor C31 are connected in parallel with the capacitor C29, and the capacitor C34 and the capacitor C35 are connected in parallel with the capacitor C23.

In another embodiment, referring to fig. 4, fig. 4 is a circuit diagram of an amplifying module according to another embodiment of the present utility model, and as shown in fig. 4, the amplifying module 32 further includes a resistor R26, a resistor R27, a resistor R28, a capacitor C36, a capacitor C37, a capacitor C38, and a capacitor C41; the second end of the capacitor C37 is respectively connected with the same-direction end of the emitter follower U1 and one end of the capacitor C36, the first end of the capacitor C37 and the second end of the capacitor C36 are both used for grounding, the seventh pin of the emitter follower U1 is connected with the first power supply 51 through the capacitor R26, the fourth pin of the emitter follower U1 is connected with the second power supply 52 through the resistor R28, the output end of the emitter follower U1 is connected with the reverse end of the operational amplifier U3 through the resistor R27, the first power supply 51 is also connected with the grounding end through the capacitor C38, and the second power supply 52 is connected with the grounding end through the capacitor C41. It should be noted that, in order to accurately remove noise in the power supply, the amplifying module 32 further includes a capacitor C39, a capacitor C40, a capacitor C42, and a capacitor C43; the capacitor C39 and the capacitor C40 are connected in parallel with the capacitor C38, and the capacitor C42 and the capacitor C43 are connected in parallel with the capacitor C41.

In some embodiments, the resistor R5 and the resistor R7 may be replaced by digital potentiometers, and referring to fig. 5, fig. 5 is a circuit diagram of a digital potentiometer according to an embodiment of the present utility model, and as shown in fig. 5, the digital potentiometer includes a resistor R36, a resistor R37, a resistor R38, a resistor R39, a capacitor C50, a capacitor C51, a capacitor C52, and a digital potentiometer U8. The second pin of the digital potentiometer U8 is connected with a third power supply 53, the third pin of the digital potentiometer U8 is used for grounding, the third power supply 53 is grounded through a capacitor C50, both the capacitor C51 and the capacitor C52 are connected with the capacitor C50 in parallel, the first pin of the digital potentiometer U8 is connected with the fifth pin of the operational amplifier U2 (U3), and the eighth pin of the digital potentiometer U8 is connected with the sixth pin of the operational amplifier U2 (U3). The fourth pin of the digital potentiometer U8 is connected with a clock signal through a resistor R39, the fifth pin of the digital potentiometer U8 receives an input signal through a resistor R38, and the sixth pin of the digital potentiometer receives the type of the input signal through a resistor R37. The digital potentiometer U8 determines a resistance value through signals input by a fourth pin, a fifth pin and a sixth pin. It should be noted that, the digital potentiometer U8 replaces the resistor R5 or the resistor R7, so that the feedback resistors of the operational amplifier U2 and the operational amplifier U3 are adjustable, and further the signal amplification is adjusted. Alternatively, the digital potentiometer U8 may be of the type AD5160BRJZ100-RL7.

Referring to fig. 6, fig. 6 is a circuit diagram of a sampling module according to an embodiment of the present utility model, as shown in fig. 6, the sampling module 31 includes a diode D1, a diode D2, a diode D3, a diode D4, a diode D5, a diode D6, a diode D7, a voltage regulator D8, a voltage regulator D9, a sampling resistor R8, a resistor R9, and a capacitor C5; the first end of the sampling resistor R8 is respectively connected with the device 10 to be tested and the first end of the resistor R9, the second end of the sampling resistor R8 is used for being grounded, the second end of the resistor R9 is respectively connected with the anode of the voltage stabilizing tube D8, the first end of the capacitor C5 and the amplifying module 32, the cathode of the voltage stabilizing tube D8 is connected with the cathode of the voltage stabilizing tube D9, the anode of the voltage stabilizing tube D9 and the second end of the capacitor C5 are respectively connected with the grounding end, the diode D1, the diode D2, the diode D3, the diode D4 and the diode D5 are connected in series, the anode of the diode D1 is connected with the device 10 to be tested, the cathode of the diode D5 is connected with the grounding end, the cathode of the diode D6 is connected with the device 10 to be tested, the anode of the diode D6 and the cathode of the diode D7 are respectively connected with the grounding end, and the anode of the diode D7 is connected with the device 10 to be tested.

Specifically, the diode D1, the diode D2, the diode D3, the diode D4, and the diode D5 form a first protection unit, when the device to be tested 10 performs the dynamic gate bias test, if the voltage drop on the sampling resistor R8 is greater than the saturated voltage drop of the diode D1, the diode D2, the diode D3, the diode D4, and the diode D5, the current on the device to be tested 10 flows into the ground terminal through the diode, thereby avoiding the sampling resistor R8 from being damaged due to the overlarge voltage. The diode D6, the diode D7, the voltage stabilizing tube D8, the voltage stabilizing tube D9, the resistor R9 and the capacitor C5 form a second protection unit, and when a pulse voltage with a preset threshold value is output on the device to be tested 10, the pulse voltage is absorbed by the second protection unit, so that the sampling resistor R8 is prevented from being damaged.

In some embodiments, as shown in fig. 2, the signal processing circuit 30 further includes a processing module 34, where the processing module 34 is respectively connected to the amplifying module 32 and the converting module 34, and the processing module 34 is configured to process the voltage signal output by the amplifying module 32 to remove noise generated during signal amplification.

Specifically, referring to fig. 7, fig. 7 is a circuit diagram of a processing module provided in an embodiment of the present utility model, as shown in fig. 7, the processing module 34 includes an inductor L1, an inductor L2, a capacitor C1, a capacitor C2, a capacitor C3, a capacitor C4, a capacitor C53, and an emitter follower U6;

The first end of inductance L1 respectively with the output of amplification module 32 the first end of electric capacity C1 is connected, the second end of inductance L1 respectively with electric capacity C2's first end with inductance L2's first end is connected, inductance L2's second end respectively with emitter follower U6's syntropy end the first end of electric capacity C4 is connected, electric capacity C1, electric capacity C2 and the second end of electric capacity C4 all are used for ground connection, electric capacity C3 and electric capacity C53 all with electric capacity C2 connects in parallel, emitter follower U6's reverse end with emitter follower U6's output is connected, emitter follower U6's output still with conversion module 33 connects. It can be known that the inductor L1, the inductor L2, the capacitor C1, the capacitor C2, the capacitor C3, the capacitor C4 and the capacitor C53 form a passive butterworth filter, which is mainly used for filtering noise in the voltage signal output by the amplifying module 32, and the emitter follower U6 is used for removing impedance in the voltage signal. The emitter follower U1, the operational amplifier U2, the operational amplifier U3, the operational amplifier U4, and the emitter follower U6 are all in-phase proportional operational amplifiers, and in some embodiments, the emitter follower U1, the operational amplifier U2, the operational amplifier U3, the operational amplifier U4, and the emitter follower U6 may be in-phase proportional operational amplifiers of the same model, or may be operational amplifiers of different models.

In another embodiment, as shown in fig. 7, the processing module 34 further includes a resistor R29, a resistor R30, a resistor R31, a resistor R32, a resistor R33, a resistor R34, a capacitor C44, a capacitor C45, a capacitor C46, a capacitor C47, a capacitor C48, and a capacitor C49. The same direction end of the emitter follower U6 receives the voltage signal output by the amplifying module 32 through the resistor R30 and the resistor R29, the fourth pin of the emitter follower U6 is connected with the second power supply 52 through the resistor R32, the seventh pin of the emitter follower U6 is connected with the first power supply 51 through the resistor R31, the first power supply 51 is further connected with the grounding end through the capacitor C44, the capacitor C45 and the capacitor C46, and the second power supply 52 is further connected with the grounding end through the capacitor C47, the capacitor C48 and the capacitor C49. The output end of the emitter follower U6 is connected with the conversion module 33 through the resistor R33 and the resistor R34,

in some embodiments, as shown in fig. 7, the processing module 34 further includes a resistor R35, where the resistor R35 is connected to the second end of the resistor R33 and the controller 20, respectively. Specifically, after the processing module 34 outputs a voltage signal through the resistor R33, the voltage signal may also be directly input to the controller 20 through the resistor R35, so that the controller 20 directly stores the voltage signal.

In some embodiments, the conversion module 33 is an ADC chip U5, as shown in fig. 8, fig. 8 is a circuit diagram of the ADC chip provided in the embodiment of the utility model, as shown in fig. 8, the ADC chip U5 includes an input pin (41 st pin) and 14 output pins) (11 th pin-24 th pin), the input pin of the ADC chip U5 is connected to the output end of the amplifying module 32, and the output pin of the ADC chip U5 is used for outputting a digital signal. Specifically, the voltage signal output by the amplifying module 32 is an analog signal, and after the amplifying module 32 inputs the analog signal to the ADC chip U5, the ADC chip U5 converts the analog signal to convert the analog signal into a digital signal, and outputs the digital signal through the 14 output pins. Note that, the 24 th pin of the ADC chip U5 is the most significant bit, and the 11 th pin is the least significant bit. After the digital signals are output through the 14 output pins, the amplitude of the voltage signals can be known through the 14-bit digital signals and corresponding binary systems thereof. Optionally, the digital signal output by the ADC chip U5 is 2 scale. For example, when the digital signal is 2, and the output of the ADC chip U5 is 00000000011111 from pin 24 to pin 11, the amplitude corresponding to the digital signal is 62. Alternatively, the model of the ADC chip U5 may be AD9240ASZRL.

Further, the signal processing circuit 30 further includes a waveform processing module, where the waveform processing module is respectively connected to the controller 20 and a clock signal end (seventh pin) of the ADC chip U5, and the waveform processing module is configured to receive a clock signal output by the controller 20, and perform shaping processing on the clock signal, so that the clock signal received by the ADC chip U5 is a standard signal. The clock signal is a pulse signal, and when the frequency of the pulse signal is too high, the pulse signal is distorted, and at this time, the pulse signal is shaped by the waveform processing circuit, so that the pulse signal is ensured to be a standard pulse signal.

Specifically, referring to fig. 9, fig. 9 is a circuit diagram of a waveform processing module provided in an embodiment of the present utility model, as shown in fig. 9, the waveform processing module includes a hysteresis comparator U9, a resistor R40, a resistor R41, a resistor R42, a resistor R43, a resistor R44, a resistor R45, a capacitor C54, a capacitor C55, a capacitor C56, and a capacitor C57;

the second pin of the hysteresis comparator U9 is connected with the controller 20 through the resistor R41, the third pin of the hysteresis comparator U9 is connected with the sixth pin of the hysteresis comparator U9 through the resistor R43, the fourth pin of the hysteresis comparator U9 is connected with the third pin of the hysteresis comparator U9 and the second end of the resistor R40 through the resistor R42, the first end of the resistor R40 is connected with the fourth power supply 54, the fourth pin of the hysteresis comparator U9 is also connected with the ground end, the eighth pin of the hysteresis comparator U9 is also connected with the first end of the capacitor C54, the first end of the capacitor C54 is also used for grounding, the second end of the capacitor C54 is connected with the second end of the capacitor R44, the second end of the resistor R44 is also connected with the fourth power supply 54, the first end of the resistor R44 is also connected with the seventh pin of the hysteresis comparator U9, the fourth pin of the capacitor C55 is also connected with the fourth pin of the capacitor C45, the fourth pin of the capacitor C45 is also connected with the fourth pin of the capacitor C54 through the resistor C45, and the fourth pin of the capacitor C45 is also connected with the fourth pin of the capacitor C45.

In some embodiments, when the digital signal needs to be sent to the single chip microcomputer, since the driving capability of the ADC chip U5 is too weak, a buffer needs to be connected after the ADC chip U5 to send the digital signal to the controller 20 through the buffer. As shown in fig. 10, the buffer U7 includes 14 input ports and 14 output ports, the 14 input ports are connected to the 14 input ports of the ADC chip U5 in a one-to-one correspondence, and after receiving the 14-bit digital signal, the buffer U7 outputs the 14-bit digital signal to the controller 20 through the 14 output ports, so that the controller 20 stores the digital signal of the device under test 10. Alternatively, the model of the buffer U7 may be SN74 alcch 16825DGGR.

The utility model provides a signal processing circuit, which comprises a sampling module, an amplifying module and a conversion module; the sampling module is respectively connected with the device to be tested and the amplifying module, the amplifying module is connected with the conversion module, and the conversion module is also used for being in communication connection with the controller; when the device to be tested is in a dynamic gate bias test, the sampling module is used for collecting leakage current of the device to be tested, converting the leakage current into a voltage signal and inputting the voltage signal to the amplifying module so that the amplifying module amplifies the voltage signal; the conversion module is used for converting the amplified voltage signal into a digital signal and sending the digital signal to the controller so that the controller stores the digital signal of the device to be tested. Based on the method, when the semiconductor device fails, a digital signal corresponding to the semiconductor device is acquired, an electric parameter corresponding to the semiconductor device is obtained based on the digital signal and an algorithm program, and the reason of the failure of the semiconductor device is determined according to the electric parameter.

Finally, it should be noted that: the above embodiments are only for illustrating the technical solution of the present utility model, and are not limiting; the technical features of the above embodiments or in the different embodiments may also be combined within the idea of the utility model, the steps may be implemented in any order, and there are many other variations of the different aspects of the utility model as described above, which are not provided in detail for the sake of brevity; although the utility model has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit of the corresponding technical solutions from the scope of the technical solutions of the embodiments of the present application.

Claims (10)

1. The signal processing circuit is characterized by comprising a sampling module, an amplifying module and a conversion module;

the sampling module is respectively connected with the device to be tested and the amplifying module, the amplifying module is connected with the conversion module, and the conversion module is also used for being in communication connection with the controller;

When the device to be tested is in a dynamic gate bias test, the sampling module is used for collecting leakage current of the device to be tested, converting the leakage current into a voltage signal and inputting the voltage signal to the amplifying module so that the amplifying module amplifies the voltage signal;

the conversion module is used for converting the amplified voltage signal into a digital signal and sending the digital signal to the controller so that the controller stores the digital signal of the device to be tested.

2. The signal processing circuit according to claim 1, wherein the amplifying module includes a first amplifying unit, a second amplifying unit, a third amplifying unit, an emitter follower U1, and a slide rheostat R1;

the first input end of the first amplifying unit is connected with the sampling module, the second input end of the first amplifying unit is connected with the grounding end, the output end of the first amplifying unit is connected with the first input end of the second amplifying unit, the second input end of the second amplifying unit is connected with the output end of the emitter follower U1, the output end of the second amplifying unit is connected with the first input end of the third amplifying unit, the second input end of the third amplifying unit is connected with the grounding end, the output end of the third amplifying unit is connected with the conversion module, the first input end of the emitter follower U1 is connected with the second end of the sliding rheostat R1, the first end of the sliding rheostat R1 is connected with a first power supply, the second end of the sliding rheostat R1 is connected with a second power supply, and the second input end of the emitter follower U1 is connected with the output end of the emitter follower U1.

3. The signal processing circuit according to claim 2, wherein the first amplifying unit includes an operational amplifier U2, a resistor R2, and a resistor R3;

the same direction end of the operational amplifier U2 is connected with the sampling module, the reverse end of the operational amplifier U2 is connected with the grounding end through the resistor R2, the reverse end of the operational amplifier U2 is also connected with the output end of the operational amplifier U2 through the resistor R3, and the output end of the operational amplifier U2 is also connected with the first input end of the second amplifying unit.

4. A signal processing circuit according to claim 3, wherein the second amplifying unit includes an operational amplifier U3, a resistor R4, and a resistor R5;

the same direction end of the operational amplifier U3 is connected with the output end of the operational amplifier U2, the reverse end of the operational amplifier U3 is connected with the output end of the emitter follower U1 through the resistor R4, the reverse end of the operational amplifier U3 is also connected with the output end of the operational amplifier U3 through the resistor R5, and the output end of the operational amplifier U3 is also connected with the first input end of the third amplifying unit.

5. The signal processing circuit according to claim 4, wherein the third amplifying unit includes an operational amplifier U4, a resistor R6, and a resistor R7;

The same direction end of the operational amplifier U4 is connected with the output end of the operational amplifier U3, the reverse end of the operational amplifier U4 is connected with the grounding end through the resistor R6, the reverse end of the operational amplifier U4 is also connected with the output end of the operational amplifier U4 through the resistor R7, and the output end of the operational amplifier U4 is also connected with the conversion module.

6. The signal processing circuit of claim 1, wherein the sampling module comprises a diode D1, a diode D2, a diode D3, a diode D4, a diode D5, a diode D6, a diode D7, a regulator D8, a regulator D9, a sampling resistor R8, a resistor R9, and a capacitor C5;

the first end of sampling resistance R8 respectively with the device that awaits measuring the first end of resistance R9 is connected, the second end of sampling resistance R8 is used for ground connection, the second end of resistance R9 respectively with the positive pole of steady voltage tube D8, the first end of electric capacity C5 and amplification module 32 are connected, the negative pole of steady voltage tube D8 with the negative pole of steady voltage tube D9 is connected, the positive pole of steady voltage tube D9 with the second end of electric capacity C5 all is connected with the ground connection, diode D1, diode D2, diode D3, diode D4 and diode D5 establish ties, the positive pole of diode D1 is connected with the device that awaits measuring, the negative pole of diode D5 is connected with the ground connection, the negative pole of diode D6 with the device that awaits measuring, the positive pole of diode D6, the negative pole of diode D7 all is connected with the ground connection, the positive pole of diode D7 with the device that awaits measuring.

7. The signal processing circuit of claim 1, further comprising a processing module, wherein the processing module comprises an inductance L1, an inductance L2, a capacitance C1, a capacitance C2, a capacitance C3, a capacitance C4, and an emitter follower U6;

the first end of inductance L1 respectively with amplifying module's output the first end of electric capacity C1 is connected, inductance L1's second end respectively with electric capacity C2's first end with inductance L2's first end is connected, inductance L2's second end respectively with emitter follower U6's syntropy end the first end of electric capacity C4 is connected, electric capacity C1, electric capacity C2 and the second end of electric capacity C4 all are used for ground connection, electric capacity C3 with electric capacity C2 connects in parallel, emitter follower U6's reverse end with emitter follower U6's output is connected, emitter follower U6's output still with converting module connects.

8. The signal processing circuit of claim 1, wherein the conversion module is an ADC chip U5, the ADC chip U5 comprising an input pin and an output pin, wherein the output pins comprise 14; the input pin of the ADC chip U5 is connected with the output end of the amplifying module;

The ADC chip U5 is used for receiving the voltage signal output by the amplifying module and converting the voltage signal so as to output a 14-bit digital signal through an output pin of the ADC chip U5.

9. The signal processing circuit of claim 8, further comprising a buffer U7;

the buffer U7 comprises 14 input pins and 14 output pins, the 14 input pins of the buffer U7 are correspondingly connected with the 14 output pins of the ADC chip U5, and the 14 output pins of the buffer U7 are connected with the controller.

10. A signal processing system, the signal processing system comprising:

a device under test;

a controller; and

a signal processing circuit as claimed in any one of claims 1 to 9.