CN2203773Y

CN2203773Y - Rotary direction arbiter of coding device with doubling circuit

Info

Publication number: CN2203773Y
Application number: CN 94224992
Authority: CN
Inventors: 程建中; 黄效国
Original assignee: University of Science and Technology Beijing USTB
Current assignee: University of Science and Technology Beijing USTB
Priority date: 1994-08-09
Filing date: 1994-08-09
Publication date: 1995-07-19
Anticipated expiration: 2004-08-09

Abstract

The utility model relates to a rotary direction arbiter of a coding device with a doubling circuit, and comprises a rim discrimination circuit, a multiplex demodulator circuit, an inverter and a direction arbiter circuit. The output voltage pulse signals of phase A and phase B in two different phases of the rotary encoder are respectively input into the multiplex demodulator circuit and the rim discrimination circuit which is formed by that a capacitance resistant delay circuit and a rim discrimination delay pulse circuit are successively connected. The output signals of the rim discrimination circuit and the multiplex demodulator circuit enter the direction arbiter circuit after being reverted by the inverter.

Description

Rotary direction arbiter of coding device with doubling circuit

The utility model relates to a kind of sense of rotation arbiter that is used to detect the rotating object corner that rotary encoder is housed, particularly a kind of scrambler sense of rotation arbiter with frequency multiplier circuit.

In the modern control technology application, often need accurately to judge the direction and the rotating speed of rotating object.But be used for behind the voltage output type encoder (making E6A2 type rotary encoder) as Japanese Omron the discriminating direction device then seldom.And, in order to improve accuracy of detection (promptly improving resolution), also need to insert special frequency multiplication device, certainly will increase cost like this, adjust also very difficult simultaneously.In addition, the special-purpose counting assembly that is equipped with later (as counter chip or computing machine tally) is if untimely zero clearing is easy to cause numeration inaccurate because of overflowing.

The purpose of this utility model is to overcome the defective of present technology, and a kind of scrambler sense of rotation arbiter that adopts the band frequency multiplier circuit of integrated circuit component is provided.

Another purpose of the present utility model is to provide that a kind of circuit is simple, cost is lower, and the scrambler sense of rotation arbiter of the band frequency multiplier circuit of reset signal can be provided to counting assembly.

The purpose of this utility model is achieved in that a kind of scrambler sense of rotation arbiter with frequency multiplier circuit, comprise: the edge discriminator circuit, the demultiplexer circuit, phase inverter and discriminating direction device circuit, it is characterized in that: the output voltage pulse signal A of two outs of phase of rotary encoder inputs to demultiplexer circuit and edge discriminator circuit respectively mutually with B mutually, described edge discriminator circuit, differentiate by rc-delay circuit and edge that delay pulse circuit is linked in sequence and form signal approach axis arbiter circuit after phase inverter is anti-phase of edge discriminator circuit and the output of demultiplexer circuit.Described edge discriminator circuit is made up of two rc-delay circuits and two two input four Sheffer stroke gate integrated circuit D1 and D2; The A D1 that joins _1,2Pin is through D1 ₃Pin enters the resistance R 1 of rc-delay circuit, and R1 is connected with the base stage of triode DG1, the grounded emitter of DG1, and+5V power supply joins through the collector of potentiometer W1 and DG1, is connected with potentiometer W2 between W1 and DG1 collector, W2 and D1 _4,5Pin connects, at W2 and D1 _4,5Be connected to capacitor C 1 between the pin, the other end ground connection of capacitor C 1, D1 ₆Pin and D1 ₉Pin connects, when A is identical and D1 ₁₀Pin connects, D1 ₃Pin and D1 ₁₃Pin links to each other, D1 ₅Pin and D1 ₁₂Pin links to each other, D1 ₈Pin and D1 ₁₁Pin output edge delay pulse signal Q1 and Q2; The B D2 that joins _1,2Pin is through D2 ₃Pin enters the resistance R 2 of rc-delay circuit, and R2 is connected with the base stage of triode DG2, the grounded emitter of DG2, and+5V power supply links to each other with the collector of DG2 through potentiometer W3, is connected with potentiometer W4 between W3 and DG2 emitter, W4 and D2 _4,5Pin connects, at W4 and D2 _4,5Between be connected to capacitor C 2, the other end ground connection of capacitor C 2, D2 ₆Pin and D2 ₉Pin connects, when B is identical and D2 ₁₀Pin connects, D2 ₃Pin and D2 ₁₃Pin links to each other, D2 ₅Pin D2 ₁₂The pin D2 that links to each other ₈Pin and D2 ₁1 pin output edge delay pulse signal Q3 and Q4, described demultiplexer circuit is an integrated circuit D8, D8 ₁Pin ground connection D8 ₂Pin meets A phase, D8 ₃Pin meets B phase, D8 _4,5,6,7Pin divides limit output four kinds of potential state signal Y1, Y2, Y3 and Y4.Described phase inverter is two two input four Sheffer stroke gate integrated circuit D3 and D4, and D3 links to each other with the output of edge discriminator circuit, and D4 links to each other with the output of demultiplexer circuit.Described discriminating direction device circuit is imported two Sheffer stroke gate integrated circuit D7 for one four by two two input four Sheffer stroke gate integrated circuit D5 and D6, and two two inputs four are formed with a door integrated circuit D16; Q1 respectively with D5 ₁Pin and D6 ₉Pin links to each other, Q2 respectively with D5 ₉Pin and D6 ₁Pin links to each other, Q3 respectively with D5 ₄Pin and D6 ₁₂Pin links to each other, Q4 respectively with D5 ₁₂Pin and D6 ₄Pin links to each other, Y1 respectively with D5 ₁₃Pin and D6 ₂Pin links to each other, Y2 respectively with D5 ₁Pin and D6 ₅Pin links to each other, Y3 respectively with D5 ₁₀Pin and D6 ₁₃Pin links to each other, Y4 respectively with D5 ₅Pin and D6 ₁₀Pin links to each other; D5 _3,6,8,11Pin successively with D7 _1,2,4,5Pin links to each other, D6 _3,6,8,11Pin successively with D7 _9,10,12,13Pin links to each other; D7 ₆Pin and D16 ₁Pin links to each other, D7 ₈Pin and D16 ₅Pin links to each other; D16 ₃Pin is exported clockwise signal, D16 ₆Pin is exported counterclockwise signal.Described or the door D16 ₂Pin and D16 ₅Pin can join with scrambler Z phase voltage signal.Described W1,3 is 10K, and W2,4 is 4.7K, and C1,2 is 0.033u, and R1,2 is 10K, and DG1,2 model are 3DK4B; D1,2 is 74LS00.Described D8 is double demultiplexer 74LS139.Described D3 and D4 are 74LS00.Described D5 and D6 are 74LS00, and D7 is 74LS20, and D16 is 74LS32.

The utility model provides the scrambler sense of rotation arbiter of the band frequency multiplier circuit that does not have in a kind of prior art.It has the advantage that volume is little, cost is low, easy to manufacture, easy to adjust, can directly export 5 volts of normal voltages (giving computing machine), and can (clockwise with counterclockwise) provide reset signal on two directions.

With reference to the accompanying drawings most preferred embodiment of the present utility model is done more detailed description.

Fig. 1 is the principle of work block scheme of the scrambler sense of rotation arbiter of band frequency multiplier circuit of the present utility model;

Fig. 2 is an edge discriminator circuit schematic diagram;

Fig. 3 is the voltage pulse signal view;

Fig. 4 is demultiplexer circuit and phase inverter and discriminating direction device circuit theory diagrams.

With reference to accompanying drawing, Fig. 1 particularly, the utility model provides a kind of discriminating gear of three-phase voltage output type rotary encoder sense of rotation.And output turns clockwise or the counter-clockwise pulse signal that is several times as much as (as 4 times) scrambler output frequency that rotates respectively.Mainly by the discriminating on square-wave signal rising and trailing edge edge, demultiplexer and discriminating direction device three partly circuit constitute for it.The phase differential of A, B two-phase is 90 °.

The circuit that constitutes by Fig. 2 is to utilize rc-delay circuit, obtains the pulse output of square-wave signal rising edge and negative edge respectively, thereby identifies the edge of square-wave signal.Scrambler A, B two-phase output are imported rc-delay circuit by 1,2 pin of D1 and D2 respectively, 2 of A ', B ' are the time-delay output of scrambler A, B two-phase among the figure, promptly obtain Q1 after time-delay output signal and the Sheffer stroke gate conversion of original signal in D1, D2, Q2, Q3, the delay pulse output of four edges of Q4, the width of output pulse can be regulated by adjusting delay time.Q1---the phase differential between the Q4 is 90 °, and the precision of phase differential is decided by the precision of scrambler A, B two-phase phase differential.By illustrated parameter pulse output sum frequency can be more than the 30KHZ.

Referring to Fig. 3, to carve at a time, scrambler A, B two-phase output only have 4 kinds of potential states, that is: 0(A1A2), 0(B1B2) ］; 1(A2A3), 0(B2B3) ］; 1(A3A4), 1(B3B4) ］; 0(A4A5), 1(B4B5) ］.Under every kind of potential state, the corresponding A that scrambler changes clockwise or its output of counterclockwise rotation is all determined, certain rising edge of exporting mutually or negative edge in the B two-phase, so determine to carve at a time the potential state of A, B two-phase, that differentiate output at this moment simultaneously again is Q1---which pulse among the Q4 can determine the sense of rotation of scrambler.Thereby allow at this direction output pulse signal.

Fig. 2 has constituted the complete circuit of most preferred embodiment of the present utility model with Fig. 4.

D8 adopts 74LS139 as demultiplexer as shown in Figure 4, scrambler A, and the B two-phase just can be represented the Y1 of A, 4 kinds of potential states of B two-phase, Y2, Y3, four output signals of Y4 respectively by 2, the 3 pin input of D8.Press the connection of five Sheffer stroke gate integrated circuit (IC) chip of D3-D7 among Fig. 4, behind comprehensive eight signals of Q1---Q4 and Y1---Y4, can differentiate scrambler is to change clockwise or counterclockwise rotation at this constantly, when scrambler rotates continuously in a direction, can export one 4 times of pulse signals at the output terminal of this direction to the scrambler output frequency, shield the pulse output of opposite sense of rotation output terminal simultaneously, the 4 double frequency pulse signals that output of two output terminals of D7 (6 pin of D7 and 8 pin of D7) is changeed clockwise, another exports anticlockwise 4 double frequency pulse signals, uses for outside counting device through D16.D3 among the figure, D4 only for level join with phase inverter.

Disposed or door D16 in the final output of discriminating direction device.2,4 pin at D16 have added scrambler Z phase signals, see Fig. 4.Make scrambler once Z phase output signal occurs, 3 pin of two output terminal D16 of discriminating direction device and 6 pin are then exported a reset signal simultaneously, this aims at some outside register and is provided with, as does not have this needs, can be easy to cancel this reset signal in circuit.

Frequency in the utility model can be 0,2,4 or 8, can adjust as required.

Selected integrated circuit (IC) chip can be to realize setting in the block diagram 1 integrated circuit of any model of function in the utility model circuit, the preferred integrated circuit that adopts following model among the application:

D1～D6: two inputs, four Sheffer stroke gate 74LS00;

D7: four inputs, two Sheffer stroke gate 74LS20;

D8: double demultiplexer 74LS139;

D16: two inputs four or door 74LS32.

Claims

1, a kind of scrambler sense of rotation arbiter with frequency multiplier circuit, it comprises edge discriminator circuit, demultiplexer circuit, phase inverter and discriminating direction device circuit, it is characterized in that: the output voltage pulse signal A of two outs of phase of rotary encoder inputs to demultiplexer circuit and edge discriminator circuit respectively mutually with B mutually, described edge discriminator circuit, differentiate by rc-delay circuit and edge that delay pulse circuit is linked in sequence and form signal approach axis arbiter circuit after phase inverter is anti-phase of edge discriminator circuit and the output of demultiplexer circuit.

2, the scrambler sense of rotation arbiter of band frequency multiplier circuit as claimed in claim 1 is characterized in that: described edge discriminator circuit is made up of two rc-delay circuits and two two input four Sheffer stroke gate integrated circuit D1 and D2; The A D1 that joins _1,2Pin is through D1 ₃Pin enters the resistance R 1 of rc-delay circuit, and R1 is connected with the base stage of triode DG1, the grounded emitter of DG1, and+5V power supply joins through the collector of potentiometer W1 and DG1, is connected with potentiometer W2 between W1 and DG1 collector, W2 and D1 _4,5Pin connects, at W2 and D1 _4,5Be connected to capacitor C 1 between the pin, the other end ground connection of capacitor C 1, D1 ₆Pin and D1 ₉Pin connects, when A is identical and D1 ₁₀Pin connects, D1 ₃Pin and D1 ₁₃Pin links to each other, D1 ₅Pin and D1 ₁₂Pin links to each other, D1 ₈Pin and D1 ₁₁Pin output edge delay pulse signal Q1 and Q2; The B D2 that joins _1,2Pin is through D2 ₃Pin enters the resistance R 2 of rc-delay circuit, and R2 is connected with the base stage of triode DG2, the grounded emitter of DG2, and+5V power supply links to each other with the collector of DG2 through potentiometer W3, is connected with potentiometer W4 between W3 and DG2 emitter, W4 and D2 _4,5Pin connects, at W4 and D2 _4,5Between be connected to capacitor C 2, the other end ground connection of capacitor C 2, D2 ₆Pin and D2 ₉Pin connects, when B is identical and D2 ₁₀Pin connects, D2 ₃Pin and D2 ₁₃Pin links to each other, D2 ₅Pin D2 ₁₂Pin links to each other, D2 ₈Pin and D2 ₁₁Pin output edge delay pulse signal Q3 and Q4.

3, the scrambler sense of rotation arbiter of band frequency multiplier circuit as claimed in claim 1 is characterized in that: described demultiplexer circuit is an integrated circuit D8, D8 ₁Pin ground connection, D8 ₂Pin meets A phase, D8 ₃Pin meets B phase, D8 _4,5,6,7Pin divides limit output four kinds of potential state signal Y1, Y2, Y3 and Y4.

4, the scrambler sense of rotation arbiter of band frequency multiplier circuit as claimed in claim 1, it is characterized in that: described phase inverter is two two input four Sheffer stroke gate integrated circuit D3 and D4, D3 links to each other with the output of edge discriminator circuit, and D4 links to each other with the output of demultiplexer circuit.

5, the scrambler sense of rotation arbiter of band frequency multiplier circuit as claimed in claim 1, it is characterized in that: described discriminating direction device circuit is by two two input four Sheffer stroke gate integrated circuit D5 and D6, one four input two Sheffer stroke gate integrated circuit D7, two two inputs four or a door integrated circuit D16 form; Q1 respectively with D5 ₁Pin and D6 ₉Pin links to each other, Q2 respectively with D5 ₉Pin and D6 ₁Pin links to each other, Q3 respectively with D5 ₄Pin and D6 ₁₂Pin links to each other, Q4 respectively with D5 ₁₂Pin and D6 ₄Pin links to each other, Y1 respectively with D5 ₁₃Pin and D6 ₂Pin links to each other, Y2 respectively with D5 ₁Pin and D6 ₅Pin links to each other, Y3 respectively with D5 ₁₀Pin and D6 ₁₃Pin links to each other, Y4 respectively with D5 ₅Pin and D6 ₁₀Pin links to each other; D5 _3,6,8,11Pin successively with D7 _1,2,4,5Pin links to each other, D6 _3,6,8,11Pin successively with D7 _9,10,12,13Pin links to each other; D7 ₆Pin and D16 ₁Pin links to each other, D7 ₈Pin and D16 ₅Pin links to each other; D16 ₃Pin is exported clockwise signal, D16 ₆Pin is exported counterclockwise signal.

6, the scrambler sense of rotation arbiter of band frequency multiplier circuit as claimed in claim 5 is characterized in that: described or door D16 ₂Pin and D16 ₅Pin can join with scrambler Z phase voltage signal.

7, the scrambler sense of rotation arbiter of band frequency multiplier circuit as claimed in claim 2 is characterized in that: described W1,3 is 10K, and W2,4 is 4.7K, and C1,2 is 0.033u, and R1,2 is 10K; DG1,2 model are 3DK4B; D1,2 is 74LS00.

8, the scrambler sense of rotation arbiter of band frequency multiplier circuit as claimed in claim 3 is characterized in that: described D8 is double demultiplexer 74LS139.

9, the scrambler sense of rotation arbiter of band frequency multiplier circuit as claimed in claim 4, it is characterized in that: described D3 and D4 are 74LS00.

10, the scrambler sense of rotation arbiter of band frequency multiplier circuit as claimed in claim 5, it is characterized by: described D5 and D6 are 74LS00, and D7 is 74LS20, and D16 is 74LS32.