CN220368701U - Signal generation circuit, control circuit and DCDC conversion circuit - Google Patents
Signal generation circuit, control circuit and DCDC conversion circuit Download PDFInfo
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- CN220368701U CN220368701U CN202321767834.6U CN202321767834U CN220368701U CN 220368701 U CN220368701 U CN 220368701U CN 202321767834 U CN202321767834 U CN 202321767834U CN 220368701 U CN220368701 U CN 220368701U
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Abstract
The application provides a signal generation circuit, a control circuit and a DCDC conversion circuit, and relates to the technical field of electronic circuits. The signal generation circuit includes: the device comprises an error correction module, a ripple injection module and a summation comparator; the first input end of the error correction module is connected with a reference power supply, the second input end of the error correction module is connected with the voltage output end of the DCDC converter, the output end of the error correction module is connected with the first positive input end of the summation comparator, and the second positive input end of the summation comparator is connected with the reference power supply; the input end of the ripple injection module is connected with the first output end of the control unit corresponding to the DCDC converter, the output end of the ripple injection module is connected with the first negative input end of the summation comparator, the second negative input end of the summation comparator is connected with the voltage output end of the DCDC converter, and the output end of the summation comparator is connected with the input end of the control unit. The method and the device can improve the working stability of the DCDC converter.
Description
Technical Field
The present utility model relates to the technical field of electronic circuits, and in particular, to a signal generating circuit, a control circuit, and a DCDC conversion circuit.
Background
In a Constant On Time (COT) direct current-to-direct current (DC-DC) converter, the generation of the pwm signal is triggered by a ripple On the output voltage.
Ripple waves in a reasonable range can improve stability of the DCDC converter and cannot damage the stability of the DCDC converter, but the DCDC converter is difficult to keep in a stable working state due to half ripple errors of output voltage of the DCDC converter and influence of other non-ideal factors in a loop.
Disclosure of Invention
The present utility model has been made in view of the above-described drawbacks of the related art, and an object of the present utility model is to provide a signal generating circuit, a control circuit, and a DCDC converting circuit, which can improve the operation stability of a DCDC converter.
In order to achieve the above purpose, the technical solution adopted in the embodiment of the present application is as follows:
in a first aspect, embodiments of the present application provide a signal generating circuit, including: the device comprises an error correction module, a ripple injection module and a summation comparator;
the first input end of the error correction module is connected with a reference power supply, the second input end of the error correction module is connected with the voltage output end of the DCDC converter, the output end of the error correction module is connected with the first positive input end of the summation comparator, and the second positive input end of the summation comparator is connected with the reference power supply;
the input end of the ripple injection module is connected with the first output end of the control unit corresponding to the DCDC converter, the output end of the ripple injection module is connected with the first negative input end of the summation comparator, the second negative input end of the summation comparator is connected with the voltage output end of the DCDC converter, and the output end of the summation comparator is connected with the input end of the control unit.
Optionally, the signal generating circuit further includes: a maladjustment elimination module;
wherein the offset cancellation module is connected to a third positive input of the summing comparator.
Optionally, the ripple injection module includes: an integrator and an operational transconductance amplifier;
the input end of the integrator is used as the input end of the ripple injection module, the first output end of the integrator is connected with the first input end of the operational transconductance amplifier, the second output end of the integrator is connected with the second input end of the operational transconductance amplifier, and the output end of the operational transconductance amplifier is used as the output end of the ripple injection module.
Optionally, the integrator includes: a first transistor, a second transistor, an inverter, a first resistor, a second resistor, a first capacitor, and a second capacitor;
the grid electrode of the first transistor and the input end of the inverter are connected to serve as the input end of the integrator, the output end of the inverter is connected to the grid electrode of the second transistor, the source electrode of the first transistor and the source electrode of the second transistor are connected with first bias current, the drain electrode of the second transistor is respectively connected with one end of the first resistor, one end of the first capacitor and one end of the second resistor, the connection point of the drain electrode of the second transistor is used as the first output end of the integrator, one end of the second resistor is connected with one end of the second capacitor to serve as the second input end of the integrator, and the drain electrode of the first transistor, the other end of the first resistor, the other end of the first capacitor and the other end of the second capacitor are grounded.
Optionally, the operational transconductance amplifier includes: the first current mirror, the second current mirror, the third current mirror, the fourth current mirror and the differential voltage comparison unit;
the input end of the first current mirror is connected with a second bias current, the output end of the first current mirror is connected with the current input end of the differential voltage comparison unit, the first voltage input end of the differential voltage comparison unit is used as the first input end of the operational transconductance amplifier, the second voltage input end of the differential voltage comparison unit is used as the second input end of the operational transconductance amplifier, the first output end of the differential voltage comparison unit is connected with the input end of the second current mirror, the second output end of the differential voltage comparison unit is connected with the input end of the third current mirror, the output end of the third current mirror is connected with the input end of the fourth current mirror, and the output end of the second current mirror and the output end of the fourth current mirror are connected to serve as the output end of the operational transconductance amplifier.
In a second aspect, embodiments of the present application further provide a control circuit, including: a signal generating circuit and control unit as claimed in any one of the first aspects;
the signal generating circuit is connected with the input end of the control unit, and the output end of the control unit is connected with the control end of the power device in the DCDC converter.
Optionally, the control circuit further includes: an on-time timer;
the on-time timer is connected with the control unit.
Optionally, the control circuit further includes: a minimum off-time timer;
the minimum off-time timer is connected to the control unit.
Optionally, the control circuit further includes: a first buffer and a second buffer;
the first buffer is connected between a first output end of the control unit and a control end of a first group of power devices in the DCDC converter;
the second buffer is connected between the second output end of the control unit and the control end of the second group of power devices in the DCDC converter.
In a third aspect, embodiments of the present application further provide a DCDC conversion circuit, including: the control circuit and DCDC converter of any one of the second aspects;
the control circuit is connected with the control end of the power device in the DCDC converter.
The beneficial effects of this application are:
the signal generation circuit, the control circuit and the DCDC conversion circuit provided by the application, wherein the error correction module generates error voltage according to the reference voltage and the feedback voltage, can eliminate half ripple errors existing in the feedback voltage, and then the ripple injection module generates ripple voltage, so that the summation comparator can control the DCDC converter to work stably according to comparison signals output by the reference voltage, the error voltage, the feedback voltage and the ripple voltage.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present utility model, the drawings that are needed in the embodiments will be briefly described below, it being understood that the following drawings only illustrate some embodiments of the present utility model and therefore should not be considered as limiting the scope, and other related drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
Fig. 1 is a schematic block diagram of a signal generating circuit according to an embodiment of the present application;
FIG. 2 is a schematic block diagram II of a signal generating circuit according to an embodiment of the present application;
FIG. 3 is a schematic circuit diagram of a ripple injection module according to an embodiment of the present disclosure;
FIG. 4 is a schematic block diagram of a control circuit provided in an embodiment of the present application;
fig. 5 is a schematic block diagram of a DCDC conversion circuit according to an embodiment of the present application.
Detailed Description
For the purpose of making the objects, technical solutions and advantages of the embodiments of the present utility model more apparent, the technical solutions of the embodiments of the present utility model will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present utility model, and it is apparent that the described embodiments are some embodiments of the present utility model, but not all embodiments of the present utility model.
Thus, the following detailed description of the embodiments of the present application, as provided in the accompanying drawings, is not intended to limit the scope of the application, as claimed, but is merely representative of selected embodiments of the application. All other embodiments, which can be made by one of ordinary skill in the art based on the embodiments herein without making any inventive effort, are intended to be within the scope of the present application.
Furthermore, the terms first, second and the like in the description and in the claims and in the above-described figures, are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged where appropriate such that the embodiments of the utility model described herein may be implemented in sequences other than those illustrated or otherwise described herein. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.
It should be noted that, without conflict, features in embodiments of the present application may be combined with each other.
Referring to fig. 1, which is a schematic block diagram of a signal generating circuit according to an embodiment of the present application, as shown in fig. 1, the signal generating circuit 10 may include: an error correction module 101, a ripple injection module 102 and a summing comparator 103.
The first input end of the error correction module 101 is connected with a reference power supply, the second input end of the error correction module 101 is connected with the voltage output end of the DCDC converter, the output end of the error correction module 101 is connected with the first positive input end of the summation comparator 103, and the second positive input end of the summation comparator 103 is connected with the reference power supply; the input end of the ripple injection module 102 is connected with the first output end of the control unit corresponding to the DCDC converter, the output end of the ripple injection module 102 is connected with the first negative input end of the summation comparator 103, the second negative input end of the summation comparator 103 is connected with the voltage output end of the DCDC converter, and the output end of the summation comparator 103 is connected with the input end of the control unit.
In this embodiment, a first input end of the error correction module 101 is connected to a reference power supply, and is used for obtaining a reference voltage VREF, a second input end of the error correction module 101 is connected to a voltage output end of the DCDC converter, and is used for obtaining an output voltage of the DCDC converter as a feedback voltage VFB, the error correction module 101 samples an error between the reference voltage VREF and the feedback voltage VFB, and converts the sampled error voltage into an error current, and inputs the error current to a first positive input end of the summing comparator 103.
The input end of the ripple injection module 102 is connected to a first output end of a control unit corresponding to the DCDC converter, and is configured to obtain a ripple injection control signal TON, and the ripple injection module 102 generates a ripple voltage under the control of the ripple injection control signal TON and converts the ripple voltage into a ripple current, and injects the ripple current to a first negative input end of the summing comparator 103.
A second positive input end of the summing comparator 103 is connected with a reference power supply and is used for acquiring a reference voltage VREF, and the summing comparator 103 converts the error current input by the error correction module 101 into an error voltage again and then superimposes the error voltage on the reference voltage VREF; the second negative input end of the summing comparator 103 is connected to the voltage output end of the DCDC converter, and is used for obtaining the feedback voltage VFB, the summing comparator 103 further converts the ripple current injected by the ripple injection module 102 into the ripple voltage again and then superimposes the ripple voltage on the feedback voltage VFB, and the summing comparator 103 compares the superimposed reference voltage with the superimposed feedback voltage to output a comparison signal.
When the superimposed feedback voltage is smaller than the superimposed reference voltage, the summing comparator 103 outputs a high-level comparison signal, and at this time, the control unit of the DCDC converter controls the output voltage of the DCDC converter to rise according to the high-level comparison signal; when the superimposed feedback voltage is greater than the superimposed reference voltage, the summing comparator 103 outputs a low-level comparison signal, and at this time, the control unit of the DCDC converter controls the output voltage of the DCDC converter to decrease according to the low-level comparison signal.
According to the signal generation circuit provided by the embodiment, the error correction module generates the error voltage according to the reference voltage and the feedback voltage, so that half ripple errors existing in the feedback voltage can be eliminated, and the ripple injection module generates the ripple voltage, so that the summation comparator can control the DCDC converter to stably work according to the comparison signals output by the reference voltage, the error voltage, the feedback voltage and the ripple voltage.
In one possible implementation, as shown in fig. 1, the signal generating circuit 10 further includes: a detuning cancellation module 104; wherein the offset cancellation block 104 is connected to a third positive input of the summing comparator 103.
In this embodiment, in order to avoid that the no-load voltage accuracy of the DCDC converter is reduced due to the dc offset during soft start of the DCDC converter, the offset cancellation module 104 is connected to the third positive input terminal of the summing comparator 103, and the offset cancellation module 104 is configured to generate an offset cancellation signal to improve the offset of the DCDC converter due to the ripple voltage injected by the ripple injection module 102.
According to the signal generation circuit provided by the embodiment, the offset elimination module is used for providing the offset elimination signal, on one hand, the direct current offset can be corrected before soft start, the offset of the output voltage caused by ripple voltage is avoided, and the voltage precision of the DCDC converter in an idle state is improved; on the other hand, the error correction module is prevented from working in a clamping state in a low power consumption mode, and the no-load transient response of the DCDC converter can be improved.
One possible implementation of the ripple injection module is described below with reference to the drawings and embodiments.
Referring to fig. 2, for a second schematic block diagram of the signal generating circuit provided in the embodiment of the present application, as shown in fig. 2, the ripple injection module 102 may include: an integrator 121 and an operational transconductance amplifier 122.
The input end of the integrator 121 is used as the input end of the ripple injection module 102, the first output end of the integrator 121 is connected with the first input end of the operational transconductance amplifier 122, the second output end of the integrator 121 is connected with the second input end of the operational transconductance amplifier 122, and the output end of the operational transconductance amplifier 122 is used as the output end of the ripple injection module 102.
In this embodiment, the integrator 121 is connected to a first output end of a control unit corresponding to the DCDC converter, and is configured to obtain the ripple injection control signal TON, and after the integrator 121 starts working based on the ripple injection control signal TON, the integrator is based onThe bias current Isrc generates a ripple voltage V ripple And ripple voltage V ripple The operational transconductance amplifier 122 is based on the ripple voltage V ripple Ripple voltage V ripple Generating ripple current I from the difference between the dc components of (a) ripple 。
Wherein the ripple injection control signal TON is provided by the control unit of the DCDC converter, the output signal of the control unit is determined by the comparison signal output by the summing comparator 103, when the superimposed feedback voltage is smaller than the superimposed reference voltage, the summing comparator 103 outputs a high-level comparison signal, so that the ripple injection control signal TON output by the control unit is a high-level signal, in which case the feedback voltage VFB output by the DCDC converter increases, and the ripple voltage V output by the integrator 121 ripple Rising to increase the feedback voltage after superposition; when the superimposed feedback voltage is greater than the superimposed reference voltage, the summing comparator 103 outputs a low-level comparison signal such that the ripple injection control signal TON output by the control unit is a low-level signal, in which case the feedback voltage VFB output by the DCDC converter decreases and the ripple voltage V output by the integrator 121 ripple Descending.
In one possible implementation, please refer to fig. 3, which is a schematic circuit diagram of a ripple injection module provided in an embodiment of the present application, as shown in fig. 3, an integrator 121 includes: the first transistor MP1, the second transistor MP2, the inverter U1, the first resistor R1, the second resistor R2, the first capacitor C1 and the second capacitor C2.
The gate of the first transistor MP1 and the input end of the inverter U1 are connected as the input end of the integrator 121, the output end of the inverter U1 is connected to the gate of the second transistor MP2, the source of the first transistor MP1 and the source of the second transistor MP2 are connected to the first bias current Isrc, the drain of the second transistor MP2 is respectively connected to one end of the first resistor R1, one end of the first capacitor C1 and one end of the second resistor R2, the connection point is used as the first output end of the integrator 121, the other end of the second resistor R2 is connected to one end of the second capacitor C2 as the second input end of the integrator 121, and the drain of the first transistor MP1, the other end of the first resistor R1, the other end of the first capacitor C1 and the other end of the second capacitor C2 are grounded.
In this embodiment, the first transistor MP1 and the second transistor MP2 are PMOS transistors, and are used as switching transistors in the integrator 121, and the first resistor R1 is connected in parallel to two ends of the first capacitor C1 to form an RC network for sampling the ripple voltage V across the first capacitor C1 through the first resistor R1 ripple The second resistor R2 is connected in series with the second capacitor C2 to form an RC low-pass filter for the ripple voltage V ripple Low-pass filtering to obtain ripple voltage V ripple Is a direct current component VLP of (c).
When the superimposed feedback voltage is smaller than the superimposed reference voltage, the summing comparator 103 outputs a high-level comparison signal to raise the feedback voltage VFB output by the DCDC converter; the ripple injection control signal TON is a high level signal, the first transistor MP1 is turned off, the second transistor MP1 is turned on, since the resistance-capacitance value of the second resistor R2 and the second capacitor C2 is larger than the resistance-capacitance value of the first resistor R1 and the first capacitor C1, the current flowing into the low pass filter can be ignored, the first bias current Isrc flows into the RC network through the second transistor MP2, and the ripple voltage V is caused by charging the first capacitor C1 ripple Raised.
At the feedback voltage VFB and the ripple voltage V ripple When the feedback voltage after superposition is increased to be greater than the reference voltage after superposition, the summing comparator 103 outputs a low-level comparison signal to reduce the feedback voltage VFB output by the DCDC converter; the ripple injection control signal TON is a low level signal, the first transistor MP1 is turned on, the second transistor MP1 is turned off, the first bias current Isrc flows into GND through the first transistor MP1, the charge on the first capacitor C1 is discharged to GND through the first resistor R1, and the discharge of the first capacitor R1 causes the ripple voltage V ripple Descending.
In one possible implementation, the operational transconductance amplifier 122 includes: the device comprises a first current mirror, a second current mirror, a third current mirror, a fourth current mirror and a differential voltage comparison unit.
The input end of the first current mirror is connected with the second bias current, the output end of the first current mirror is connected with the current input end of the differential voltage comparison unit, the first voltage input end of the differential voltage comparison unit is used as the first input end of the operational transconductance amplifier, the second voltage input end of the differential voltage comparison unit is used as the second input end of the operational transconductance amplifier, the first output end of the differential voltage comparison unit is connected with the input end of the second current mirror, the second output end of the differential voltage comparison unit is connected with the input end of the third current mirror, the output end of the third current mirror is connected with the input end of the fourth current mirror, and the output end of the second current mirror and the output end of the fourth current mirror are connected to serve as the output end of the operational transconductance amplifier.
In this embodiment, as shown in fig. 3, the first current mirror includes: a third transistor MP3 and a fourth transistor MP4, the second current mirror comprising: a fifth transistor MN1 and a sixth transistor MN2, the third current mirror including: the seventh transistor MN3 and the eighth transistor MN4, and the fourth current mirror includes: a ninth transistor MP5 and a tenth transistor MP6; the differential voltage comparing unit includes: the third resistor R3, the fourth resistor R4, the eleventh transistor MP7, and the twelfth transistor MP8.
The third transistor MP3, the fourth transistor MP4, the ninth transistor MP5, the tenth transistor MP6, the eleventh transistor MP7, and the twelfth transistor MP8 are PMOS transistors, and the fifth transistor MN1, the sixth transistor MN2, the seventh transistor MN3, and the eighth transistor MN4 are NMOS transistors.
The drain electrode of the third transistor MP3 is connected to the gate electrode of the third transistor MP3 as the input end of the first current mirror and connected to the second bias current Ibias, the source electrode of the third transistor MP3 and the source electrode of the fourth transistor MP4 are connected to the input voltage VIN, the gate electrode of the fourth transistor MP4 is connected to the gate electrode of the third transistor MP3, and the drain electrode of the fourth transistor MP4 is used as the output end of the first current mirror.
One end of the third resistor R3 and one end of the fourth resistor R4 are connected with a current input end serving as a differential voltage comparison unit, the other end of the third resistor R3 is connected with a source electrode of an eleventh transistor MP7, a grid electrode of the eleventh transistor MP7 serves as a first voltage input end of the differential voltage comparison unit, and a drain electrode of the eleventh transistor MP7 serves as a first output end of the differential voltage comparison unit; the other end of the fourth resistor R4 is connected to the source of the twelfth transistor MP8, the gate of the twelfth transistor MP8 is used as the second voltage input end of the differential voltage comparing unit, and the drain of the twelfth transistor MP8 is used as the second output end of the differential voltage comparing unit.
The drain electrode of the fifth transistor MN1 is connected to the gate electrode of the fifth transistor MN1 as the input end of the second current mirror, and is connected to the drain electrode of the eleventh transistor MP7, the gate electrode of the fifth transistor MN1 is also connected to the gate electrode of the sixth transistor MN2, the drain electrode of the sixth transistor MN2 is used as the output end of the second current mirror, and the source electrode of the fifth transistor MN1 and the source electrode of the sixth transistor MN2 are connected to GND.
The drain electrode of the seventh transistor MN3 is connected to the gate electrode of the seventh transistor MN3 as the input end of the third current mirror, and is connected to the drain electrode of the twelfth transistor MN8, the gate electrode of the seventh transistor MN3 is also connected to the gate electrode of the eighth transistor MN4, the drain electrode of the eighth transistor MN3 is used as the output end of the third current mirror, and the source electrode of the seventh transistor MN3 and the source electrode of the eighth transistor MN4 are connected to GND.
The drain of the ninth transistor MP5 is connected with the gate of the ninth transistor MP5 as the input end of the fourth current mirror and connected with the drain of the eighth transistor MN4, the gate of the ninth transistor MP5 is also connected with the gate of the tenth transistor MP6, the source of the ninth transistor MP5 is connected with the source of the tenth transistor MP6 to input the voltage VIN, the drain of the tenth transistor MP6 is used as the output end of the fourth current mirror and connected with the drain of the sixth transistor MN2 for outputting the ripple current I ripple 。
Based on the signal generating circuit of the above embodiment, the embodiment of the present application also provides a control circuit applying the signal generating circuit. Referring to fig. 4, which is a schematic block diagram of a control circuit provided in an embodiment of the present application, as shown in fig. 4, a control circuit 100 includes: the signal generating circuit 10 and the control unit 20 of the above-described embodiment.
The signal generating circuit 10 is connected to an input end of the control unit 20, and an output end of the control unit 20 is connected to a control end of a power device in the DCDC converter.
In this embodiment, an output end of the signal generating circuit 10 is connected to an input end of the control unit 20, and is used for outputting a comparison signal to the control unit 20, the control unit 20 outputs a control signal according to the comparison signal to control on or off of power devices in the DCDC converter, wherein when the signal generating circuit 10 outputs a high-level comparison signal, a control signal output by a first output end of the control unit 20 controls a first group of power devices in the DCDC converter to be on, and a control signal output by a second output end controls a second group of power devices in the DCDC converter to be off, so that an output voltage of the DCDC converter is increased; when the signal generating circuit 10 outputs the low-level comparison signal, the control signal output by the first output end controls the first group of power devices in the DCDC converter to be disconnected, and the control signal output by the second output end controls the second group of power devices in the DCDC converter to be conducted, so that the output voltage of the DCDC converter is reduced.
In some embodiments, the first output terminal of the control unit 20 is connected to the input terminal of the ripple injection module, and is configured to obtain the control signal output by the first output terminal as the ripple injection control signal TON.
In one possible implementation, as shown in fig. 4, the control circuit 100 further includes: on-time timer 30, on-time timer 30 is connected to control unit 20.
In this embodiment, a turn-On time timer (On timer) 30 is connected to the first clock signal end of the control unit 20, and is used for generating a constant turn-On time, and in the turn-On time, the control signal controls the first group of power devices to be turned On, controls the second group of power devices to be turned off, and increases the output voltage; after the conducting time is over, the narrow pulse signal generated by the timer controls the first group of power devices to be turned off, controls the second group of power devices to be turned on, reduces the output voltage, and when the feedback voltage VFB is reduced to be smaller than the reference voltage VREF, the signal generating circuit 10 outputs a high-level comparison signal again, and the conducting time timer 30 begins to count again.
In one possible implementation, as shown in fig. 4, the control circuit 100 further includes: a minimum off-time timer 40, the minimum off-time timer 40 being connected to the control unit 20.
In this embodiment, a minimum off time Timer (minimum off Timer) 40 is connected to the second clock signal end of the control unit, and due to the influence of parasitic inductance of the power device, the power device may accompany a large amount of noise at the moment of switching between on and off states, so that the feedback voltage output by the DCDC converter may oscillate below the reference voltage, if the summing comparator immediately outputs a high-level comparison signal according to the feedback voltage at this time, the control unit 20 immediately turns on the first group of power devices to cause erroneous judgment, so that a minimum off time needs to be introduced into the control circuit, the control unit will not generate any control signal within the minimum off time, avoiding noise time, and generating a control signal according to the comparison signal generated by the feedback voltage after the minimum off time is finished.
It should be noted that, the minimum off time provided by the minimum off time timer 40 needs to be within a suitable range to avoid that the excessively short minimum off time cannot avoid noise, and avoid that the excessively long minimum off time slows down the transient response speed of the DCDC converter. Wherein the minimum off-time may be, for example, several hundred ns.
In one possible implementation, as shown in fig. 4, the control circuit 100 further includes: a first buffer 50 and a second buffer 60, wherein the first buffer 50 is connected between a first output terminal of the control circuit 100 and a control terminal of a first group of power devices in the DCDC converter; the second buffer 60 is connected between the second output of the control circuit 100 and the control terminals of the second set of power devices in the DCDC converter.
In the present embodiment, the control circuit 100 supplies control signals to the first group power device and the second group power device via the first buffer 50 and the second buffer 60 according to the comparison signal from the signal generating circuit 10, thereby controlling the on and off of the first group power device and the second group power device.
Based on the control circuit provided in the foregoing embodiment, the embodiment of the present application further provides a DCDC conversion circuit, where the DCDC conversion circuit includes: the control circuit and the DCDC converter provided by the embodiment are connected with the control end of the power device in the DCDC converter.
In a possible implementation manner, please refer to fig. 5, which is a schematic block diagram of a DCDC conversion circuit provided in this embodiment of the present application, as shown in fig. 5, a first output end of the control unit 20 is connected to a gate of the first group of power devices 70, a second output end of the control unit 20 is connected to a gate of the second group of power devices 80, a source electrode of each first power device in the first group of power devices 70 is connected to an input voltage VIN, a drain electrode of each first power device in the first group of power devices 70 is connected to a drain electrode of one second power device in the second group of power devices 80, a source electrode of each second power device in the second group of power devices 80 is connected to GND, and a connection point of the first power devices and the second power devices is used as an output end of the DCDC conversion circuit. The first group of power devices 70 are PMOS transistors, and the second group of power devices 80 are NMOS transistors.
It should be noted that, the signal generating circuit 10, the control unit 20, the first group of power devices 70 and the second group of power devices 80 may be integrated in a chip, the input port VIN, the enable port EN, the ground port GND, the output port SW, and the feedback port FB may be reserved on the chip, and an off-chip RC element may be omitted when the integrated in the chip, thereby reducing the cost and improving the integration level.
The foregoing is merely illustrative of embodiments of the present utility model, and the present utility model is not limited thereto, and any changes or substitutions can be easily made by those skilled in the art within the technical scope of the present utility model, and the present utility model is intended to be covered by the present utility model. Therefore, the protection scope of the utility model is subject to the protection scope of the claims.
Claims (10)
1. A signal generation circuit, the signal generation circuit comprising: the device comprises an error correction module, a ripple injection module and a summation comparator;
the first input end of the error correction module is connected with a reference power supply, the second input end of the error correction module is connected with the voltage output end of the DCDC converter, the output end of the error correction module is connected with the first positive input end of the summation comparator, and the second positive input end of the summation comparator is connected with the reference power supply;
the input end of the ripple injection module is connected with the first output end of the control unit corresponding to the DCDC converter, the output end of the ripple injection module is connected with the first negative input end of the summation comparator, the second negative input end of the summation comparator is connected with the voltage output end of the DCDC converter, and the output end of the summation comparator is connected with the input end of the control unit.
2. The signal generation circuit of claim 1, wherein the signal generation circuit further comprises: a maladjustment elimination module;
wherein the offset cancellation module is connected to a third positive input of the summing comparator.
3. The signal generation circuit of claim 1, wherein the ripple injection module comprises: an integrator and an operational transconductance amplifier;
the input end of the integrator is used as the input end of the ripple injection module, the first output end of the integrator is connected with the first input end of the operational transconductance amplifier, the second output end of the integrator is connected with the second input end of the operational transconductance amplifier, and the output end of the operational transconductance amplifier is used as the output end of the ripple injection module.
4. The signal generating circuit according to claim 3, wherein the integrator comprises: a first transistor, a second transistor, an inverter, a first resistor, a second resistor, a first capacitor, and a second capacitor;
the grid electrode of the first transistor and the input end of the inverter are connected to serve as the input end of the integrator, the output end of the inverter is connected to the grid electrode of the second transistor, the source electrode of the first transistor and the source electrode of the second transistor are connected with first bias current, the drain electrode of the second transistor is respectively connected with one end of the first resistor, one end of the first capacitor and one end of the second resistor, the connection point of the drain electrode of the second transistor is used as the first output end of the integrator, one end of the second resistor is connected with one end of the second capacitor to serve as the second input end of the integrator, and the drain electrode of the first transistor, the other end of the first resistor, the other end of the first capacitor and the other end of the second capacitor are grounded.
5. The signal generation circuit of claim 3, wherein the operational transconductance amplifier comprises: the first current mirror, the second current mirror, the third current mirror, the fourth current mirror and the differential voltage comparison unit;
the input end of the first current mirror is connected with a second bias current, the output end of the first current mirror is connected with the current input end of the differential voltage comparison unit, the first voltage input end of the differential voltage comparison unit is used as the first input end of the operational transconductance amplifier, the second voltage input end of the differential voltage comparison unit is used as the second input end of the operational transconductance amplifier, the first output end of the differential voltage comparison unit is connected with the input end of the second current mirror, the second output end of the differential voltage comparison unit is connected with the input end of the third current mirror, the output end of the third current mirror is connected with the input end of the fourth current mirror, and the output end of the second current mirror and the output end of the fourth current mirror are connected to serve as the output end of the operational transconductance amplifier.
6. A control circuit, the control circuit comprising: a signal generating circuit and control unit as claimed in any one of claims 1 to 5;
the signal generating circuit is connected with the input end of the control unit, and the output end of the control unit is connected with the control end of the power device in the DCDC converter.
7. The control circuit of claim 6, wherein the control circuit further comprises: an on-time timer;
the on-time timer is connected with the control unit.
8. The control circuit of claim 6, wherein the control circuit further comprises: a minimum off-time timer;
the minimum off-time timer is connected to the control unit.
9. The control circuit of claim 6, wherein the control circuit further comprises: a first buffer and a second buffer;
the first buffer is connected between a first output end of the control unit and a control end of a first group of power devices in the DCDC converter;
the second buffer is connected between the second output end of the control unit and the control end of the second group of power devices in the DCDC converter.
10. A DCDC conversion circuit, characterized in that the DCDC conversion circuit comprises: control circuit and DCDC converter according to any of claims 6-9;
the control circuit is connected with the control end of the power device in the DCDC converter.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202321767834.6U CN220368701U (en) | 2023-07-06 | 2023-07-06 | Signal generation circuit, control circuit and DCDC conversion circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202321767834.6U CN220368701U (en) | 2023-07-06 | 2023-07-06 | Signal generation circuit, control circuit and DCDC conversion circuit |
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| Publication Number | Publication Date |
|---|---|
| CN220368701U true CN220368701U (en) | 2024-01-19 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202321767834.6U Active CN220368701U (en) | 2023-07-06 | 2023-07-06 | Signal generation circuit, control circuit and DCDC conversion circuit |
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| Country | Link |
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| CN (1) | CN220368701U (en) |
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- 2023-07-06 CN CN202321767834.6U patent/CN220368701U/en active Active
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