CN220359208U - Electronic tuner circuit capable of receiving wired signal and wireless signal - Google Patents
Electronic tuner circuit capable of receiving wired signal and wireless signal Download PDFInfo
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- CN220359208U CN220359208U CN202322010359.4U CN202322010359U CN220359208U CN 220359208 U CN220359208 U CN 220359208U CN 202322010359 U CN202322010359 U CN 202322010359U CN 220359208 U CN220359208 U CN 220359208U
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Abstract
The utility model provides an electronic tuner circuit capable of receiving wired signals and wireless signals, which comprises a power supply voltage adjustment power supply circuit, wherein the input end of the power supply voltage adjustment power supply circuit is connected with a 1.2V bias voltage source, a 1.8V bias voltage source and a 3.3V bias voltage source, the power supply voltage adjustment power supply circuit is in power supply connection with a wired signal receiving and processing circuit, a wireless signal receiving and processing circuit and a signal demodulation and processing circuit, the input end of the wired signal receiving and processing circuit is connected with a wired signal source, the input end of the wireless signal receiving and processing circuit can receive wireless signals, the output end of the wired signal receiving and processing circuit and the output end of the wireless signal receiving and processing circuit are connected with the input end of a signal demodulation and processing circuit, and the output end of the signal demodulation and processing circuit is connected with the input end of a television main board. The beneficial effects of the utility model are as follows: the system can realize standard system ATSC3.0 and is downward compatible with ATSC1.0 system, and can receive wireless satellite signals and cable signals.
Description
Technical Field
The utility model relates to the technical field of electronic circuits, in particular to an electronic tuner circuit capable of receiving wired signals and wireless signals.
Background
ATSC3.0 is the latest version of the advanced television systems committee standard, a major upgrade to antenna television, designed to support 4K resolution. However, the functions of the ATSC3.0 electronic tuners on the market are uneven, and some electronic tuners are half tuners with signals of one system and two systems, and the functions are single. Some electronic tuners are designed only for ATSC3.0, cannot be well compatible with the old standard signals, and therefore, some television mainboards can only be redesigned, and manpower and material resources are wasted; there are also arbitrary design frameworks for electronic tuners, which not only do not play a role in shielding, but also affect the output of radio frequencies. The electronic tuners currently on the market mainly include the following: an electronic tuner that can only receive satellite signals; an electronic tuner that can only receive a wired signal; the electronic tuner capable of receiving satellite signals and cable signals, but a special demodulation chip is reserved on the television main board.
Disclosure of Invention
In order to solve the problems in the prior art, the utility model provides an electronic tuner circuit capable of receiving a wired signal and a wireless signal, which can realize standard ATSC3.0 and downward compatibility with ATSC1.0 and other standards, can not only receive a wireless satellite signal, but also synchronously receive the wired signal, and solves the problems of single function and poor demodulation capability of the ATSC3.0 electronic tuner in the prior art.
The utility model provides an electronic tuner circuit capable of receiving wired signals and wireless signals, which is arranged in an electronic tuner, wherein the electronic coordinator is provided with a wrapping shielding layer consisting of an upper cover, a lower cover and a main body frame, and the electronic tuner comprises a wired signal receiving and processing circuit, a wireless signal receiving and processing circuit, a power supply voltage adjusting and supplying circuit and a signal demodulation and processing circuit, wherein the input end of the power supply voltage adjusting and supplying circuit is connected with a 1.2V bias voltage source, a 1.8V bias voltage source and a 3.3V bias voltage source, the output end of the power supply voltage adjusting and supplying circuit is in power supply connection with the wired signal receiving and processing circuit, the wireless signal receiving and processing circuit and the signal demodulation and processing circuit, the input end of the wired signal receiving and processing circuit is connected with a wired signal source, the output end of the wired signal receiving and processing circuit and the output end of the wireless signal receiving and processing circuit are connected with the input end of the signal demodulation and processing circuit, the output end of the signal demodulation and processing circuit is connected with the input end of the television, and the output end of the signal demodulation and processing circuit is capable of directly processing the audio and video signals of the main board after the audio and video signals are received and processed by the wireless signal receiving and processing circuit.
The utility model further improves, a signal demodulation chip U3, a crystal oscillator X100, a capacitor C41 and a capacitor C42 are arranged in the signal demodulation processing circuit, wherein the signal demodulation chip U3 is provided with 49 pins, pins 5, 18 and 28 of the signal demodulation chip U3 are connected with the output end of the power supply voltage adjustment power supply circuit, pin 42 of the signal demodulation chip U3 is connected with one end of the capacitor C41, pin 43 of the signal demodulation chip U3 is connected with one end of the capacitor C42, the other end of the capacitor C41 and the other end of the capacitor C42 are connected with the output end of the wired signal receiving processing circuit and the output end of the wireless signal receiving processing circuit, pins 35 and 36 of the signal demodulation chip U3 are respectively connected with two ends of the crystal oscillator X100, and pins 8, 10, 14, 15, 17, 19, 20, 21, 22, 23 and 24 of the signal demodulation chip U3 are connected with the input end of a main board of a television.
The utility model further improves, the wired signal receiving and processing circuit is provided with a wired signal processing chip U2, a capacitor C49 and a capacitor C51, wherein the wired signal processing chip U2 is provided with 29 pins, pins 6, 10, 20, 21 and 26 of the wired signal processing chip U2 are connected with the output end of the power supply voltage adjusting and supplying circuit, pins 23 and 24 of the wired signal processing chip U2 are connected with a wired signal source, pin 12 of the wired signal processing chip U2 is connected with one end of the capacitor C51, the other end of the capacitor C51 is connected with the other end of the capacitor C42, pin 13 of the wired signal processing chip U2 is connected with one end of the capacitor C49, and the other end of the capacitor C49 is connected with the other end of the capacitor C41.
The utility model is further improved, the wireless signal receiving and processing circuit is provided with a wireless signal processing chip U1 and a crystal oscillator X1, wherein the wireless signal processing chip U1 is provided with 29 pins, pins 6, 8, 10, 14, 20 and 21 of the wireless signal processing chip U1 are connected with the output end of the power supply voltage adjusting and power supply circuit, pins 23 and 24 of the wireless signal processing chip U1 can receive wireless signals, pin 12 of the wireless signal processing chip U1 is connected with the other end of a capacitor C42, pin 13 of the wireless signal processing chip U1 is connected with the other end of a capacitor C41, and pins 17 and 18 of the wireless signal processing chip U1 are respectively connected with two ends of the crystal oscillator X1.
The utility model further improves, the power supply voltage regulation power supply circuit is provided with a pin arrangement interface CON12, a pin arrangement interface CON16 and a voltage regulation chip U101, wherein the voltage regulation chip U101 is provided with 6 pins, pins A2 and C2 of the voltage regulation chip U101 are connected with a 1.2V bias voltage source and a 3.3V bias voltage source through the pin arrangement interface CON16, a pin A1 of the voltage regulation chip U101 is connected with pins 5, 18 and 28 of the signal demodulation chip U3, the input end of the pin arrangement interface CON12 is connected with a 1.8V bias voltage source and a 3.3V bias voltage source, the output end of the pin arrangement interface CON12 is connected with pins 6, 10, 20, 21 and 26 of the wired signal processing chip U2, and the output end of the pin arrangement interface CON12 is connected with pins 6, 8, 10, 14, 20 and 21 of the wireless signal processing chip U1.
The utility model is further improved, and the model of the signal demodulation chip U3 is CXD2878AER.
The utility model is further improved, and the model of the wired signal processing chip U2 is SI2190-B30-ZM7R.
The utility model is further improved, and the model of the wireless signal processing chip U1 is SI2190-B30-ZM7R.
The utility model is further improved, and the model of the voltage regulating chip U101 is RT9085AWSC.
The utility model is further improved, and the audio/video signal formats output to the television main board by the signal demodulation chip U3 comprise ATSC3.0, ATSC1.0 and DVB-T2/T, DVB-C2/C.
Compared with the prior art, the utility model has the beneficial effects that: the electronic tuner circuit can receive the wired signals and the wireless signals, and through the wired signal receiving and processing circuit, the wireless signal receiving and processing circuit, the power supply voltage adjusting and supplying circuit and the signal demodulation and processing circuit which are matched with each other, the signal demodulation and processing circuit can receive the signals processed by the wired signal receiving and processing circuit and the wireless signal receiving and processing circuit and demodulate the signals into audio and video signals which can be directly played by a television main board, standard ATSC3.0 and downward compatible ATSC1.0 and other standard can be realized, not only wireless satellite signals can be received, but also the wired signals can be synchronously received, CXD2878AER also has strong demodulation capability, so that the electronic tuner can be directly used by the television main board, and the modulation and demodulation are integrated on one module, and the use is more convenient; the wrapped shielding layer is manufactured in a mode of an upper cover, a lower cover and a frame, and aims to facilitate ultra-large batch production and better anti-interference capability, improve production efficiency and production safety and solve the problems of single function and poor demodulation capability of an ATSC3.0 electronic tuner in the prior art.
Drawings
For a clearer description of the present application or of the solutions of the prior art, a brief introduction will be given below to the drawings used in the description of the embodiments or of the prior art, it being apparent that the drawings in the description below are some embodiments of the present application, from which other drawings can be obtained, without the inventive effort for a person skilled in the art.
FIG. 1 is a circuit diagram of an electronic tuner circuit capable of receiving both wired and wireless signals in accordance with the present utility model;
fig. 2 is a circuit diagram of a power supply voltage adjustment power supply circuit of the present utility model.
Detailed Description
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs; the terminology used in the description of the applications herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application; the terms "comprising" and "having" and any variations thereof in the description and claims of the present application and in the description of the figures above are intended to cover non-exclusive inclusions. The terms first, second and the like in the description and in the claims or in the above-described figures, are used for distinguishing between different objects and not necessarily for describing a sequential or chronological order.
Reference herein to "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment may be included in at least one embodiment of the present application. The appearances of such phrases in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive of other embodiments. Those of skill in the art will explicitly and implicitly appreciate that the embodiments described herein may be combined with other embodiments.
In order to better understand the technical solutions of the present application, the following description will clearly and completely describe the technical solutions in the embodiments of the present application with reference to the accompanying drawings.
As shown in fig. 1-2, the electronic tuner circuit capable of receiving wired signals and wireless signals is arranged in the electronic tuner, the electronic coordinator is provided with a wrapping shielding layer consisting of an upper cover, a lower cover and a main body frame, the electronic tuner comprises a wired signal receiving and processing circuit, a wireless signal receiving and processing circuit, a power supply voltage adjusting and supplying circuit and a signal demodulation and processing circuit, the input end of the power supply voltage adjusting and supplying circuit is connected with a 1.2V bias voltage source, a 1.8V bias voltage source and a 3.3V bias voltage source, the output end of the power supply voltage adjusting and supplying circuit is in power supply connection with the wired signal receiving and processing circuit, the wireless signal receiving and processing circuit and the signal demodulation and processing circuit, the input end of the wired signal receiving and processing circuit can receive wireless signals, the output end of the wired signal receiving and processing circuit and the output end of the wireless signal receiving and processing circuit are connected with the input end of the signal demodulation and processing circuit, and the output end of the signal demodulation and processing circuit is connected with the input end of a television main board. In this embodiment, the signal demodulation processing circuit can receive the signals processed by the wired signal receiving processing circuit and the wireless signal receiving processing circuit and demodulate the signals into audio and video signals which can be directly played by the television main board, and can realize standard standards of ATSC3.0 and downward compatibility of standards of ATSC1.0, so that not only can wireless satellite signals be received, but also the wired signals can be synchronously received, and modulation and demodulation are integrated on one module, so that the use is more convenient; the upper cover, the lower cover and the frame are adopted to manufacture the wrapped shielding layer, so that the purpose is to facilitate ultra-large batch production and better anti-interference capability, and the production efficiency and the production safety are improved.
As shown in FIG. 1, a signal demodulation chip U3, a crystal oscillator X100, a capacitor C41 and a capacitor C42 are arranged in the signal demodulation processing circuit, wherein the signal demodulation chip U3 is provided with 49 pins, pins 5, 18 and 28 of the signal demodulation chip U3 are connected with the output end of a power supply voltage adjustment power supply circuit, pin 42 of the signal demodulation chip U3 is connected with one end of the capacitor C41, pin 43 of the signal demodulation chip U3 is connected with one end of the capacitor C42, the other end of the capacitor C41 and the other end of the capacitor C42 are connected with the output end of a wired signal receiving processing circuit and the output end of a wireless signal receiving processing circuit, pins 35 and 36 of the signal demodulation chip U3 are respectively connected with two ends of the crystal oscillator X100, and pins 8, 10, 14, 15, 17, 19, 20, 21, 22, 23 and 24 of the signal demodulation chip U3 are connected with the input end of a television mainboard. In this embodiment, the model of the signal demodulation chip U3 is CXD2878AER, and the signal demodulation chip U3 CXD2878AER has a strong demodulation capability, so that the electronic tuner can be directly used on the television main board, and the audio/video signal format output from the signal demodulation chip U3 to the television main board includes ATSC3.0, ATSC1.0, DVB-T2/T, DVB-C2/C.
As shown in fig. 1, the wired signal receiving and processing circuit is provided with a wired signal processing chip U2, a capacitor C49 and a capacitor C51, wherein the wired signal processing chip U2 is provided with 29 pins, pins 6, 10, 20, 21 and 26 of the wired signal processing chip U2 are connected with the output end of the power supply voltage adjusting and supplying circuit, pins 23 and 24 of the wired signal processing chip U2 are connected with a wired signal source, pin 12 of the wired signal processing chip U2 is connected with one end of the capacitor C51, the other end of the capacitor C51 is connected with the other end of the capacitor C42, pin 13 of the wired signal processing chip U2 is connected with one end of the capacitor C49, and the other end of the capacitor C49 is connected with the other end of the capacitor C41; the model of the wired signal processing chip U2 is SI2190-B30-ZM7R. In this embodiment, when a wired signal is received, the wired signal processing chip U2 performs basic processing, the wired signal processing chip U2 and the wireless signal processing chip U1 share the 24MHz crystal oscillator X1 to perform oscillation starting operation, the wired signal processing chip U2 performs operation by supplying power to 3.3V and 1.8V voltages provided by the power supply voltage adjustment power supply circuit, and the processed signal is transmitted to the signal demodulation chip U3 to receive and demodulate a television signal.
As shown in fig. 1, the wireless signal receiving and processing circuit is provided with a wireless signal processing chip U1 and a crystal oscillator X1, wherein the wireless signal processing chip U1 is provided with 29 pins, pins 6, 8, 10, 14, 20 and 21 of the wireless signal processing chip U1 are connected with the output end of the power supply voltage adjusting and supplying circuit, pins 23 and 24 of the wireless signal processing chip U1 can receive wireless signals, pin 12 of the wireless signal processing chip U1 is connected with the other end of the capacitor C42, pin 13 of the wireless signal processing chip U1 is connected with the other end of the capacitor C41, and pins 17 and 18 of the wireless signal processing chip U1 are respectively connected with two ends of the crystal oscillator X1. In this embodiment, the model of the wireless signal processing chip U1 is SI2190-B30-ZM7R, when a wireless signal is received, the wireless signal processing chip U1 performs basic processing, the wireless signal processing chip U1 is externally connected with a 24MHz crystal oscillator X1, the wireless signal processing chip U1 is powered by 3.3V and 1.8V voltages provided by a power supply voltage adjustment power supply circuit to operate, and the processed signal is transmitted to the signal demodulation chip U3 to receive and demodulate a television signal.
As shown in fig. 2, the power supply voltage adjustment power supply circuit is provided with a pin arrangement interface CON12, a pin arrangement interface CON16 and a voltage adjustment chip U101, wherein the voltage adjustment chip U101 is provided with 6 pins, pins A2 and C2 of the voltage adjustment chip U101 are connected with a 1.2V bias voltage source and a 3.3V bias voltage source through the pin arrangement interface CON16, pin A1 of the voltage adjustment chip U101 is connected with pins 5, 18 and 28 of the signal demodulation chip U3, an input end of the pin arrangement interface CON12 is connected with a 1.8V bias voltage source and a 3.3V bias voltage source, an output end of the pin arrangement interface CON12 is connected with pins 6, 10, 20, 21 and 26 of the wired signal processing chip U2, and an output end of the pin arrangement interface CON12 is connected with pins 6, 8, 10, 14, 20 and 21 of the wireless signal processing chip U1. In this embodiment, the voltage adjustment chip U101 is of the type RT9085AWSC, the signal demodulation chip U3 is externally connected with the 24MHz crystal oscillator X100, the 3.3V and 1.0V voltages provided by the voltage adjustment chip U101 are operated, and since the 1.0V voltage cannot be generated under normal conditions, the voltage adjustment chip U101 is required to convert 1.2V into 1.0V voltage, and the signal demodulation chip U3 performs demodulation processing on the received signal.
As can be seen from the above, the utility model provides an electronic tuner circuit capable of receiving a wired signal and a wireless signal, which is capable of receiving the signal processed by the wired signal receiving processing circuit and the wireless signal receiving processing circuit and demodulating the signal processed by the wireless signal receiving processing circuit into an audio/video signal which can be directly played by a television main board through the wired signal receiving processing circuit, the wireless signal receiving processing circuit, the power supply voltage adjusting and supplying circuit and the signal demodulating processing circuit which are mutually matched, and is capable of realizing standard ATSC3.0 and downward compatible with ATSC1.0 and other standard, not only can receive a wireless satellite signal, but also can synchronously receive the wired signal, CXD2878AER also has strong demodulating capability, so that the electronic tuner can be directly used by the television main board, and modulation and demodulation are integrated on a module, thereby being more convenient to use; the wrapped shielding layer is manufactured in a mode of an upper cover, a lower cover and a frame, and aims to facilitate ultra-large batch production and better anti-interference capability, improve production efficiency and production safety and solve the problems of single function and poor demodulation capability of an ATSC3.0 electronic tuner in the prior art.
The above embodiments are preferred embodiments of the present utility model, and are not intended to limit the scope of the present utility model, which includes but is not limited to the embodiments, and equivalent modifications according to the present utility model are within the scope of the present utility model.
Claims (10)
1. An electronic tuner circuit capable of receiving wired signals and wireless signals is arranged in an electronic tuner, and the electronic tuner is provided with a wrapped shielding layer consisting of an upper cover, a lower cover and a main body frame, and is characterized in that: the wireless signal receiving and processing circuit comprises a wired signal receiving and processing circuit, a wireless signal receiving and processing circuit, a power supply voltage adjusting and power supply circuit and a signal demodulation processing circuit, wherein the input end of the power supply voltage adjusting and power supply circuit is connected with a 1.2V bias voltage source, a 1.8V bias voltage source and a 3.3V bias voltage source, the output end of the power supply voltage adjusting and power supply circuit is connected with the wired signal receiving and processing circuit, the wireless signal receiving and processing circuit is connected with the power supply of the signal demodulation processing circuit, the input end of the wired signal receiving and processing circuit is connected with the wired signal source, the output end of the wireless signal receiving and processing circuit is connected with the input end of the signal demodulation processing circuit, and the signal demodulation processing circuit can receive the signals processed by the wired signal receiving and processing circuit and demodulate the signals into audio and video signals which can be directly played by the television main board.
2. The electronic tuner circuit capable of receiving both wired and wireless signals as recited in claim 1, wherein: the signal demodulation processing circuit is internally provided with a signal demodulation chip U3, a crystal oscillator X100, a capacitor C41 and a capacitor C42, wherein the signal demodulation chip U3 is provided with 49 pins, pins 5, 18 and 28 of the signal demodulation chip U3 are connected with the output end of the power supply voltage adjustment power supply circuit, pin 42 of the signal demodulation chip U3 is connected with one end of the capacitor C41, pin 43 of the signal demodulation chip U3 is connected with one end of the capacitor C42, the other end of the capacitor C41 and the other end of the capacitor C42 are connected with the output end of the wired signal receiving processing circuit and the output end of the wireless signal receiving processing circuit, pins 35 and 36 of the signal demodulation chip U3 are respectively connected with two ends of the crystal oscillator X100, and pins 8, 10, 14, 15, 17, 19, 20, 21, 22, 23 and 24 of the signal demodulation chip U3 are connected with the input end of a television mainboard.
3. The electronic tuner circuit capable of receiving both wired and wireless signals as recited in claim 2, wherein: the wired signal receiving and processing circuit is provided with a wired signal processing chip U2, a capacitor C49 and a capacitor C51, wherein the wired signal processing chip U2 is provided with 29 pins, pins 6, 10, 20, 21 and 26 of the wired signal processing chip U2 are connected with the output end of the power supply voltage adjusting and power supply circuit, pins 23 and 24 of the wired signal processing chip U2 are connected with a wired signal source, pin 12 of the wired signal processing chip U2 is connected with one end of the capacitor C51, the other end of the capacitor C51 is connected with the other end of the capacitor C42, pin 13 of the wired signal processing chip U2 is connected with one end of the capacitor C49, and the other end of the capacitor C49 is connected with the other end of the capacitor C41.
4. The electronic tuner circuit capable of receiving both wired and wireless signals as recited in claim 3, wherein: the wireless signal receiving and processing circuit is provided with a wireless signal processing chip U1 and a crystal oscillator X1, wherein the wireless signal processing chip U1 is provided with 29 pins, pins 6, 8, 10, 14, 20 and 21 of the wireless signal processing chip U1 are connected with the output end of the power supply voltage adjusting and power supply circuit, pins 23 and 24 of the wireless signal processing chip U1 can receive wireless signals, pin 12 of the wireless signal processing chip U1 is connected with the other end of the capacitor C42, pin 13 of the wireless signal processing chip U1 is connected with the other end of the capacitor C41, and pins 17 and 18 of the wireless signal processing chip U1 are respectively connected with two ends of the crystal oscillator X1.
5. The electronic tuner circuit capable of receiving both wired and wireless signals as recited in claim 4, wherein: the power supply voltage adjustment power supply circuit is provided with a pin arrangement interface CON12, a pin arrangement interface CON16 and a voltage adjustment chip U101, wherein the voltage adjustment chip U101 is provided with 6 pins, pins A2 and C2 of the voltage adjustment chip U101 are connected with a 1.2V bias voltage source and a 3.3V bias voltage source through the pin arrangement interface CON16, a pin A1 of the voltage adjustment chip U101 is connected with pins 5, 18 and 28 of the signal demodulation chip U3, the input end of the pin arrangement interface CON12 is connected with a 1.8V bias voltage source and a 3.3V bias voltage source, the output end of the pin arrangement interface CON12 is connected with pins 6, 10, 20, 21 and 26 of the wired signal processing chip U2, and the output end of the pin arrangement interface CON12 is connected with pins 6, 8, 10, 14, 20 and 21 of the wireless signal processing chip U1.
6. The electronic tuner circuit capable of receiving both wired and wireless signals as recited in claim 5, wherein: the model of the signal demodulation chip U3 is CXD2878AER.
7. The electronic tuner circuit capable of receiving both wired and wireless signals as recited in claim 6, wherein: the model of the wired signal processing chip U2 is SI2190-B30-ZM7R.
8. The electronic tuner circuit capable of receiving both wired and wireless signals as recited in claim 7, wherein: the model of the wireless signal processing chip U1 is SI2190-B30-ZM7R.
9. The electronic tuner circuit capable of receiving both wired and wireless signals as recited in claim 8, wherein: the voltage regulation chip U101 is of the model RT9085AWSC.
10. The electronic tuner circuit capable of receiving both wired and wireless signals as recited in claim 9, wherein: the audio/video signal formats output to the television mainboard by the signal demodulation chip U3 comprise ATSC3.0, ATSC1.0 and DVB-T2/T, DVB-C2/C.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202322010359.4U CN220359208U (en) | 2023-07-28 | 2023-07-28 | Electronic tuner circuit capable of receiving wired signal and wireless signal |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202322010359.4U CN220359208U (en) | 2023-07-28 | 2023-07-28 | Electronic tuner circuit capable of receiving wired signal and wireless signal |
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| Publication Number | Publication Date |
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| CN220359208U true CN220359208U (en) | 2024-01-16 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202322010359.4U Active CN220359208U (en) | 2023-07-28 | 2023-07-28 | Electronic tuner circuit capable of receiving wired signal and wireless signal |
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| Country | Link |
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| CN (1) | CN220359208U (en) |
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2023
- 2023-07-28 CN CN202322010359.4U patent/CN220359208U/en active Active
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Denomination of utility model: An electronic tuner circuit capable of receiving wired and wireless signals Granted publication date: 20240116 Pledgee: Shenzhen hi tech investment small loan Co.,Ltd. Pledgor: CHINA DRAGON TECHNOLOGY CO.,LTD. Registration number: Y2024980008731 |
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